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// (C) 2001-2017 Intel Corporation. All rights reserved.
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// Your use of Intel Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files from any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Intel Program License Subscription
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// Agreement, Intel FPGA IP License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Intel and sold by
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// Intel or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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// $Id: //acds/rel/17.1std/ip/merlin/altera_merlin_traffic_limiter/altera_merlin_reorder_memory.sv#1 $
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// $Revision: #1 $
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// $Date: 2017/07/30 $
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// $Author: swbranch $
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// ------------------------------------------------------------------
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// Merlin Order Memory: this stores responses from slave
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// and do reorder. The memory structure is normal memory
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// with many segments for different responses that master
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// can handle.
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// The number of segment is the number of MAX_OUTSTANDING_RESPONSE
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// ------------------------------------------------------------------
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`timescale 1 ns / 1 ns
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module altera_merlin_reorder_memory
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#(
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parameter DATA_W = 32,
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ADDR_H_W = 4, // width to represent how many segments
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ADDR_L_W = 4,
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VALID_W = 4,
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NUM_SEGMENT = 4,
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DEPTH = 16
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)
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(
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// -------------------
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// Clock
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// -------------------
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input clk,
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input reset,
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// -------------------
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// Signals
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// -------------------
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input [DATA_W - 1 : 0] in_data,
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input in_valid,
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output in_ready,
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output reg [DATA_W - 1 : 0] out_data,
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output reg out_valid,
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input out_ready,
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// --------------------------------------------
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// wr_segment: select write portion of memory
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// rd_segment: select read portion of memory
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// --------------------------------------------
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input [ADDR_H_W - 1 : 0] wr_segment,
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input [ADDR_H_W - 1 : 0] rd_segment
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);
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// -------------------------------------
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// Local parameter
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// -------------------------------------
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localparam SEGMENT_W = ADDR_H_W;
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wire [ADDR_H_W + ADDR_L_W - 1 : 0] mem_wr_addr;
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reg [ADDR_H_W + ADDR_L_W - 1 : 0] mem_rd_addr;
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wire [ADDR_L_W - 1 : 0] mem_wr_ptr;
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wire [ADDR_L_W - 1 : 0] mem_rd_ptr;
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reg [ADDR_L_W - 1 : 0] mem_next_rd_ptr;
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reg [DATA_W - 1 : 0] out_payload;
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wire [NUM_SEGMENT - 1 : 0] pointer_ctrl_in_ready;
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wire [NUM_SEGMENT - 1 : 0] pointer_ctrl_in_valid;
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wire [NUM_SEGMENT - 1 : 0] pointer_ctrl_out_valid;
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wire [NUM_SEGMENT - 1 : 0] pointer_ctrl_out_ready;
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wire [ADDR_L_W - 1 : 0] pointer_ctrl_wr_ptr [NUM_SEGMENT];
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wire [ADDR_L_W - 1 : 0] pointer_ctrl_rd_ptr [NUM_SEGMENT];
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wire [ADDR_L_W - 1 : 0] pointer_ctrl_next_rd_ptr [NUM_SEGMENT];
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// ---------------------------------
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// Memory storage
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// ---------------------------------
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(* ramstyle="no_rw_check" *) reg [DATA_W - 1 : 0] mem [DEPTH - 1 : 0];
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always @(posedge clk) begin
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if (in_valid && in_ready)
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mem[mem_wr_addr] = in_data;
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out_payload = mem[mem_rd_addr];
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end
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//assign mem_rd_addr = {rd_segment, mem_next_rd_ptr};
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always_comb
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begin
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out_data = out_payload;
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out_valid = pointer_ctrl_out_valid[rd_segment];
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end
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// ---------------------------------
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// Memory addresses
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// ---------------------------------
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assign mem_wr_ptr = pointer_ctrl_wr_ptr[wr_segment];
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//assign mem_rd_ptr = pointer_ctrl_rd_ptr[rd_segment];
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//assign mem_next_rd_ptr = pointer_ctrl_next_rd_ptr[rd_segment];
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assign mem_wr_addr = {wr_segment, mem_wr_ptr};
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// ---------------------------------------------------------------------------
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// Bcos want, empty latency, mean assert read the data will appear on out_data.
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// And need to jump around different segment of the memory.
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// So when seeing endofpacket for this current segment, the read address
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// will jump to next segment at first read address, so that the data will be ready
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// it is okay to jump to next segment as this is the sequence of all transaction
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// and they just increment. (standing at segment 0, then for sure next segment 1)
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// ----------------------------------------------------------------------------
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wire endofpacket;
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assign endofpacket = out_payload[0];
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wire [ADDR_H_W - 1: 0] next_rd_segment;
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assign next_rd_segment = ((rd_segment + 1'b1) == NUM_SEGMENT) ? '0 : rd_segment + 1'b1;
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always_comb
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begin
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if (out_valid && out_ready && endofpacket)
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begin
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mem_next_rd_ptr = pointer_ctrl_rd_ptr[next_rd_segment];
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//mem_rd_addr = {rd_segment + 1'b1, mem_next_rd_ptr};
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mem_rd_addr = {next_rd_segment, mem_next_rd_ptr};
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end
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else
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begin
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mem_next_rd_ptr = pointer_ctrl_next_rd_ptr[rd_segment];
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mem_rd_addr = {rd_segment, mem_next_rd_ptr};
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end
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end
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// ---------------------------------
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// Output signals
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// ---------------------------------
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assign in_ready = pointer_ctrl_in_ready[wr_segment];
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// ---------------------------------
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// Control signals for each segment
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// ---------------------------------
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genvar j;
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generate
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for (j = 0; j < NUM_SEGMENT; j = j + 1)
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begin : pointer_signal
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assign pointer_ctrl_in_valid[j] = (wr_segment == j) && in_valid;
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assign pointer_ctrl_out_ready[j] = (rd_segment == j) && out_ready;
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end
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endgenerate
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// ---------------------------------
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// Seperate write and read pointer
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// for each segment in memory
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// ---------------------------------
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genvar i;
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generate
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for (i = 0; i < NUM_SEGMENT; i = i + 1)
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begin : each_segment_pointer_controller
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memory_pointer_controller
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#(
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.ADDR_W (ADDR_L_W)
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) reorder_memory_pointer_controller
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(
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.clk (clk),
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.reset (reset),
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.in_ready (pointer_ctrl_in_ready[i]),
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.in_valid (pointer_ctrl_in_valid[i]),
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.out_ready (pointer_ctrl_out_ready[i]),
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.out_valid (pointer_ctrl_out_valid[i]),
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.wr_pointer (pointer_ctrl_wr_ptr[i]),
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.rd_pointer (pointer_ctrl_rd_ptr[i]),
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.next_rd_pointer (pointer_ctrl_next_rd_ptr[i])
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);
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end // block: each_segment_pointer_controller
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endgenerate
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endmodule
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module memory_pointer_controller
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#(
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parameter ADDR_W = 4
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)
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(
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// -------------------
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// Clock
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// -------------------
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input clk,
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input reset,
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// -------------------
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// Signals
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// -------------------
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output reg in_ready,
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input in_valid,
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input out_ready,
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output reg out_valid,
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// -------------------------------
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// Output write and read pointer
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// -------------------------------
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output [ADDR_W - 1 : 0] wr_pointer,
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output [ADDR_W - 1 : 0] rd_pointer,
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output [ADDR_W - 1 : 0] next_rd_pointer
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);
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reg [ADDR_W - 1 : 0] incremented_wr_ptr;
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reg [ADDR_W - 1 : 0] incremented_rd_ptr;
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reg [ADDR_W - 1 : 0] wr_ptr;
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reg [ADDR_W - 1 : 0] rd_ptr;
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reg [ADDR_W - 1 : 0] next_wr_ptr;
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reg [ADDR_W - 1 : 0] next_rd_ptr;
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reg full, empty, next_full, next_empty;
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reg read, write, internal_out_ready, internal_out_valid;
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assign incremented_wr_ptr = wr_ptr + 1'b1;
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assign incremented_rd_ptr = rd_ptr + 1'b1;
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assign next_wr_ptr = write ? incremented_wr_ptr : wr_ptr;
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assign next_rd_ptr = read ? incremented_rd_ptr : rd_ptr;
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assign wr_pointer = wr_ptr;
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assign rd_pointer = rd_ptr;
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assign next_rd_pointer = next_rd_ptr;
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// -------------------------------
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// Define write and read signals
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// --------------------------------
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// internal read, if it has any valid data
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// and output are ready to accepts data then a read will be performed.
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// -------------------------------
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//assign read = internal_out_ready && internal_out_valid;
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assign read = internal_out_ready && !empty;
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assign write = in_ready && in_valid;
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always_ff @(posedge clk or posedge reset)
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begin
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if (reset)
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begin
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wr_ptr <= 0;
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rd_ptr <= 0;
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end
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else
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begin
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wr_ptr <= next_wr_ptr;
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rd_ptr <= next_rd_ptr;
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end
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end
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// ---------------------------------------------------------------------------
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// Generate full/empty signal for memory
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// if read and next read pointer same as write, set empty, write will clear empty
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// if write and next write pointer same as read, set full, read will clear full
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// -----------------------------------------------------------------------------
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always_comb
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begin
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next_full = full;
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next_empty = empty;
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if (read && !write)
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begin
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next_full = 1'b0;
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if (incremented_rd_ptr == wr_ptr)
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next_empty = 1'b1;
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end
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if (write && !read)
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begin
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next_empty = 1'b0;
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if (incremented_wr_ptr == rd_ptr)
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next_full = 1'b1;
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end
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end // always_comb
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always_ff @(posedge clk or posedge reset)
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begin
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if (reset)
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begin
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empty <= 1;
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full <= 0;
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end
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else
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begin
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empty <= next_empty;
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full <= next_full;
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end
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end
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// --------------------
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// Control signals
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// --------------------
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always_comb
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begin
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in_ready = !full;
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out_valid = !empty;
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internal_out_ready = out_ready;
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end // always_comb
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endmodule
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