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//+FHDR------------------------------------------------------------------------
//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
//GLADIC Open Source RTL
//-----------------------------------------------------------------------------
//FILE NAME      :
//DEPARTMENT     : IC Design / Verification
//AUTHOR         : Felipe Fernandes da Costa
//AUTHOR’S EMAIL :
//-----------------------------------------------------------------------------
//RELEASE HISTORY
//VERSION DATE AUTHOR DESCRIPTION
//1.0 YYYY-MM-DD name
//-----------------------------------------------------------------------------
//KEYWORDS : General file searching keywords, leave blank if none.
//-----------------------------------------------------------------------------
//PURPOSE  : ECSS_E_ST_50_12C_31_july_2008
//-----------------------------------------------------------------------------
//PARAMETERS
//PARAM NAME            RANGE   : DESCRIPTION : DEFAULT : UNITS
//e.g.DATA_WIDTH        [32,16] : width of the data : 32:
//-----------------------------------------------------------------------------
//REUSE ISSUES
//Reset Strategy        :
//Clock Domains         :
//Critical Timing       :
//Test Features         :
//Asynchronous I/F      :
//Scan Methodology      :
//Instantiations        :
//Synthesizable (y/n)   :
//Other                 :
//-FHDR------------------------------------------------------------------------
module fifo_tx
#(
        parameter integer DWIDTH = 9,
        parameter integer AWIDTH = 6
)
 
(
        input clock, reset, wr_en, rd_en,
        input [DWIDTH-1:0] data_in,
        output reg f_full,write_tx,f_empty,
        output reg [DWIDTH-1:0] data_out,
        output reg [AWIDTH-1:0] counter
);
 
        reg [DWIDTH-1:0] mem [0:2**AWIDTH-1];
 
        reg [AWIDTH-1:0] wr_ptr;
        reg [AWIDTH-1:0] rd_ptr;
 
        reg  [1:0] state_data_write;
        reg  [1:0] next_state_data_write;
 
        reg  [1:0] state_data_read;
        reg  [1:0] next_state_data_read;
 
/****************************************/
 
always@(*)
begin
        next_state_data_write = state_data_write;
 
        case(state_data_write)
        2'd0:
        begin
                if(wr_en && !f_full)
                begin
                        next_state_data_write = 2'd1;
                end
                else
                begin
                        next_state_data_write = 2'd0;
                end
        end
        2'd1:
        begin
                if(wr_en)
                begin
                        next_state_data_write = 2'd1;
                end
                else
                begin
                        next_state_data_write = 2'd2;
                end
        end
        2'd2:
        begin
                next_state_data_write = 2'd0;
        end
        default:
        begin
                next_state_data_write = 2'd0;
        end
        endcase
end
 
/****************************************/
 
always@(*)
begin
        next_state_data_read = state_data_read;
 
        case(state_data_read)
        2'd0:
        begin
                if(rd_en && !f_empty)
                begin
                        next_state_data_read = 2'd1;
                end
                else
                begin
                        next_state_data_read = 2'd0;
                end
        end
        2'd1:
        begin
                if(rd_en)
                begin
                        next_state_data_read = 2'd1;
                end
                else
                begin
                        next_state_data_read = 2'd2;
                end
        end
        2'd2:
        begin
                next_state_data_read = 2'd0;
        end
        default:
        begin
                next_state_data_read = 2'd0;
        end
        endcase
end
 
//Write pointer
        always@(posedge clock or negedge reset)
        begin
                if (!reset)
                begin
                        mem[0]  <= {(DWIDTH){1'b0}};
                        mem[1]  <= {(DWIDTH){1'b0}};
                        mem[2]  <= {(DWIDTH){1'b0}};
                        mem[3]  <= {(DWIDTH){1'b0}};
                        mem[4]  <= {(DWIDTH){1'b0}};
                        mem[5]  <= {(DWIDTH){1'b0}};
                        mem[6]  <= {(DWIDTH){1'b0}};
                        mem[7]  <= {(DWIDTH){1'b0}};
                        mem[8]  <= {(DWIDTH){1'b0}};
                        mem[9]  <= {(DWIDTH){1'b0}};
                        mem[10] <= {(DWIDTH){1'b0}};
 
                        mem[11] <= {(DWIDTH){1'b0}};
                        mem[12] <= {(DWIDTH){1'b0}};
                        mem[13] <= {(DWIDTH){1'b0}};
                        mem[14] <= {(DWIDTH){1'b0}};
                        mem[15] <= {(DWIDTH){1'b0}};
                        mem[16] <= {(DWIDTH){1'b0}};
                        mem[17] <= {(DWIDTH){1'b0}};
                        mem[18] <= {(DWIDTH){1'b0}};
                        mem[19] <= {(DWIDTH){1'b0}};
                        mem[20] <= {(DWIDTH){1'b0}};
                        mem[21] <= {(DWIDTH){1'b0}};
 
                        mem[22] <= {(DWIDTH){1'b0}};
                        mem[23] <= {(DWIDTH){1'b0}};
                        mem[24] <= {(DWIDTH){1'b0}};
                        mem[25] <= {(DWIDTH){1'b0}};
                        mem[26] <= {(DWIDTH){1'b0}};
                        mem[27] <= {(DWIDTH){1'b0}};
                        mem[28] <= {(DWIDTH){1'b0}};
                        mem[29] <= {(DWIDTH){1'b0}};
                        mem[30] <= {(DWIDTH){1'b0}};
                        mem[31] <= {(DWIDTH){1'b0}};
                        mem[32] <= {(DWIDTH){1'b0}};
 
 
                        mem[33] <= {(DWIDTH){1'b0}};
                        mem[34] <= {(DWIDTH){1'b0}};
                        mem[35] <= {(DWIDTH){1'b0}};
                        mem[36] <= {(DWIDTH){1'b0}};
                        mem[37] <= {(DWIDTH){1'b0}};
                        mem[38] <= {(DWIDTH){1'b0}};
                        mem[39] <= {(DWIDTH){1'b0}};
                        mem[40] <= {(DWIDTH){1'b0}};
                        mem[41] <= {(DWIDTH){1'b0}};
                        mem[42] <= {(DWIDTH){1'b0}};
                        mem[43] <= {(DWIDTH){1'b0}};
 
                        mem[44] <= {(DWIDTH){1'b0}};
                        mem[45] <= {(DWIDTH){1'b0}};
                        mem[46] <= {(DWIDTH){1'b0}};
                        mem[47] <= {(DWIDTH){1'b0}};
                        mem[48] <= {(DWIDTH){1'b0}};
                        mem[49] <= {(DWIDTH){1'b0}};
                        mem[50] <= {(DWIDTH){1'b0}};
                        mem[51] <= {(DWIDTH){1'b0}};
                        mem[52] <= {(DWIDTH){1'b0}};
                        mem[53] <= {(DWIDTH){1'b0}};
                        mem[54] <= {(DWIDTH){1'b0}};
 
                        mem[55] <= {(DWIDTH){1'b0}};
                        mem[56] <= {(DWIDTH){1'b0}};
                        mem[57] <= {(DWIDTH){1'b0}};
                        mem[58] <= {(DWIDTH){1'b0}};
                        mem[59] <= {(DWIDTH){1'b0}};
                        mem[60] <= {(DWIDTH){1'b0}};
                        mem[61] <= {(DWIDTH){1'b0}};
                        mem[62] <= {(DWIDTH){1'b0}};
                        mem[63] <= {(DWIDTH){1'b0}};
 
                        wr_ptr      <= {(AWIDTH){1'b0}};
                        state_data_write <= 2'd0;
                end
                else
                begin
 
                        state_data_write <= next_state_data_write;
 
                        case(state_data_write)
                        2'd0:
                        begin
                                mem[wr_ptr]<=mem[wr_ptr];
                                wr_ptr <= wr_ptr;
                        end
                        2'd1:
                        begin
                                mem[wr_ptr]<=data_in;
                        end
                        2'd2:
                        begin
                                wr_ptr <= wr_ptr + 6'd1;
                        end
                        default:
                        begin
                                mem[wr_ptr]<=mem[wr_ptr];
                                wr_ptr <= wr_ptr;
                        end
                        endcase
                end
        end
 
//FULL - EMPTY COUNTER
always@(posedge clock or negedge reset)
begin
        if (!reset)
        begin
                counter <= {(AWIDTH){1'b0}};
        end
        else
        begin
 
                if(state_data_write == 2'd2)
                begin
                        if(counter == 6'd63)
                                counter <= counter;
                        else
                                counter <= counter + 6'd1;
                end
                else if(state_data_read == 2'd2)
                begin
                        if(counter == 6'd0)
                                counter <= counter;
                        else
                                counter <= counter - 6'd1;
                end
                else
                begin
                        counter <= counter;
                end
 
        end
end
 
 
always@(*)
begin
 
        f_full  = 1'b0;
        f_empty = 1'b0;
 
        if(counter == 6'd63)
        begin
                f_full  = 1'b1;
        end
 
        if(counter == 6'd0)
        begin
                f_empty = 1'b1;
        end
 
end
 
//Read pointer
always@(posedge clock or negedge reset)
begin
        if (!reset)
        begin
                rd_ptr     <= {(AWIDTH){1'b0}};
                data_out   <= 9'd0;
                write_tx   <= 1'b0;
                state_data_read <= 2'd0;
        end
        else
        begin
                state_data_read <= next_state_data_read;
 
                case(state_data_read)
                2'd0:
                begin
                        if(rd_en)
                        begin
                                write_tx<= 1'b0;
                                rd_ptr     <= rd_ptr + 6'd1;
                        end
                        else
                        begin
                                data_out   <= mem[rd_ptr];
 
                                if(counter > 6'd0)
                                begin
                                        write_tx<= 1'b1;
                                end
                                else
                                        write_tx<= 1'b0;
                        end
                end
                2'd1:
                begin
                        write_tx<= 1'b0;
                        data_out   <= mem[rd_ptr];
                end
                2'd2:
                begin
                        write_tx<= 1'b0;
                        data_out   <= mem[rd_ptr];
                end
                default:
                begin
                        rd_ptr     <= rd_ptr;
                        data_out   <= data_out;
                end
                endcase
        end
end
 
endmodule

Line No.	Rev	Author	Line
1	33	redbear	`//+FHDR------------------------------------------------------------------------`
2			`//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved`
3			`//GLADIC Open Source RTL`
4			`//-----------------------------------------------------------------------------`
5			`//FILE NAME :`
6			`//DEPARTMENT : IC Design / Verification`
7			`//AUTHOR : Felipe Fernandes da Costa`
8			`//AUTHOR’S EMAIL :`
9			`//-----------------------------------------------------------------------------`
10			`//RELEASE HISTORY`
11			`//VERSION DATE AUTHOR DESCRIPTION`
12			`//1.0 YYYY-MM-DD name`
13			`//-----------------------------------------------------------------------------`
14			`//KEYWORDS : General file searching keywords, leave blank if none.`
15			`//-----------------------------------------------------------------------------`
16			`//PURPOSE : ECSS_E_ST_50_12C_31_july_2008`
17			`//-----------------------------------------------------------------------------`
18			`//PARAMETERS`
19			`//PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS`
20			`//e.g.DATA_WIDTH [32,16] : width of the data : 32:`
21			`//-----------------------------------------------------------------------------`
22			`//REUSE ISSUES`
23			`//Reset Strategy :`
24			`//Clock Domains :`
25			`//Critical Timing :`
26			`//Test Features :`
27			`//Asynchronous I/F :`
28			`//Scan Methodology :`
29			`//Instantiations :`
30			`//Synthesizable (y/n) :`
31			`//Other :`
32			`//-FHDR------------------------------------------------------------------------`
33			`module fifo_tx`
34			`#(`
35			`parameter integer DWIDTH = 9,`
36			`parameter integer AWIDTH = 6`
37			`)`
38
39			`(`
40			`input clock, reset, wr_en, rd_en,`
41			`input [DWIDTH-1:0] data_in,`
42			`output reg f_full,write_tx,f_empty,`
43			`output reg [DWIDTH-1:0] data_out,`
44			`output reg [AWIDTH-1:0] counter`
45			`);`
46
47			`reg [DWIDTH-1:0] mem [0:2**AWIDTH-1];`
48
49			`reg [AWIDTH-1:0] wr_ptr;`
50			`reg [AWIDTH-1:0] rd_ptr;`
51
52	37	redbear	`reg [1:0] state_data_write;`
53			`reg [1:0] next_state_data_write;`
54	33	redbear
55	37	redbear	`reg [1:0] state_data_read;`
56			`reg [1:0] next_state_data_read;`
57
58			`/****************************************/`
59
60			`always@(*)`
61			`begin`
62			`next_state_data_write = state_data_write;`
63
64			`case(state_data_write)`
65			`2'd0:`
66			`begin`
67			`if(wr_en && !f_full)`
68			`begin`
69			`next_state_data_write = 2'd1;`
70			`end`
71			`else`
72			`begin`
73			`next_state_data_write = 2'd0;`
74			`end`
75			`end`
76			`2'd1:`
77			`begin`
78			`if(wr_en)`
79			`begin`
80			`next_state_data_write = 2'd1;`
81			`end`
82			`else`
83			`begin`
84			`next_state_data_write = 2'd2;`
85			`end`
86			`end`
87			`2'd2:`
88			`begin`
89			`next_state_data_write = 2'd0;`
90			`end`
91			`default:`
92			`begin`
93			`next_state_data_write = 2'd0;`
94			`end`
95			`endcase`
96			`end`
97
98			`/****************************************/`
99
100			`always@(*)`
101			`begin`
102			`next_state_data_read = state_data_read;`
103
104			`case(state_data_read)`
105			`2'd0:`
106			`begin`
107			`if(rd_en && !f_empty)`
108			`begin`
109			`next_state_data_read = 2'd1;`
110			`end`
111			`else`
112			`begin`
113			`next_state_data_read = 2'd0;`
114			`end`
115			`end`
116			`2'd1:`
117			`begin`
118			`if(rd_en)`
119			`begin`
120			`next_state_data_read = 2'd1;`
121			`end`
122			`else`
123			`begin`
124			`next_state_data_read = 2'd2;`
125			`end`
126			`end`
127			`2'd2:`
128			`begin`
129			`next_state_data_read = 2'd0;`
130			`end`
131			`default:`
132			`begin`
133			`next_state_data_read = 2'd0;`
134			`end`
135			`endcase`
136			`end`
137
138	33	redbear	`//Write pointer`
139			`always@(posedge clock or negedge reset)`
140			`begin`
141			`if (!reset)`
142			`begin`
143	34	redbear	`mem[0] <= {(DWIDTH){1'b0}};`
144			`mem[1] <= {(DWIDTH){1'b0}};`
145			`mem[2] <= {(DWIDTH){1'b0}};`
146			`mem[3] <= {(DWIDTH){1'b0}};`
147			`mem[4] <= {(DWIDTH){1'b0}};`
148			`mem[5] <= {(DWIDTH){1'b0}};`
149			`mem[6] <= {(DWIDTH){1'b0}};`
150			`mem[7] <= {(DWIDTH){1'b0}};`
151			`mem[8] <= {(DWIDTH){1'b0}};`
152			`mem[9] <= {(DWIDTH){1'b0}};`
153			`mem[10] <= {(DWIDTH){1'b0}};`
154
155			`mem[11] <= {(DWIDTH){1'b0}};`
156			`mem[12] <= {(DWIDTH){1'b0}};`
157			`mem[13] <= {(DWIDTH){1'b0}};`
158			`mem[14] <= {(DWIDTH){1'b0}};`
159			`mem[15] <= {(DWIDTH){1'b0}};`
160			`mem[16] <= {(DWIDTH){1'b0}};`
161			`mem[17] <= {(DWIDTH){1'b0}};`
162			`mem[18] <= {(DWIDTH){1'b0}};`
163			`mem[19] <= {(DWIDTH){1'b0}};`
164			`mem[20] <= {(DWIDTH){1'b0}};`
165			`mem[21] <= {(DWIDTH){1'b0}};`
166
167			`mem[22] <= {(DWIDTH){1'b0}};`
168			`mem[23] <= {(DWIDTH){1'b0}};`
169			`mem[24] <= {(DWIDTH){1'b0}};`
170			`mem[25] <= {(DWIDTH){1'b0}};`
171			`mem[26] <= {(DWIDTH){1'b0}};`
172			`mem[27] <= {(DWIDTH){1'b0}};`
173			`mem[28] <= {(DWIDTH){1'b0}};`
174			`mem[29] <= {(DWIDTH){1'b0}};`
175			`mem[30] <= {(DWIDTH){1'b0}};`
176			`mem[31] <= {(DWIDTH){1'b0}};`
177			`mem[32] <= {(DWIDTH){1'b0}};`
178
179
180			`mem[33] <= {(DWIDTH){1'b0}};`
181			`mem[34] <= {(DWIDTH){1'b0}};`
182			`mem[35] <= {(DWIDTH){1'b0}};`
183			`mem[36] <= {(DWIDTH){1'b0}};`
184			`mem[37] <= {(DWIDTH){1'b0}};`
185			`mem[38] <= {(DWIDTH){1'b0}};`
186			`mem[39] <= {(DWIDTH){1'b0}};`
187			`mem[40] <= {(DWIDTH){1'b0}};`
188			`mem[41] <= {(DWIDTH){1'b0}};`
189			`mem[42] <= {(DWIDTH){1'b0}};`
190			`mem[43] <= {(DWIDTH){1'b0}};`
191
192			`mem[44] <= {(DWIDTH){1'b0}};`
193			`mem[45] <= {(DWIDTH){1'b0}};`
194			`mem[46] <= {(DWIDTH){1'b0}};`
195			`mem[47] <= {(DWIDTH){1'b0}};`
196			`mem[48] <= {(DWIDTH){1'b0}};`
197			`mem[49] <= {(DWIDTH){1'b0}};`
198			`mem[50] <= {(DWIDTH){1'b0}};`
199			`mem[51] <= {(DWIDTH){1'b0}};`
200			`mem[52] <= {(DWIDTH){1'b0}};`
201			`mem[53] <= {(DWIDTH){1'b0}};`
202			`mem[54] <= {(DWIDTH){1'b0}};`
203
204			`mem[55] <= {(DWIDTH){1'b0}};`
205			`mem[56] <= {(DWIDTH){1'b0}};`
206			`mem[57] <= {(DWIDTH){1'b0}};`
207			`mem[58] <= {(DWIDTH){1'b0}};`
208			`mem[59] <= {(DWIDTH){1'b0}};`
209			`mem[60] <= {(DWIDTH){1'b0}};`
210			`mem[61] <= {(DWIDTH){1'b0}};`
211			`mem[62] <= {(DWIDTH){1'b0}};`
212			`mem[63] <= {(DWIDTH){1'b0}};`
213
214			`wr_ptr <= {(AWIDTH){1'b0}};`
215	37	redbear	`state_data_write <= 2'd0;`
216	33	redbear	`end`
217	34	redbear	`else`
218	33	redbear	`begin`
219
220	37	redbear	`state_data_write <= next_state_data_write;`
221	33	redbear
222	37	redbear	`case(state_data_write)`
223			`2'd0:`
224	33	redbear	`begin`
225	39	redbear	`mem[wr_ptr]<=mem[wr_ptr];`
226			`wr_ptr <= wr_ptr;`
227	33	redbear	`end`
228	37	redbear	`2'd1:`
229	34	redbear	`begin`
230	39	redbear	`mem[wr_ptr]<=data_in;`
231	34	redbear	`end`
232	37	redbear	`2'd2:`
233	33	redbear	`begin`
234	37	redbear	`wr_ptr <= wr_ptr + 6'd1;`
235	33	redbear	`end`
236	37	redbear	`default:`
237	34	redbear	`begin`
238	37	redbear	`mem[wr_ptr]<=mem[wr_ptr];`
239			`wr_ptr <= wr_ptr;`
240	34	redbear	`end`
241	37	redbear	`endcase`
242			`end`
243			`end`
244	33	redbear
245	37	redbear	`//FULL - EMPTY COUNTER`
246			`always@(posedge clock or negedge reset)`
247			`begin`
248			`if (!reset)`
249			`begin`
250			`counter <= {(AWIDTH){1'b0}};`
251			`end`
252			`else`
253			`begin`
254
255	39	redbear	`if(state_data_write == 2'd2)`
256	37	redbear	`begin`
257	33	redbear	`if(counter == 6'd63)`
258	37	redbear	`counter <= counter;`
259	33	redbear	`else`
260	37	redbear	`counter <= counter + 6'd1;`
261			`end`
262			`else if(state_data_read == 2'd2)`
263			`begin`
264	33	redbear	`if(counter == 6'd0)`
265	37	redbear	`counter <= counter;`
266	33	redbear	`else`
267	37	redbear	`counter <= counter - 6'd1;`
268			`end`
269			`else`
270			`begin`
271			`counter <= counter;`
272			`end`
273	33	redbear
274	39	redbear	`end`
275			`end`
276	33	redbear
277	39	redbear
278			`always@(*)`
279			`begin`
280
281			`f_full = 1'b0;`
282			`f_empty = 1'b0;`
283
284			`if(counter == 6'd63)`
285			`begin`
286			`f_full = 1'b1;`
287	37	redbear	`end`
288	39	redbear
289			`if(counter == 6'd0)`
290			`begin`
291			`f_empty = 1'b1;`
292			`end`
293
294	37	redbear	`end`
295	33	redbear
296	37	redbear	`//Read pointer`
297			`always@(posedge clock or negedge reset)`
298			`begin`
299			`if (!reset)`
300			`begin`
301			`rd_ptr <= {(AWIDTH){1'b0}};`
302			`data_out <= 9'd0;`
303			`write_tx <= 1'b0;`
304			`state_data_read <= 2'd0;`
305			`end`
306			`else`
307			`begin`
308			`state_data_read <= next_state_data_read;`
309	33	redbear
310	37	redbear	`case(state_data_read)`
311			`2'd0:`
312			`begin`
313	34	redbear	`if(rd_en)`
314	33	redbear	`begin`
315			`write_tx<= 1'b0;`
316	39	redbear	`rd_ptr <= rd_ptr + 6'd1;`
317	33	redbear	`end`
318	37	redbear	`else`
319	33	redbear	`begin`
320	37	redbear	`data_out <= mem[rd_ptr];`
321	39	redbear
322	37	redbear	`if(counter > 6'd0)`
323			`begin`
324			`write_tx<= 1'b1;`
325			`end`
326			`else`
327			`write_tx<= 1'b0;`
328	33	redbear	`end`
329			`end`
330	37	redbear	`2'd1:`
331			`begin`
332			`write_tx<= 1'b0;`
333			`data_out <= mem[rd_ptr];`
334			`end`
335			`2'd2:`
336			`begin`
337			`write_tx<= 1'b0;`
338	39	redbear	`data_out <= mem[rd_ptr];`
339	37	redbear	`end`
340			`default:`
341			`begin`
342			`rd_ptr <= rd_ptr;`
343			`data_out <= data_out;`
344			`end`
345			`endcase`
346	33	redbear	`end`
347	37	redbear	`end`
348	33	redbear
349			`endmodule`

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