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//+FHDR------------------------------------------------------------------------
//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
//GLADIC Open Source RTL
//-----------------------------------------------------------------------------
//FILE NAME      :
//DEPARTMENT     : IC Design / Verification
//AUTHOR         : Felipe Fernandes da Costa
//AUTHOR’S EMAIL :
//-----------------------------------------------------------------------------
//RELEASE HISTORY
//VERSION DATE AUTHOR DESCRIPTION
//1.0 YYYY-MM-DD name
//-----------------------------------------------------------------------------
//KEYWORDS : General file searching keywords, leave blank if none.
//-----------------------------------------------------------------------------
//PURPOSE  : ECSS_E_ST_50_12C_31_july_2008
//-----------------------------------------------------------------------------
//PARAMETERS
//PARAM NAME            RANGE   : DESCRIPTION : DEFAULT : UNITS
//e.g.DATA_WIDTH        [32,16] : width of the data : 32:
//-----------------------------------------------------------------------------
//REUSE ISSUES
//Reset Strategy        :
//Clock Domains         :
//Critical Timing       :
//Test Features         :
//Asynchronous I/F      :
//Scan Methodology      :
//Instantiations        :
//Synthesizable (y/n)   :
//Other                 :
//-FHDR------------------------------------------------------------------------
 
`timescale 1ns/1ns
 
module FSM_SPW (
                input  pclk,
                input  resetn,
 
                //fsm status control
                input  auto_start,
                input  link_start,
                input  link_disable,
 
                //rx status input control
                input  rx_error,
                input  rx_credit_error,
                input  rx_got_bit,
                input  rx_got_null,
                input  rx_got_nchar,
                input  rx_got_time_code,
                input  rx_got_fct,
                output reg rx_resetn,
 
                //tx status control
                output reg enable_tx,
                output reg send_null_tx,
                output reg send_fct_tx,
 
                output [5:0] fsm_state
 
              );
 
localparam [5:0]  error_reset   = 6'b00_0000,
                  error_wait    = 6'b00_0001,
                  ready         = 6'b00_0010,
                  started       = 6'b00_0100,
                  connecting    = 6'b00_1000,
                  run           = 6'b01_0000;
 
        reg [5:0] state_fsm;
        reg [5:0] next_state_fsm;
 
        reg [11:0] after128us;
        reg [11:0] after64us;
        reg [11:0] after850ns;
 
        reg got_bit_internal;
 
//
assign fsm_state    = state_fsm;
 
always@(*)
begin
 
        next_state_fsm = state_fsm;
 
        case(state_fsm)
        error_reset:
        begin
 
                if(after64us == 12'd639)
                begin
                        next_state_fsm = error_wait;
                end
                else
                begin
                        next_state_fsm = error_reset;
                end
 
        end
        error_wait:
        begin
 
                if(after128us == 12'd1279)
                begin
                        next_state_fsm = ready;
                end
                else if(rx_error | rx_got_fct | rx_got_nchar | rx_got_time_code)
                begin
                        next_state_fsm = error_reset;
                end
 
        end
        ready:
        begin
 
                if(rx_error | rx_got_fct | rx_got_nchar | rx_got_time_code)
                begin
                        next_state_fsm = error_reset;
                end
                else if(((!link_disable) & (link_start |(auto_start & rx_got_null)))==1'b1)
                begin
                        next_state_fsm = started;
                end
 
        end
        started:
        begin
 
                if(rx_error | rx_got_fct | rx_got_nchar | rx_got_time_code | after128us == 12'd1279)
                begin
                        next_state_fsm = error_reset;
                end
                else if((rx_got_null & rx_got_bit)== 1'b1)
                begin
                        next_state_fsm = connecting;
                end
 
        end
        connecting:
        begin
 
                if(rx_error | rx_got_nchar | rx_got_time_code | after128us == 12'd1279)
                begin
                        next_state_fsm = error_reset;
                end
                else if(rx_got_fct)
                begin
                        next_state_fsm = run;
                end
 
        end
        run:
        begin
 
                if(rx_error | rx_credit_error | link_disable  | after850ns == 12'd85)
                begin
                        next_state_fsm = error_reset;
                end
                else
                begin
                        next_state_fsm = run;
                end
 
        end
        endcase
end
 
always@(posedge pclk or negedge resetn)
begin
        if(!resetn)
        begin
                state_fsm <= error_reset;
 
                rx_resetn <= 1'b0;
 
                enable_tx<= 1'b0;
                send_null_tx<= 1'b0;
                send_fct_tx<= 1'b0;
        end
        else
        begin
 
                state_fsm <= next_state_fsm;
 
                case(state_fsm)
                error_reset:
                begin
                        enable_tx<= 1'b0;
                        send_null_tx<= 1'b0;
                        send_fct_tx<= 1'b0;
 
                        if(after64us == 12'd639)
                                rx_resetn <= 1'b1;
                        else
                                rx_resetn <= 1'b0;
                end
                error_wait:
                begin
                        rx_resetn <= 1'b1;
                        enable_tx<= 1'b0;
                        send_null_tx<= 1'b0;
                        send_fct_tx<= 1'b0;
                end
                ready:
                begin
                        rx_resetn <= 1'b1;
                        enable_tx<= 1'b1;
                        send_null_tx<= 1'b0;
                        send_fct_tx<= 1'b0;
                end
                started:
                begin
                        rx_resetn <= 1'b1;
                        enable_tx<= 1'b1;
                        send_null_tx<= 1'b1;
                        send_fct_tx<= 1'b0;
                end
                connecting:
                begin
                        rx_resetn <= 1'b1;
                        enable_tx<= 1'b1;
                        send_null_tx<= 1'b1;
                        send_fct_tx<= 1'b1;
                end
                run:
                begin
                        rx_resetn <= 1'b1;
                        enable_tx<= 1'b1;
                        send_null_tx<= 1'b1;
                        send_fct_tx<= 1'b1;
                end
                endcase
 
        end
end
 
always@(posedge pclk)
begin
 
        if(!resetn || state_fsm == error_reset)
        begin
                after128us <= 12'd0;
        end
        else
        begin
 
                if(next_state_fsm == connecting && state_fsm == started)
                begin
                        after128us <= 12'd0;
                end
                else if(state_fsm == error_wait || state_fsm == started || state_fsm == connecting)
                begin
                        if(after128us < 12'd1279)
                                after128us <= after128us + 12'd1;
                        else
                                after128us <= 12'd0;
                end
                else
                begin
                                after128us <= 12'd0;
                end
        end
 
end
 
always@(posedge pclk)
begin
 
        if(!resetn)
        begin
                after64us <= 12'd0;
        end
        else
        begin
                if(state_fsm == error_reset && (auto_start | link_start))
                begin
                        if(after64us < 12'd639)
                                after64us <= after64us + 12'd1;
                        else
                                after64us <= 12'd0;
                end
                else
                begin
                        after64us <= 12'd0;
                end
        end
 
end
 
always@(posedge pclk)
begin
        if(!resetn)
        begin
                got_bit_internal <= 1'b0;
        end
        else
        begin
                if(rx_got_bit)
                        got_bit_internal <= 1'b1;
                else
                        got_bit_internal <= 1'b0;
        end
end
 
always@(posedge pclk)
begin
 
        if(!resetn | got_bit_internal)
        begin
                after850ns <= 12'd0;
        end
        else
        begin
                if(state_fsm != run)
                begin
                        after850ns <= 12'd0;
                end
                else
                begin
                        if(after850ns < 12'd85 && state_fsm == run)
                                after850ns <= after850ns + 12'd1;
                        else
                                after850ns <= after850ns;
 
                end
        end
 
end
 
endmodule

Line No.	Rev	Author	Line
1	5	redbear	`//+FHDR------------------------------------------------------------------------`
2			`//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved`
3			`//GLADIC Open Source RTL`
4			`//-----------------------------------------------------------------------------`
5			`//FILE NAME :`
6			`//DEPARTMENT : IC Design / Verification`
7			`//AUTHOR : Felipe Fernandes da Costa`
8			`//AUTHOR’S EMAIL :`
9			`//-----------------------------------------------------------------------------`
10			`//RELEASE HISTORY`
11			`//VERSION DATE AUTHOR DESCRIPTION`
12			`//1.0 YYYY-MM-DD name`
13			`//-----------------------------------------------------------------------------`
14			`//KEYWORDS : General file searching keywords, leave blank if none.`
15			`//-----------------------------------------------------------------------------`
16			`//PURPOSE : ECSS_E_ST_50_12C_31_july_2008`
17			`//-----------------------------------------------------------------------------`
18			`//PARAMETERS`
19			`//PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS`
20			`//e.g.DATA_WIDTH [32,16] : width of the data : 32:`
21			`//-----------------------------------------------------------------------------`
22			`//REUSE ISSUES`
23			`//Reset Strategy :`
24			`//Clock Domains :`
25			`//Critical Timing :`
26			`//Test Features :`
27			`//Asynchronous I/F :`
28			`//Scan Methodology :`
29			`//Instantiations :`
30			`//Synthesizable (y/n) :`
31			`//Other :`
32			`//-FHDR------------------------------------------------------------------------`
33
34			`timescale 1ns/1ns
35
36			`module FSM_SPW (`
37			`input pclk,`
38			`input resetn,`
39
40			`//fsm status control`
41			`input auto_start,`
42			`input link_start,`
43			`input link_disable,`
44
45			`//rx status input control`
46			`input rx_error,`
47			`input rx_credit_error,`
48			`input rx_got_bit,`
49			`input rx_got_null,`
50			`input rx_got_nchar,`
51			`input rx_got_time_code,`
52			`input rx_got_fct,`
53	33	redbear	`output reg rx_resetn,`
54	5	redbear
55			`//tx status control`
56	33	redbear	`output reg enable_tx,`
57			`output reg send_null_tx,`
58			`output reg send_fct_tx,`
59	5	redbear
60			`output [5:0] fsm_state`
61
62			`);`
63
64			`localparam [5:0] error_reset = 6'b00_0000,`
65			`error_wait = 6'b00_0001,`
66			`ready = 6'b00_0010,`
67			`started = 6'b00_0100,`
68			`connecting = 6'b00_1000,`
69			`run = 6'b01_0000;`
70
71			`reg [5:0] state_fsm;`
72			`reg [5:0] next_state_fsm;`
73
74			`reg [11:0] after128us;`
75			`reg [11:0] after64us;`
76			`reg [11:0] after850ns;`
77
78	33	redbear	`reg got_bit_internal;`
79	5	redbear
80			`//`
81			`assign fsm_state = state_fsm;`
82
83			`always@(*)`
84			`begin`
85
86			`next_state_fsm = state_fsm;`
87
88			`case(state_fsm)`
89			`error_reset:`
90			`begin`
91
92			`if(after64us == 12'd639)`
93			`begin`
94			`next_state_fsm = error_wait;`
95			`end`
96			`else`
97			`begin`
98			`next_state_fsm = error_reset;`
99			`end`
100
101			`end`
102			`error_wait:`
103			`begin`
104
105			`if(after128us == 12'd1279)`
106			`begin`
107			`next_state_fsm = ready;`
108			`end`
109			`else if(rx_error \| rx_got_fct \| rx_got_nchar \| rx_got_time_code)`
110			`begin`
111			`next_state_fsm = error_reset;`
112			`end`
113
114			`end`
115			`ready:`
116			`begin`
117
118			`if(rx_error \| rx_got_fct \| rx_got_nchar \| rx_got_time_code)`
119			`begin`
120			`next_state_fsm = error_reset;`
121			`end`
122	33	redbear	`else if(((!link_disable) & (link_start \|(auto_start & rx_got_null)))==1'b1)`
123	5	redbear	`begin`
124			`next_state_fsm = started;`
125			`end`
126
127			`end`
128			`started:`
129			`begin`
130
131	25	redbear	`if(rx_error \| rx_got_fct \| rx_got_nchar \| rx_got_time_code \| after128us == 12'd1279)`
132	5	redbear	`begin`
133			`next_state_fsm = error_reset;`
134			`end`
135	33	redbear	`else if((rx_got_null & rx_got_bit)== 1'b1)`
136	5	redbear	`begin`
137			`next_state_fsm = connecting;`
138			`end`
139
140			`end`
141			`connecting:`
142			`begin`
143
144	25	redbear	`if(rx_error \| rx_got_nchar \| rx_got_time_code \| after128us == 12'd1279)`
145	5	redbear	`begin`
146			`next_state_fsm = error_reset;`
147			`end`
148			`else if(rx_got_fct)`
149			`begin`
150			`next_state_fsm = run;`
151			`end`
152
153			`end`
154			`run:`
155			`begin`
156
157			`if(rx_error \| rx_credit_error \| link_disable \| after850ns == 12'd85)`
158			`begin`
159			`next_state_fsm = error_reset;`
160			`end`
161			`else`
162			`begin`
163			`next_state_fsm = run;`
164			`end`
165
166			`end`
167			`endcase`
168			`end`
169
170	33	redbear	`always@(posedge pclk or negedge resetn)`
171	5	redbear	`begin`
172			`if(!resetn)`
173			`begin`
174			`state_fsm <= error_reset;`
175	33	redbear
176			`rx_resetn <= 1'b0;`
177
178			`enable_tx<= 1'b0;`
179			`send_null_tx<= 1'b0;`
180			`send_fct_tx<= 1'b0;`
181	5	redbear	`end`
182			`else`
183			`begin`
184
185			`state_fsm <= next_state_fsm;`
186
187			`case(state_fsm)`
188			`error_reset:`
189			`begin`
190	33	redbear	`enable_tx<= 1'b0;`
191			`send_null_tx<= 1'b0;`
192			`send_fct_tx<= 1'b0;`
193
194			`if(after64us == 12'd639)`
195			`rx_resetn <= 1'b1;`
196			`else`
197			`rx_resetn <= 1'b0;`
198	5	redbear	`end`
199			`error_wait:`
200			`begin`
201	33	redbear	`rx_resetn <= 1'b1;`
202			`enable_tx<= 1'b0;`
203			`send_null_tx<= 1'b0;`
204			`send_fct_tx<= 1'b0;`
205	5	redbear	`end`
206			`ready:`
207			`begin`
208	33	redbear	`rx_resetn <= 1'b1;`
209			`enable_tx<= 1'b1;`
210			`send_null_tx<= 1'b0;`
211			`send_fct_tx<= 1'b0;`
212	5	redbear	`end`
213			`started:`
214			`begin`
215	33	redbear	`rx_resetn <= 1'b1;`
216			`enable_tx<= 1'b1;`
217			`send_null_tx<= 1'b1;`
218			`send_fct_tx<= 1'b0;`
219	5	redbear	`end`
220			`connecting:`
221			`begin`
222	33	redbear	`rx_resetn <= 1'b1;`
223			`enable_tx<= 1'b1;`
224			`send_null_tx<= 1'b1;`
225			`send_fct_tx<= 1'b1;`
226	5	redbear	`end`
227			`run:`
228			`begin`
229	33	redbear	`rx_resetn <= 1'b1;`
230			`enable_tx<= 1'b1;`
231			`send_null_tx<= 1'b1;`
232			`send_fct_tx<= 1'b1;`
233	5	redbear	`end`
234			`endcase`
235	25	redbear
236	5	redbear	`end`
237			`end`
238
239			`always@(posedge pclk)`
240			`begin`
241
242	33	redbear	`if(!resetn \|\| state_fsm == error_reset)`
243	5	redbear	`begin`
244			`after128us <= 12'd0;`
245			`end`
246			`else`
247			`begin`
248	25	redbear
249			`if(next_state_fsm == connecting && state_fsm == started)`
250	5	redbear	`begin`
251	25	redbear	`after128us <= 12'd0;`
252			`end`
253			`else if(state_fsm == error_wait \|\| state_fsm == started \|\| state_fsm == connecting)`
254			`begin`
255	5	redbear	`if(after128us < 12'd1279)`
256			`after128us <= after128us + 12'd1;`
257			`else`
258			`after128us <= 12'd0;`
259			`end`
260			`else`
261			`begin`
262			`after128us <= 12'd0;`
263			`end`
264			`end`
265
266			`end`
267
268			`always@(posedge pclk)`
269			`begin`
270
271			`if(!resetn)`
272			`begin`
273			`after64us <= 12'd0;`
274			`end`
275			`else`
276			`begin`
277			`if(state_fsm == error_reset && (auto_start \| link_start))`
278			`begin`
279			`if(after64us < 12'd639)`
280			`after64us <= after64us + 12'd1;`
281			`else`
282			`after64us <= 12'd0;`
283			`end`
284			`else`
285			`begin`
286			`after64us <= 12'd0;`
287			`end`
288			`end`
289
290			`end`
291
292			`always@(posedge pclk)`
293			`begin`
294	18	redbear	`if(!resetn)`
295	5	redbear	`begin`
296	33	redbear	`got_bit_internal <= 1'b0;`
297			`end`
298			`else`
299			`begin`
300			`if(rx_got_bit)`
301			`got_bit_internal <= 1'b1;`
302			`else`
303			`got_bit_internal <= 1'b0;`
304			`end`
305			`end`
306
307			`always@(posedge pclk)`
308			`begin`
309
310			`if(!resetn \| got_bit_internal)`
311			`begin`
312	5	redbear	`after850ns <= 12'd0;`
313			`end`
314			`else`
315			`begin`
316	25	redbear	`if(state_fsm != run)`
317	18	redbear	`begin`
318			`after850ns <= 12'd0;`
319			`end`
320	5	redbear	`else`
321	18	redbear	`begin`
322	33	redbear	`if(after850ns < 12'd85 && state_fsm == run)`
323			`after850ns <= after850ns + 12'd1;`
324			`else`
325	37	redbear	`after850ns <= after850ns;`
326	33	redbear
327	18	redbear	`end`
328	5	redbear	`end`
329
330			`end`
331
332			`endmodule`

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[/] [spacewiresystemc/] [trunk/] [rtl/] [RTL_VB/] [fsm_spw.v] - Blame information for rev 37