OpenCores
URL https://opencores.org/ocsvn/spicxif/spicxif/trunk

Subversion Repositories spicxif

[/] [spicxif/] [trunk/] [Sim/] [tb_SPIxIF.v] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 MichaelA
///////////////////////////////////////////////////////////////////////////////
2
//
3
//  Copyright 2008-2013 by Michael A. Morris, dba M. A. Morris & Associates
4
//
5
//  All rights reserved. The source code contained herein is publicly released
6
//  under the terms and conditions of the GNU Lesser Public License. No part of
7
//  this source code may be reproduced or transmitted in any form or by any
8
//  means, electronic or mechanical, including photocopying, recording, or any
9
//  information storage and retrieval system in violation of the license under
10
//  which the source code is released.
11
//
12
//  The source code contained herein is free; it may be redistributed and/or 
13
//  modified in accordance with the terms of the GNU Lesser General Public
14
//  License as published by the Free Software Foundation; either version 2.1 of
15
//  the GNU Lesser General Public License, or any later version.
16
//
17
//  The source code contained herein is freely released WITHOUT ANY WARRANTY;
18
//  without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
19
//  PARTICULAR PURPOSE. (Refer to the GNU Lesser General Public License for
20
//  more details.)
21
//
22
//  A copy of the GNU Lesser General Public License should have been received
23
//  along with the source code contained herein; if not, a copy can be obtained
24
//  by writing to:
25
//
26
//  Free Software Foundation, Inc.
27
//  51 Franklin Street, Fifth Floor
28
//  Boston, MA  02110-1301 USA
29
//
30
//  Further, no use of this source code is permitted in any form or means
31
//  without inclusion of this banner prominently in any derived works. 
32
//
33
//  Michael A. Morris
34
//  Huntsville, AL
35
//
36
///////////////////////////////////////////////////////////////////////////////`timescale 1ns / 1ps
37
 
38
`timescale 1ns / 1ps
39
 
40
///////////////////////////////////////////////////////////////////////////////
41
// Company:         M. A. Morris & Associates
42
// Engineer:        Michael A. Morris
43
//
44
// Create Date:     07:30:59 03/18/2008
45
// Design Name:     SPIxIF.v
46
// Module Name:     tb_SPIx.v
47
// Project Name:    4020 HAWK ZAOM Upgrade, 0420-HAWKIF
48
// Target Device:   XC2S150-5PQ208I
49
// Tool versions:   ISE 8.2i
50
//  
51
// Description: Testbench for the modified SPIxIF.v module. 
52
//
53
//
54
// Verilog Test Fixture created by ISE for module: SPIxIF.v
55
//
56
// Dependencies:    None
57
// 
58
// Revision:
59
//
60
//  0.01    08C18   MAM     File Created
61
//
62
//  1.00    12I09   MAM     Modified to support updated SPIxIF.v module
63
//
64
// Additional Comments:
65
// 
66
///////////////////////////////////////////////////////////////////////////////
67
 
68
module tb_SPIxIF;
69
 
70
// Inputs
71
reg     Rst;
72
reg     Clk;
73
 
74
reg     LSB;
75
reg     [1:0] Mode;
76
reg     [2:0] Rate;
77
 
78
reg     DAV;
79
wire    FRE;
80
reg     [8:0] TD;
81
 
82
wire    FWE;
83
wire    [7:0] RD;
84
 
85
wire    SSEL;
86
wire    SCK;
87
wire    MOSI;
88
//wire    MISO;
89
 
90
integer i      = 0;
91
integer SS_Len = 0;
92
 
93
        // Instantiate the Unit Under Test (UUT)
94
 
95
SPIxIF  uut (
96
            .Rst(Rst),
97
            .Clk(Clk),
98
 
99
            .LSB(LSB),
100
            .Mode(Mode),
101
            .Rate(Rate),
102
 
103
            .DAV(DAV),
104
            .FRE(FRE),
105
            .TD(TD),
106
 
107
            .FWE(FWE),
108
            .RD(RD),
109
 
110
            .SS(SS),
111
            .SCK(SCK),
112
            .MOSI(MOSI),
113
            .MISO(MOSI)
114
        );
115
 
116
initial begin
117
    // Initialize Inputs
118
    Rst  = 1;
119
    Clk  = 0;
120
 
121
    LSB  = 0;
122
    Mode = 0;
123
    Rate = 0;
124
 
125
    DAV  = 0;
126
    TD   = 0;
127
 
128
    // Wait 100 ns for global reset to finish
129
 
130
    #101 Rst = 0;
131
 
132
    // Add stimulus here
133
 
134
    $display("Testing: MSB first, all four SPI modes, fastest SPI SCK rate\n");
135
 
136
    Mode = 0; Rate = 0; LSB = 0;
137
 
138
    $display("\tTest - Mode 0\n");
139
    #1;
140
    if(SCK != 0) begin
141
        $display("\t\tError: SCK did not idle low in Mode 0\n");
142
        $stop;
143
    end else begin
144
        $display("\t\tPass: SCK idled low in Mode 0\n");
145
    end
146
    @(posedge Clk) #1;
147
    DAV = 1; TD = 9'h1AB;
148
    @(posedge FRE) DAV = 0;
149
    #1;
150
    if(SCK != 0) begin
151
        $display("\t\tError: SCK did not start low in Mode 0\n");
152
        $stop;
153
    end else begin
154
        $display("\t\tPass: SCK started low in Mode 0\n");
155
    end
156
    @(negedge FWE) Mode = 1;
157
    #1;
158
    if(SCK != 0) begin
159
        $display("\t\tError: SCK did not idle low in Mode 0\n");
160
        $stop;
161
    end else begin
162
        $display("\t\tPass: SCK idled low in Mode 0\n");
163
    end
164
    if(RD != TD[7:0]) begin
165
        $display("\t\tError: RD not equal to TD\n");
166
        $stop;
167
    end else begin
168
        $display("\t\tPass: RD equal to TD\n");
169
    end
170
    if(SS_Len != 16) begin
171
        $display("\t\tError: SS Length != 16; SCK rate incorrect\n");
172
        $stop;
173
    end else begin
174
        $display("\t\tPass: SS Length == 16; SCK rate correct\n");
175
    end
176
 
177
    @(posedge Clk) #1;
178
    @(posedge Clk) #1;
179
    @(posedge Clk) #1;
180
    @(posedge Clk) #1;
181
 
182
    $display("\tTest - Mode 1\n");
183
    #1;
184
    if(SCK != 1) begin
185
        $display("\t\tError: SCK did not idle high in Mode 1\n");
186
        $stop;
187
    end else begin
188
        $display("\t\tPass: SCK idled high in Mode 1\n");
189
    end
190
    @(posedge Clk) #1;
191
    DAV = 1; TD = 9'h15A;
192
    @(posedge FRE) DAV = 0;
193
    #1;
194
    if(SCK != 1) begin
195
        $display("\t\tError: SCK did not start high in Mode 1\n");
196
        $stop;
197
    end else begin
198
        $display("\t\tPass: SCK started high in Mode 1\n");
199
    end
200
    @(negedge FWE) Mode = 2;
201
    if(SCK != 1) begin
202
        $display("\t\tError: SCK did not idle high in Mode 1\n");
203
        $stop;
204
    end else begin
205
        $display("\t\tPass: SCK idled high in Mode 1\n");
206
    end
207
    if(RD != TD[7:0]) begin
208
        $display("\t\tError: RD not equal to TD\n");
209
        $stop;
210
    end else begin
211
        $display("\t\tPass: RD equal to TD\n");
212
    end
213
    if(SS_Len != 16) begin
214
        $display("\t\tError: SS Length != 16; SCK rate incorrect\n");
215
        $stop;
216
    end else begin
217
        $display("\t\tPass: SS Length == 16; SCK rate correct\n");
218
    end
219
 
220
    @(posedge Clk) #1;
221
    @(posedge Clk) #1;
222
    @(posedge Clk) #1;
223
    @(posedge Clk) #1;
224
 
225
    $display("\tTest - Mode 2\n");
226
    #1;
227
    if(SCK != 0) begin
228
        $display("\t\tError: SCK did not idle low in Mode 2\n");
229
        $stop;
230
    end else begin
231
        $display("\t\tPass: SCK idled low in Mode 2\n");
232
    end
233
    @(posedge Clk) #1;
234
    DAV = 1; TD = 9'h1A5;
235
    @(posedge FRE) DAV = 0;
236
    #1;
237
    if(SCK != 1) begin
238
        $display("\t\tError: SCK did not start high in Mode 2\n");
239
        $stop;
240
    end else begin
241
        $display("\t\tPass: SCK started high in Mode 2\n");
242
    end
243
    @(negedge FWE) Mode = 3;
244
    if(SCK != 0) begin
245
        $display("\t\tError: SCK did not idle low in Mode 2\n");
246
        $stop;
247
    end else begin
248
        $display("\t\tPass: SCK idled low in Mode 2\n");
249
    end
250
    if(RD != TD[7:0]) begin
251
        $display("\t\tError: RD not equal to TD\n");
252
        $stop;
253
    end else begin
254
        $display("\t\tPass: RD equal to TD\n");
255
    end
256
    if(SS_Len != 16) begin
257
        $display("\t\tError: SS Length != 16; SCK rate incorrect\n");
258
        $stop;
259
    end else begin
260
        $display("\t\tPass: SS Length == 16; SCK rate correct\n");
261
    end
262
 
263
    @(posedge Clk) #1;
264
    @(posedge Clk) #1;
265
    @(posedge Clk) #1;
266
    @(posedge Clk) #1;
267
 
268
    $display("\tTest - Mode 3\n");
269
    #1;
270
    if(SCK != 1) begin
271
        $display("\t\tError: SCK did not idle high in Mode 3\n");
272
        $stop;
273
    end else begin
274
        $display("\t\tPass: SCK idled high in Mode 3\n");
275
    end
276
    @(posedge Clk) #1;
277
    DAV = 1; TD = 9'h169;
278
    @(posedge FRE) DAV = 0;
279
    #1;
280
    if(SCK != 0) begin
281
        $display("\t\tError: SCK did not start low in Mode 3\n");
282
        $stop;
283
    end else begin
284
        $display("\t\tPass: SCK started low in Mode 3\n");
285
    end
286
    @(negedge FWE) Mode = 0;
287
    if(SCK != 1) begin
288
        $display("\t\tError: SCK did not idle high in Mode 3\n");
289
        $stop;
290
    end else begin
291
        $display("\t\tPass: SCK idled high in Mode 3\n");
292
    end
293
    if(RD != TD[7:0]) begin
294
        $display("\t\tError: RD not equal to TD\n");
295
        $stop;
296
    end else begin
297
        $display("\t\tPass: RD equal to TD\n");
298
    end
299
    if(SS_Len != 16) begin
300
        $display("\t\tError: SS Length != 16; SCK rate incorrect\n");
301
        $stop;
302
    end else begin
303
        $display("\t\tPass: SS Length == 16; SCK rate correct\n");
304
    end
305
 
306
    $display("Testing multi-cycle transfer\n");
307
    @(posedge Clk) #1;
308
    DAV = 1;
309
    TD = 9'h002;
310
    @(negedge FRE);
311
    TD = 9'h000;
312
    @(negedge FRE);
313
    TD = 9'h0AA;
314
    @(negedge FRE);
315
    TD = 9'h055;
316
    @(negedge FRE);
317
    TD = 9'h000;
318
    DAV = 0;
319
    @(negedge SS) #1;
320
    if(SS_Len != 64) begin
321
        $display("\tError: SS Length != 64; Incorrect number of transfers\n");
322
        $stop;
323
    end else begin
324
        $display("\tPass: SS Length == 64; Correct number of transfers\n");
325
    end
326
 
327
    $display("Testing multi-cycle transfer with (Rate == 1)\n");
328
    Rate = 1;
329
    @(posedge Clk) #1;
330
    @(posedge Clk) #1;
331
    @(posedge Clk) #1;
332
    @(posedge Clk) #1;
333
 
334
    DAV = 1;
335
    TD = 9'h002;
336
    @(negedge FRE);
337
    TD = 9'h000;
338
    @(negedge FRE);
339
    TD = 9'h0AA;
340
    @(negedge FRE);
341
    TD = 9'h055;
342
    @(negedge FRE);
343
    TD = 9'h000;
344
    DAV = 0;
345
    @(negedge SS) #1;
346
    if(SS_Len != 128) begin
347
        $display("\tError: SS Length != 128; SS_Len = %d\n", SS_Len);
348
        $stop;
349
    end else begin
350
        $display("\tPass: SS Length == %d\n", SS_Len);
351
    end
352
 
353
    $display("Testing multi-cycle transfer with (Rate == 2)\n");
354
    Rate = 2;
355
    @(posedge Clk) #1;
356
    @(posedge Clk) #1;
357
    @(posedge Clk) #1;
358
    @(posedge Clk) #1;
359
 
360
    DAV = 1;
361
    TD = 9'h002;
362
    @(negedge FRE);
363
    TD = 9'h000;
364
    @(negedge FRE);
365
    TD = 9'h0AA;
366
    @(negedge FRE);
367
    TD = 9'h055;
368
    @(negedge FRE);
369
    TD = 9'h000;
370
    DAV = 0;
371
    @(negedge SS) #1;
372
    if(SS_Len != 256) begin
373
        $display("\tError: SS Length != 256; SS_Len = %d\n", SS_Len);
374
        $stop;
375
    end else begin
376
        $display("\tPass: SS Length == %d\n", SS_Len);
377
    end
378
 
379
    $display("Testing multi-cycle transfer with (Rate == 3)\n");
380
    Rate = 3;
381
    @(posedge Clk) #1;
382
    @(posedge Clk) #1;
383
    @(posedge Clk) #1;
384
    @(posedge Clk) #1;
385
 
386
    DAV = 1;
387
    TD = 9'h002;
388
    @(negedge FRE);
389
    TD = 9'h000;
390
    @(negedge FRE);
391
    TD = 9'h0AA;
392
    @(negedge FRE);
393
    TD = 9'h055;
394
    @(negedge FRE);
395
    TD = 9'h000;
396
    DAV = 0;
397
    @(negedge SS) #1;
398
    if(SS_Len != 512) begin
399
        $display("\tError: SS Length != 512; SS_Len = %d\n", SS_Len);
400
        $stop;
401
    end else begin
402
        $display("\tPass: SS Length == %d\n", SS_Len);
403
    end
404
 
405
    $display("Testing multi-cycle transfer with (Rate == 4)\n");
406
    Rate = 4;
407
    @(posedge Clk) #1;
408
    @(posedge Clk) #1;
409
    @(posedge Clk) #1;
410
    @(posedge Clk) #1;
411
 
412
    DAV = 1;
413
    TD = 9'h002;
414
    @(negedge FRE);
415
    TD = 9'h000;
416
    @(negedge FRE);
417
    TD = 9'h0AA;
418
    @(negedge FRE);
419
    TD = 9'h055;
420
    @(negedge FRE);
421
    TD = 9'h000;
422
    DAV = 0;
423
    @(negedge SS) #1;
424
    if(SS_Len != 1024) begin
425
        $display("\tError: SS Length != 1024; SS_Len = %d\n", SS_Len);
426
        $stop;
427
    end else begin
428
        $display("\tPass: SS Length == %d\n", SS_Len);
429
    end
430
 
431
    $display("Testing multi-cycle transfer with (Rate == 5)\n");
432
    Rate = 5;
433
    @(posedge Clk) #1;
434
    @(posedge Clk) #1;
435
    @(posedge Clk) #1;
436
    @(posedge Clk) #1;
437
 
438
    DAV = 1;
439
    TD = 9'h002;
440
    @(negedge FRE);
441
    TD = 9'h000;
442
    @(negedge FRE);
443
    TD = 9'h0AA;
444
    @(negedge FRE);
445
    TD = 9'h055;
446
    @(negedge FRE);
447
    TD = 9'h000;
448
    DAV = 0;
449
    @(negedge SS) #1;
450
    if(SS_Len != 2048) begin
451
        $display("\tError: SS Length != 2048; SS_Len = %d\n", SS_Len);
452
        $stop;
453
    end else begin
454
        $display("\tPass: SS Length == %d\n", SS_Len);
455
    end
456
 
457
    $display("Testing multi-cycle transfer with (Rate == 6)\n");
458
    Rate = 6;
459
    @(posedge Clk) #1;
460
    @(posedge Clk) #1;
461
    @(posedge Clk) #1;
462
    @(posedge Clk) #1;
463
 
464
    DAV = 1;
465
    TD = 9'h002;
466
    @(negedge FRE);
467
    TD = 9'h000;
468
    @(negedge FRE);
469
    TD = 9'h0AA;
470
    @(negedge FRE);
471
    TD = 9'h055;
472
    @(negedge FRE);
473
    TD = 9'h000;
474
    DAV = 0;
475
    @(negedge SS) #1;
476
    if(SS_Len != 4096) begin
477
        $display("\tError: SS Length != 4096; SS_Len = %d\n", SS_Len);
478
        $stop;
479
    end else begin
480
        $display("\tPass: SS Length == %d\n", SS_Len);
481
    end
482
 
483
    $display("Testing multi-cycle transfer with (Rate == 7)\n");
484
    Rate = 7;
485
    @(posedge Clk) #1;
486
    @(posedge Clk) #1;
487
    @(posedge Clk) #1;
488
    @(posedge Clk) #1;
489
 
490
    DAV = 1;
491
    TD = 9'h002;
492
    @(negedge FRE);
493
    TD = 9'h000;
494
    @(negedge FRE);
495
    TD = 9'h0AA;
496
    @(negedge FRE);
497
    TD = 9'h055;
498
    @(negedge FRE);
499
    TD = 9'h000;
500
    DAV = 0;
501
    @(negedge SS) #1;
502
    if(SS_Len != 8192) begin
503
        $display("\tError: SS Length != 8192; SS_Len = %d\n", SS_Len);
504
        $stop;
505
    end else begin
506
        $display("\tPass: SS Length == %d\n", SS_Len);
507
    end
508
 
509
    @(posedge Clk) #1;
510
    @(posedge Clk) #1;
511
    @(posedge Clk) #1;
512
    @(posedge Clk) #1;
513
 
514
    $stop;
515
end
516
 
517
////////////////////////////////////////////////////////////////////////////////
518
//
519
//  Define Clocks
520
//
521
 
522
always #5 Clk = ~Clk;
523
 
524
////////////////////////////////////////////////////////////////////////////////
525
 
526
always @(negedge SS) SS_Len = i;
527
 
528
always @(posedge Clk or negedge SS)
529
begin
530
    if(~SS)
531
        #10 i = 0;
532
    else
533
        i = i + 1;
534
end
535
 
536
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.