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[/] [spimaster/] [trunk/] [bench/] [testCase0.v] - Blame information for rev 4

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1 2 sfielding 
// ---------------------------------- testcase0.v ----------------------------
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`include "timescale.v"
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`include "spiMaster_defines.v"
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module testCase0();
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reg ack;
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reg [7:0] data;
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reg [15:0] dataWord;
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reg [7:0] dataRead;
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reg [7:0] dataWrite;
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integer i;
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integer j;
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initial
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begin
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  $write("\n\n");
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  //testHarness.reset;
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  #1000;
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  //write to block addr reg, and read back
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  //testHarness.u_wb_master_model.wb_write(1, `CTRL_STS_REG_BASE+`TRANS_TYPE_REG , 8'h5a);
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  $write("Testing register read/write\n");
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  testHarness.u_wb_master_model.wb_write(1, `CTRL_STS_REG_BASE+`SPI_CLK_DEL_REG , 8'h10);
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  testHarness.u_wb_master_model.wb_cmp(1, `CTRL_STS_REG_BASE+`SPI_CLK_DEL_REG , 8'h10);
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  testHarness.u_wb_master_model.wb_write(1, `CTRL_STS_REG_BASE+`SD_ADDR_7_0_REG , 8'h78);
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  testHarness.u_wb_master_model.wb_write(1, `CTRL_STS_REG_BASE+`SD_ADDR_15_8_REG , 8'h56);
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  testHarness.u_wb_master_model.wb_write(1, `CTRL_STS_REG_BASE+`SD_ADDR_23_16_REG , 8'h34);
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  testHarness.u_wb_master_model.wb_write(1, `CTRL_STS_REG_BASE+`SD_ADDR_31_24_REG , 8'h12);
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  testHarness.u_wb_master_model.wb_cmp(1, `CTRL_STS_REG_BASE+`SD_ADDR_7_0_REG , 8'h78);
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  testHarness.u_wb_master_model.wb_cmp(1, `CTRL_STS_REG_BASE+`SD_ADDR_15_8_REG , 8'h56);
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  testHarness.u_wb_master_model.wb_cmp(1, `CTRL_STS_REG_BASE+`SD_ADDR_23_16_REG , 8'h34);
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  testHarness.u_wb_master_model.wb_cmp(1, `CTRL_STS_REG_BASE+`SD_ADDR_31_24_REG , 8'h12);
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  //write one byte to spi bus, and wait for complete
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  $write("Testing SPI bus direct access\n");
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  testHarness.u_wb_master_model.wb_write(1, `CTRL_STS_REG_BASE+`TRANS_TYPE_REG , {6'b000000, `DIRECT_ACCESS});
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  testHarness.u_wb_master_model.wb_write(1, `CTRL_STS_REG_BASE+`DIRECT_ACCESS_DATA_REG , 8'h5f);
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  testHarness.u_wb_master_model.wb_write(1, `CTRL_STS_REG_BASE+`TRANS_CTRL_REG , {7'b0000000, `TRANS_START});
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  testHarness.u_wb_master_model.wb_read(1, `CTRL_STS_REG_BASE+`TRANS_STS_REG , dataRead);
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  while (dataRead[0] == `TRANS_BUSY)
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    testHarness.u_wb_master_model.wb_read(1, `CTRL_STS_REG_BASE+`TRANS_STS_REG , dataRead);
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  //write one byte to spi bus, and wait for complete
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  testHarness.u_wb_master_model.wb_write(1, `CTRL_STS_REG_BASE+`DIRECT_ACCESS_DATA_REG , 8'haa);
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  testHarness.u_wb_master_model.wb_write(1, `CTRL_STS_REG_BASE+`TRANS_CTRL_REG , {7'b0000000, `TRANS_START});
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  testHarness.u_wb_master_model.wb_read(1, `CTRL_STS_REG_BASE+`TRANS_STS_REG , dataRead);
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  while (dataRead[0] == `TRANS_BUSY)
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    testHarness.u_wb_master_model.wb_read(1, `CTRL_STS_REG_BASE+`TRANS_STS_REG , dataRead);
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  //init test
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  $write("Testing SD init\n");
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  testHarness.u_sdModel.setRespByte(8'h01);
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  testHarness.u_wb_master_model.wb_write(1, `CTRL_STS_REG_BASE+`TRANS_TYPE_REG , {6'b000000, `INIT_SD});
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  testHarness.u_wb_master_model.wb_write(1, `CTRL_STS_REG_BASE+`TRANS_CTRL_REG , {7'b0000000, `TRANS_START});
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  #60000;
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  testHarness.u_sdModel.setRespByte(8'h00);
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  testHarness.u_wb_master_model.wb_read(1, `CTRL_STS_REG_BASE+`TRANS_STS_REG , dataRead);
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  while (dataRead[0] == `TRANS_BUSY)
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    testHarness.u_wb_master_model.wb_read(1, `CTRL_STS_REG_BASE+`TRANS_STS_REG , dataRead);
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  testHarness.u_wb_master_model.wb_read(1, `CTRL_STS_REG_BASE+`TRANS_ERROR_REG , dataRead);
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  if (dataRead[1:0] == `INIT_NO_ERROR)
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    $write("SD init test passed\n");
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  else
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    $write("---- ERROR: SD init test failed. Error code = 0x%01x\n", dataRead[1:0] );
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  //block write
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  $write("Testing block write\n");
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  dataWrite = 8'h00;
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  for (i=0; i<=2; i=i+1) begin
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    testHarness.u_wb_master_model.wb_write(1, `TX_FIFO_BASE+`FIFO_DATA_REG , dataWrite);
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    dataWrite = dataWrite + 1'b1;
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  end
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  testHarness.u_wb_master_model.wb_write(1, `TX_FIFO_BASE+`FIFO_CONTROL_REG , 8'h01); //empty the fifo
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  dataWrite = 8'h00;
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  for (i=0; i<=511; i=i+1) begin
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    testHarness.u_wb_master_model.wb_write(1, `TX_FIFO_BASE+`FIFO_DATA_REG , dataWrite);
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    dataWrite = dataWrite + 1'b1;
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  end
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  testHarness.u_wb_master_model.wb_write(1, `CTRL_STS_REG_BASE+`TRANS_TYPE_REG , {6'b000000, `RW_WRITE_SD_BLOCK});
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  testHarness.u_wb_master_model.wb_write(1, `CTRL_STS_REG_BASE+`TRANS_CTRL_REG , {7'b0000000, `TRANS_START});
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  #100000;
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  testHarness.u_sdModel.setRespByte(8'h05); //write response
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  #8000000;
85 3 sfielding 
  #8000000;
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  #8000000;
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  #8000000;
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  #8000000;
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  #8000000;
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  #8000000;
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  testHarness.u_wb_master_model.wb_read(1, `CTRL_STS_REG_BASE+`TRANS_STS_REG , dataRead);
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  if (dataRead[0] == `TRANS_BUSY) begin
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    $write("---- ERROR: SD block write failed to complete\n");
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  end
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  else begin
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    testHarness.u_wb_master_model.wb_read(1, `CTRL_STS_REG_BASE+`TRANS_ERROR_REG , dataRead);
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    if (dataRead[5:4] == `WRITE_NO_ERROR)
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      $write("SD block write passed\n");
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    else
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      $write("---- ERROR: SD block write failed. Error code = 0x%01x\n", dataRead[5:4] );
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  end
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  //block read
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  $write("Testing block read\n");
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  testHarness.u_sdModel.setRespByte(8'h00); //cmd response
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  testHarness.u_wb_master_model.wb_write(1, `CTRL_STS_REG_BASE+`TRANS_TYPE_REG , {6'b000000, `RW_READ_SD_BLOCK});
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  testHarness.u_wb_master_model.wb_write(1, `CTRL_STS_REG_BASE+`TRANS_CTRL_REG , {7'b0000000, `TRANS_START});
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  #100000;
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  testHarness.u_sdModel.setRespByte(8'hfe); //read response
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  #8000000;
111 3 sfielding 
  #8000000;
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  #8000000;
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  #8000000;
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  #8000000;
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  #8000000;
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  #8000000;
117 2 sfielding 
  testHarness.u_wb_master_model.wb_read(1, `CTRL_STS_REG_BASE+`TRANS_STS_REG , dataRead);
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  if (dataRead[0] == `TRANS_BUSY) begin
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    $write("---- ERROR: SD block read failed to complete\n");
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  end
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  else begin
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    testHarness.u_wb_master_model.wb_read(1, `CTRL_STS_REG_BASE+`TRANS_ERROR_REG , dataRead);
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    if (dataRead[3:2] == `READ_NO_ERROR) begin
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      $write("SD block read passed\n");
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      for (j=0; j<=15; j=j+1) begin
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        $write("Data 0x%0x = ",j*32);
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        for (i=0; i<=31; i=i+1) begin
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          testHarness.u_wb_master_model.wb_read(1, `RX_FIFO_BASE+`FIFO_DATA_REG , dataRead);
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          $write("0x%0x ",dataRead);
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        end
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        $write("\n");
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      end
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    end
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    else
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      $write("---- ERROR: SD block read failed. Error code = 0x%01x\n", dataRead[3:2] );
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  end
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  $write("Finished all tests\n");
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  $stop;
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end
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endmodule
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