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[/] [spislave/] [trunk/] [spislave/] [rtl/] [verilog/] [spigpio.v] - Blame information for rev 4

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// RTL program for SPI GPIO -- shift 8 bit register
 
`define         P0_P9_OP        8'b10101010 //0xAA
`define         P0_P3_OP        8'b11111111 //0xFF
`define         P4_P7_OP        8'b11111110 //0xFE
 
module spigpio(clk, cs, sr_in, gpioout, sr_out);
 
        input clk, cs;
        input sr_in;
        output sr_out;
        output [7:0] gpioout;
 
        reg [7:0] gpioout;
        reg sr_out;
 
        wire rw;
        reg [7:0] sr;
 
        assign rw = sr[7];
 
        always@(posedge clk )
        begin
                if (cs == 1'b0)
                begin
                        sr_out <= sr[7];
                        sr[7:1] <= sr[6:0];
                        sr[0] <= sr_in;
                end
 
                if (cs == 1'b1)
                begin
 
                        if (rw == 1'b1)
                        begin
 
                                case (sr)
                                `P0_P9_OP : gpioout[7:0] <= { sr[0], sr[1], sr[2], sr[3],
                                                              sr[4], sr[5], sr[6], sr[7]};
                                `P0_P3_OP : gpioout[3:0] <= {sr[0], sr[1], sr[2], sr[3]};
                                `P4_P7_OP : gpioout[7:4] <= { sr[4], sr[5], sr[6], sr[7]};
                                default   : gpioout[0] <= sr[0];
                                endcase
                        end
                end
        end
endmodule

Line No.	Rev	Author	Line
1	4	siva12	`// RTL program for SPI GPIO -- shift 8 bit register`
2
3			`define P0_P9_OP 8'b10101010 //0xAA
4			`define P0_P3_OP 8'b11111111 //0xFF
5			`define P4_P7_OP 8'b11111110 //0xFE
6
7			`module spigpio(clk, cs, sr_in, gpioout, sr_out);`
8
9			`input clk, cs;`
10			`input sr_in;`
11			`output sr_out;`
12			`output [7:0] gpioout;`
13
14			`reg [7:0] gpioout;`
15			`reg sr_out;`
16
17			`wire rw;`
18			`reg [7:0] sr;`
19
20			`assign rw = sr[7];`
21
22			`always@(posedge clk )`
23			`begin`
24			`if (cs == 1'b0)`
25			`begin`
26			`sr_out <= sr[7];`
27			`sr[7:1] <= sr[6:0];`
28			`sr[0] <= sr_in;`
29			`end`
30
31			`if (cs == 1'b1)`
32			`begin`
33
34			`if (rw == 1'b1)`
35			`begin`
36
37			`case (sr)`
38			`P0_P9_OP : gpioout[7:0] <= { sr[0], sr[1], sr[2], sr[3],
39			`sr[4], sr[5], sr[6], sr[7]};`
40			`P0_P3_OP : gpioout[3:0] <= {sr[0], sr[1], sr[2], sr[3]};
41			`P4_P7_OP : gpioout[7:4] <= { sr[4], sr[5], sr[6], sr[7]};
42			`default : gpioout[0] <= sr[0];`
43			`endcase`
44			`end`
45			`end`
46			`end`
47			`endmodule`

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[/] [spislave/] [trunk/] [spislave/] [rtl/] [verilog/] [spigpio.v] - Blame information for rev 4