| 1 |
5 |
siva12 |
////////////////////////////////////////////////////////////////// ////
|
| 2 |
|
|
//// ////
|
| 3 |
|
|
//// SPI SLAVE IP Core ////
|
| 4 |
|
|
//// ////
|
| 5 |
|
|
//// This file is part of the spislave project ////
|
| 6 |
|
|
//// http://www.opencores.org/project,spislave ////
|
| 7 |
|
|
//// ////
|
| 8 |
|
|
//// Description ////
|
| 9 |
|
|
//// Implementation of spislave IP core according to ////
|
| 10 |
|
|
//// spislave IP core specification document. ////
|
| 11 |
|
|
//// ////
|
| 12 |
|
|
//// To Do: ////
|
| 13 |
|
|
//// - ////
|
| 14 |
|
|
//// ////
|
| 15 |
|
|
//// Author(s): ////
|
| 16 |
|
|
//// - Sivakumar.B , email: sivabsk12@yahoo.co.in ////
|
| 17 |
|
|
//// Engr Zilogic systems, chennai, www.zilogic.com ////
|
| 18 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 19 |
|
|
//// ////
|
| 20 |
|
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
| 21 |
|
|
//// ////
|
| 22 |
|
|
//// This source file may be used and distributed without ////
|
| 23 |
|
|
//// restriction provided that this copyright statement is not ////
|
| 24 |
|
|
//// removed from the file and that any derivative work contains ////
|
| 25 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
| 26 |
|
|
//// ////
|
| 27 |
|
|
//// This source file is free software; you can redistribute it ////
|
| 28 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
| 29 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
| 30 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
| 31 |
|
|
//// later version. ////
|
| 32 |
|
|
//// ////
|
| 33 |
|
|
//// This source is distributed in the hope that it will be ////
|
| 34 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
| 35 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
| 36 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
| 37 |
|
|
//// details. ////
|
| 38 |
|
|
//// ////
|
| 39 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
| 40 |
|
|
//// Public License along with this source; if not, download it ////
|
| 41 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
| 42 |
|
|
//// ////
|
| 43 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 44 |
|
|
//// RTL program for SPI GPIO -- shift 8 bit register ////
|
| 45 |
4 |
siva12 |
|
| 46 |
|
|
`define P0_P9_OP 8'b10101010 //0xAA
|
| 47 |
|
|
`define P0_P3_OP 8'b11111111 //0xFF
|
| 48 |
|
|
`define P4_P7_OP 8'b11111110 //0xFE
|
| 49 |
|
|
|
| 50 |
|
|
module spigpio(clk, cs, sr_in, gpioout, sr_out);
|
| 51 |
|
|
|
| 52 |
|
|
input clk, cs;
|
| 53 |
|
|
input sr_in;
|
| 54 |
|
|
output sr_out;
|
| 55 |
|
|
output [7:0] gpioout;
|
| 56 |
|
|
|
| 57 |
|
|
reg [7:0] gpioout;
|
| 58 |
|
|
reg sr_out;
|
| 59 |
|
|
|
| 60 |
|
|
wire rw;
|
| 61 |
|
|
reg [7:0] sr;
|
| 62 |
|
|
|
| 63 |
|
|
assign rw = sr[7];
|
| 64 |
|
|
|
| 65 |
|
|
always@(posedge clk )
|
| 66 |
|
|
begin
|
| 67 |
|
|
if (cs == 1'b0)
|
| 68 |
|
|
begin
|
| 69 |
|
|
sr_out <= sr[7];
|
| 70 |
|
|
sr[7:1] <= sr[6:0];
|
| 71 |
|
|
sr[0] <= sr_in;
|
| 72 |
|
|
end
|
| 73 |
|
|
|
| 74 |
|
|
if (cs == 1'b1)
|
| 75 |
|
|
begin
|
| 76 |
|
|
|
| 77 |
|
|
if (rw == 1'b1)
|
| 78 |
|
|
begin
|
| 79 |
|
|
|
| 80 |
|
|
case (sr)
|
| 81 |
|
|
`P0_P9_OP : gpioout[7:0] <= { sr[0], sr[1], sr[2], sr[3],
|
| 82 |
|
|
sr[4], sr[5], sr[6], sr[7]};
|
| 83 |
|
|
`P0_P3_OP : gpioout[3:0] <= {sr[0], sr[1], sr[2], sr[3]};
|
| 84 |
|
|
`P4_P7_OP : gpioout[7:4] <= { sr[4], sr[5], sr[6], sr[7]};
|
| 85 |
|
|
default : gpioout[0] <= sr[0];
|
| 86 |
|
|
endcase
|
| 87 |
|
|
end
|
| 88 |
|
|
end
|
| 89 |
|
|
end
|
| 90 |
|
|
endmodule
|
