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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  weigand_tx_top.v                                            ////
////                                                              ////
////                                                              ////
////  This file is part of the Time Triggered Protocol Controller ////
////  http://www.opencores.org/projects/weigand/                  ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////       Jeff Anderson                                          ////
////       jeaander@opencores.org                                 ////
////                                                              ////
////                                                              ////
////  All additional information is available in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2013 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//// The Weigand protocol is maintained by                        ////
//// This product has been tested to interoperate with certified  ////
//// devices, but has not been certified itself.  This product    ////
//// should be certified through prior to claiming strict         ////
//// adherence to the standard.                                   ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
//  Revisions at end of file
//
 
`include "timescale.v"
`include "SPORT_defines.v"
 
module testbench_top;
  reg [5:0]   wb_addr_i;
  reg [31:0]  wb_dat_i;
  wire [31:0] wb_dat_o;
  wire [31:0] wb_dat_o_rx;
  reg         wb_cyc_i;
  reg         wb_stb_i;
  reg [2:0]   wb_cti_i;
  reg [3:0]   wb_sel_i;
  reg         wb_we_i;
  reg         wb_rst_i;
  reg         wb_clk_i;
  reg         one_i, zero_i;
 
  //DUTs
  sport_top sport_top(wb_clk_i,wb_rst_i,wb_dat_i,wb_dat_o,wb_cyc_i,wb_stb_i,wb_cti_i,wb_sel_i,wb_we_i,wb_addr_i,
                      wb_ack_o,wb_err_o,wb_rty_o, DTxPRI,DTxSEC,TSCLKx,TFSx,DRxPRI,DRxSEC,RSCLKx,TRSx,);
 
  //tasks for simulation
 
  initial begin
    wb_addr_i = 6'h0;
    wb_dat_i = 32'h0;
    wb_cyc_i = 1'b0;
    wb_stb_i = 1'b0;
    wb_we_i = 1'b0;
    wb_rst_i = 1'b0;
    wb_clk_i = 1'b0;
    one_i = 1'b1;
    zero_i = 1'b1;
  end
 
  always
    #5 wb_clk_i = !wb_clk_i;
 
  /**********************   tasks run by testcases for this testbench ******************/
  //SPORT bus write tasks
  task SPORT_write;
    input [63:0] SPORT_data;
    input [5:0]  word_length;
    input [5:0]  p2p;
    input [5:0]  pw;
    integer i;
    integer j;
    begin
      j = 0;
      repeat (word_length) begin
        @ (posedge wb_clk_i) begin
          if (SPORT_data[j] == 1'b0) begin
            SPORT0(pw);
          end
          else begin
            SPORT1(pw);
          end
          j=j+1;
          i = 0;
          while(i <= p2p) begin
            @ (posedge wb_clk_i) begin i=i+1; end
          end
        end
      end
    end
  endtask
 
  task SPORT0;
    input [5:0] pw;
    integer i;
    begin
      for (i = 0; i <= pw; i=i+1) begin
        @(posedge wb_clk_i)  zero_i = 1'b0;
      end
      zero_i = 1'b1;
    end
  endtask
 
  task SPORT1;
    input [5:0] pw;
    integer i;
    begin
      for (i = 0; i <= pw; i=i+1) begin
        @(posedge wb_clk_i)  one_i = 1'b0;
      end
      one_i = 1'b1;
    end
  endtask
 
  //Wishbone readn adn write tasks
  task wb_rst;
    begin
          wb_rst_i = 1'b1;
      #20 wb_rst_i = 1'b0;
    end
  endtask
 
  task wb_write_async;
    input [31:0] wb_data;
    begin
      @ (posedge wb_clk_i) begin
        wb_addr_i = `SPORT_ADDR;
        wb_dat_i = wb_data;
        wb_stb_i = 1'b1;
        wb_cyc_i = 1'b1;
        wb_we_i = 1'b1;
      end
      @ (posedge wb_clk_i) begin
        wb_addr_i = 6'h0;
        wb_dat_i = 32'h0;
        wb_stb_i = 1'b0;
        wb_cyc_i = 1'b0;
        wb_we_i = 1'b0;
      end
    end
  endtask
 
  task wb_write_sync;
    input [31:0] wb_data;
    begin
      @ (posedge wb_clk_i) begin
        wb_addr_i = `SPORT_ADDR;
        wb_dat_i = wb_data;
        wb_stb_i = 1'b1;
        wb_cyc_i = 1'b1;
        wb_we_i = 1'b1;
      end
      @ (posedge wb_clk_i) begin
        wb_addr_i = `SPORT_ADDR;
        wb_dat_i = wb_data;
        wb_stb_i = 1'b1;
        wb_cyc_i = 1'b1;
        wb_we_i = 1'b1;
      end
      @ (posedge wb_clk_i) begin
        wb_addr_i = 6'h0;
        wb_dat_i = 32'h0;
        wb_stb_i = 1'b0;
        wb_cyc_i = 1'b0;
        wb_we_i = 1'b0;
      end
    end
  endtask
 
  task wb_writep2p_async;
    input [31:0] p2p;
    begin
      @ (posedge wb_clk_i) begin
        wb_addr_i = `WB_CNFG_P2P;
        wb_dat_i = p2p;
        wb_stb_i = 1'b1;
        wb_cyc_i = 1'b1;
        wb_we_i = 1'b1;
      end
      @ (posedge wb_clk_i) begin
        wb_addr_i = 6'h0;
        wb_dat_i = 32'h0;
        wb_stb_i = 1'b0;
        wb_cyc_i = 1'b0;
        wb_we_i = 1'b0;
      end
    end
  endtask
 
  task wb_writepw_async;
    input [31:0] pw;
    begin
      @ (posedge wb_clk_i) begin
        wb_addr_i = `WB_CNFG_PW;
        wb_dat_i = pw;
        wb_stb_i = 1'b1;
        wb_cyc_i = 1'b1;
        wb_we_i = 1'b1;
      end
      @ (posedge wb_clk_i) begin
        wb_addr_i = 6'h0;
        wb_dat_i = 32'h0;
        wb_stb_i = 1'b0;
        wb_cyc_i = 1'b0;
        wb_we_i = 1'b0;
      end
    end
  endtask
 
  task wb_writesize_async;
    input [31:0] size;
    begin
      @ (posedge wb_clk_i) begin
        wb_addr_i = `WB_CNFG_MSGSIZE;
        wb_dat_i = (size & 32'h7F);
        wb_stb_i = 1'b1;
        wb_cyc_i = 1'b1;
        wb_we_i = 1'b1;
      end
      @ (posedge wb_clk_i) begin
        wb_addr_i = 6'h0;
        wb_dat_i = 32'h0;
        wb_stb_i = 1'b0;
        wb_cyc_i = 1'b0;
        wb_we_i = 1'b0;
      end
    end
  endtask
 
  task wb_writesend_async;
    input [31:0] size;
    begin
      @ (posedge wb_clk_i) begin
        wb_addr_i = `WB_CNFG_MSGSIZE;
        wb_dat_i = (size | 32'h80);
        wb_stb_i = 1'b1;
        wb_cyc_i = 1'b1;
        wb_we_i = 1'b1;
      end
      @ (posedge wb_clk_i) begin
        wb_addr_i = 6'h0;
        wb_dat_i = 32'h0;
        wb_stb_i = 1'b0;
        wb_cyc_i = 1'b0;
        wb_we_i = 1'b0;
      end
    end
  endtask
 
  task wb_read_async;
    begin
      @ (posedge wb_clk_i) begin
        wb_stb_i = 1'b1;
        wb_cyc_i = 1'b1;
        wb_we_i = 1'b0;
      end
      @ (posedge wb_clk_i) begin
        wb_stb_i = 1'b0;
        wb_cyc_i = 1'b0;
      end
    end
  endtask
 
  task wb_read_sync;
    begin
      @ (posedge wb_clk_i) begin
        wb_stb_i = 1'b1;
        wb_cyc_i = 1'b1;
        wb_we_i = 1'b0;
      end
      @ (posedge wb_clk_i) begin
        wb_stb_i = 1'b1;
        wb_cyc_i = 1'b1;
      end
      @ (posedge wb_clk_i) begin
        wb_stb_i = 1'b0;
        wb_cyc_i = 1'b0;
      end
    end
  endtask
 
endmodule

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[/] [sport/] [trunk/] [bench/] [testbench_top.v.bak] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	jeaander	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// weigand_tx_top.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the Time Triggered Protocol Controller ////`
7			`//// http://www.opencores.org/projects/weigand/ ////`
8			`//// ////`
9			`//// ////`
10			`//// Author(s): ////`
11			`//// Jeff Anderson ////`
12			`//// jeaander@opencores.org ////`
13			`//// ////`
14			`//// ////`
15			`//// All additional information is available in the README.txt ////`
16			`//// file. ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2013 Authors ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//// The Weigand protocol is maintained by ////`
44			`//// This product has been tested to interoperate with certified ////`
45			`//// devices, but has not been certified itself. This product ////`
46			`//// should be certified through prior to claiming strict ////`
47			`//// adherence to the standard. ////`
48			`//// ////`
49			`//////////////////////////////////////////////////////////////////////`
50			`//`
51			`// Revisions at end of file`
52			`//`
53
54			`include "timescale.v"
55			`include "SPORT_defines.v"
56
57			`module testbench_top;`
58			`reg [5:0] wb_addr_i;`
59			`reg [31:0] wb_dat_i;`
60			`wire [31:0] wb_dat_o;`
61			`wire [31:0] wb_dat_o_rx;`
62			`reg wb_cyc_i;`
63			`reg wb_stb_i;`
64			`reg [2:0] wb_cti_i;`
65			`reg [3:0] wb_sel_i;`
66			`reg wb_we_i;`
67			`reg wb_rst_i;`
68			`reg wb_clk_i;`
69			`reg one_i, zero_i;`
70
71			`//DUTs`
72			`sport_top sport_top(wb_clk_i,wb_rst_i,wb_dat_i,wb_dat_o,wb_cyc_i,wb_stb_i,wb_cti_i,wb_sel_i,wb_we_i,wb_addr_i,`
73			`wb_ack_o,wb_err_o,wb_rty_o, DTxPRI,DTxSEC,TSCLKx,TFSx,DRxPRI,DRxSEC,RSCLKx,TRSx,);`
74
75			`//tasks for simulation`
76
77			`initial begin`
78			`wb_addr_i = 6'h0;`
79			`wb_dat_i = 32'h0;`
80			`wb_cyc_i = 1'b0;`
81			`wb_stb_i = 1'b0;`
82			`wb_we_i = 1'b0;`
83			`wb_rst_i = 1'b0;`
84			`wb_clk_i = 1'b0;`
85			`one_i = 1'b1;`
86			`zero_i = 1'b1;`
87			`end`
88
89			`always`
90			`#5 wb_clk_i = !wb_clk_i;`
91
92			`/******************** tasks run by testcases for this testbench ****************/`
93			`//SPORT bus write tasks`
94			`task SPORT_write;`
95			`input [63:0] SPORT_data;`
96			`input [5:0] word_length;`
97			`input [5:0] p2p;`
98			`input [5:0] pw;`
99			`integer i;`
100			`integer j;`
101			`begin`
102			`j = 0;`
103			`repeat (word_length) begin`
104			`@ (posedge wb_clk_i) begin`
105			`if (SPORT_data[j] == 1'b0) begin`
106			`SPORT0(pw);`
107			`end`
108			`else begin`
109			`SPORT1(pw);`
110			`end`
111			`j=j+1;`
112			`i = 0;`
113			`while(i <= p2p) begin`
114			`@ (posedge wb_clk_i) begin i=i+1; end`
115			`end`
116			`end`
117			`end`
118			`end`
119			`endtask`
120
121			`task SPORT0;`
122			`input [5:0] pw;`
123			`integer i;`
124			`begin`
125			`for (i = 0; i <= pw; i=i+1) begin`
126			`@(posedge wb_clk_i) zero_i = 1'b0;`
127			`end`
128			`zero_i = 1'b1;`
129			`end`
130			`endtask`
131
132			`task SPORT1;`
133			`input [5:0] pw;`
134			`integer i;`
135			`begin`
136			`for (i = 0; i <= pw; i=i+1) begin`
137			`@(posedge wb_clk_i) one_i = 1'b0;`
138			`end`
139			`one_i = 1'b1;`
140			`end`
141			`endtask`
142
143			`//Wishbone readn adn write tasks`
144			`task wb_rst;`
145			`begin`
146			`wb_rst_i = 1'b1;`
147			`#20 wb_rst_i = 1'b0;`
148			`end`
149			`endtask`
150
151			`task wb_write_async;`
152			`input [31:0] wb_data;`
153			`begin`
154			`@ (posedge wb_clk_i) begin`
155			wb_addr_i = `SPORT_ADDR;
156			`wb_dat_i = wb_data;`
157			`wb_stb_i = 1'b1;`
158			`wb_cyc_i = 1'b1;`
159			`wb_we_i = 1'b1;`
160			`end`
161			`@ (posedge wb_clk_i) begin`
162			`wb_addr_i = 6'h0;`
163			`wb_dat_i = 32'h0;`
164			`wb_stb_i = 1'b0;`
165			`wb_cyc_i = 1'b0;`
166			`wb_we_i = 1'b0;`
167			`end`
168			`end`
169			`endtask`
170
171			`task wb_write_sync;`
172			`input [31:0] wb_data;`
173			`begin`
174			`@ (posedge wb_clk_i) begin`
175			wb_addr_i = `SPORT_ADDR;
176			`wb_dat_i = wb_data;`
177			`wb_stb_i = 1'b1;`
178			`wb_cyc_i = 1'b1;`
179			`wb_we_i = 1'b1;`
180			`end`
181			`@ (posedge wb_clk_i) begin`
182			wb_addr_i = `SPORT_ADDR;
183			`wb_dat_i = wb_data;`
184			`wb_stb_i = 1'b1;`
185			`wb_cyc_i = 1'b1;`
186			`wb_we_i = 1'b1;`
187			`end`
188			`@ (posedge wb_clk_i) begin`
189			`wb_addr_i = 6'h0;`
190			`wb_dat_i = 32'h0;`
191			`wb_stb_i = 1'b0;`
192			`wb_cyc_i = 1'b0;`
193			`wb_we_i = 1'b0;`
194			`end`
195			`end`
196			`endtask`
197
198			`task wb_writep2p_async;`
199			`input [31:0] p2p;`
200			`begin`
201			`@ (posedge wb_clk_i) begin`
202			wb_addr_i = `WB_CNFG_P2P;
203			`wb_dat_i = p2p;`
204			`wb_stb_i = 1'b1;`
205			`wb_cyc_i = 1'b1;`
206			`wb_we_i = 1'b1;`
207			`end`
208			`@ (posedge wb_clk_i) begin`
209			`wb_addr_i = 6'h0;`
210			`wb_dat_i = 32'h0;`
211			`wb_stb_i = 1'b0;`
212			`wb_cyc_i = 1'b0;`
213			`wb_we_i = 1'b0;`
214			`end`
215			`end`
216			`endtask`
217
218			`task wb_writepw_async;`
219			`input [31:0] pw;`
220			`begin`
221			`@ (posedge wb_clk_i) begin`
222			wb_addr_i = `WB_CNFG_PW;
223			`wb_dat_i = pw;`
224			`wb_stb_i = 1'b1;`
225			`wb_cyc_i = 1'b1;`
226			`wb_we_i = 1'b1;`
227			`end`
228			`@ (posedge wb_clk_i) begin`
229			`wb_addr_i = 6'h0;`
230			`wb_dat_i = 32'h0;`
231			`wb_stb_i = 1'b0;`
232			`wb_cyc_i = 1'b0;`
233			`wb_we_i = 1'b0;`
234			`end`
235			`end`
236			`endtask`
237
238			`task wb_writesize_async;`
239			`input [31:0] size;`
240			`begin`
241			`@ (posedge wb_clk_i) begin`
242			wb_addr_i = `WB_CNFG_MSGSIZE;
243			`wb_dat_i = (size & 32'h7F);`
244			`wb_stb_i = 1'b1;`
245			`wb_cyc_i = 1'b1;`
246			`wb_we_i = 1'b1;`
247			`end`
248			`@ (posedge wb_clk_i) begin`
249			`wb_addr_i = 6'h0;`
250			`wb_dat_i = 32'h0;`
251			`wb_stb_i = 1'b0;`
252			`wb_cyc_i = 1'b0;`
253			`wb_we_i = 1'b0;`
254			`end`
255			`end`
256			`endtask`
257
258			`task wb_writesend_async;`
259			`input [31:0] size;`
260			`begin`
261			`@ (posedge wb_clk_i) begin`
262			wb_addr_i = `WB_CNFG_MSGSIZE;
263			`wb_dat_i = (size \| 32'h80);`
264			`wb_stb_i = 1'b1;`
265			`wb_cyc_i = 1'b1;`
266			`wb_we_i = 1'b1;`
267			`end`
268			`@ (posedge wb_clk_i) begin`
269			`wb_addr_i = 6'h0;`
270			`wb_dat_i = 32'h0;`
271			`wb_stb_i = 1'b0;`
272			`wb_cyc_i = 1'b0;`
273			`wb_we_i = 1'b0;`
274			`end`
275			`end`
276			`endtask`
277
278			`task wb_read_async;`
279			`begin`
280			`@ (posedge wb_clk_i) begin`
281			`wb_stb_i = 1'b1;`
282			`wb_cyc_i = 1'b1;`
283			`wb_we_i = 1'b0;`
284			`end`
285			`@ (posedge wb_clk_i) begin`
286			`wb_stb_i = 1'b0;`
287			`wb_cyc_i = 1'b0;`
288			`end`
289			`end`
290			`endtask`
291
292			`task wb_read_sync;`
293			`begin`
294			`@ (posedge wb_clk_i) begin`
295			`wb_stb_i = 1'b1;`
296			`wb_cyc_i = 1'b1;`
297			`wb_we_i = 1'b0;`
298			`end`
299			`@ (posedge wb_clk_i) begin`
300			`wb_stb_i = 1'b1;`
301			`wb_cyc_i = 1'b1;`
302			`end`
303			`@ (posedge wb_clk_i) begin`
304			`wb_stb_i = 1'b0;`
305			`wb_cyc_i = 1'b0;`
306			`end`
307			`end`
308			`endtask`
309
310			`endmodule`