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[/] [sport/] [trunk/] [bench/] [testcase_1.v] - Blame information for rev 2

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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  weigand_tx_top.v                                            ////
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////                                                              ////
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////                                                              ////
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////  This file is part of the Time Triggered Protocol Controller ////
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////  http://www.opencores.org/projects/weigand/                  ////
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////                                                              ////
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////                                                              ////
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////  Author(s):                                                  ////
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////       Jeff Anderson                                          ////
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////       jeaander@opencores.org                                 ////
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////                                                              ////
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////                                                              ////
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////  All additional information is available in the README.txt   ////
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////  file.                                                       ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2013 Authors                                   ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//// The Weigand protocol is maintained by                        ////
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//// This product has been tested to interoperate with certified  ////
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//// devices, but has not been certified itself.  This product    ////
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//// should be certified through prior to claiming strict         ////
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//// adherence to the standard.                                   ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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//  Revisions at end of file
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//
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`include "timescale.v"
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`include "sport_defines.v"
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`include "testbench_top.v"
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module testcase_1;
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  testbench_top testbench();
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  initial
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  begin
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    testbench.wb_rst;
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    //#40 testbench.wb_write_async(32'h0);
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    //#40 testbench.wb_write_sync(32'h0);
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    //#40 testbench.wb_read_async;
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    //#40 testbench.wb_read_sync;
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    //write a small word adn send
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    #40 testbench.wb_write_async(32'hA5A5A50F);
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    #40 testbench.wb_writep2p_async(32'h7);
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    #40 testbench.wb_writepw_async(32'h3);
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    #40 testbench.wb_writesize_async(32'h87);
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    #40 testbench.wb_writesend_async(32'h7);
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    #40 testbench.wiegand_write(32'hA5, 6'h5, 6'h7, 6'h3);
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    //now write a 32 bit word
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    #1040 testbench.wb_write_async(32'hA5A5A50F);
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    #40 testbench.wb_writep2p_async(32'h7);
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    #40 testbench.wb_writepw_async(32'h3);
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    #40 testbench.wb_writesend_async(32'b00011111);
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    #40 testbench.wiegand_write(32'hA5A5A50F, 6'h20, 6'h7, 6'h3);
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    //now write a 35 bit word
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    #4040 testbench.wb_write_async(32'hA5A5A50F);
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    #40 testbench.wb_write_async(32'h33333333);
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    #40 testbench.wb_writep2p_async(32'h7);
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    #40 testbench.wb_writepw_async(32'h3);
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    #40 testbench.wb_writesend_async(32'b00100010);
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    #40 testbench.wiegand_write(40'hF0A5A5A50F, 6'h25, 6'h7, 6'h3);
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    #10000 $stop;
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  end
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endmodule

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