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//// ////
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//// wb_interface.v ////
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//// ////
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//// ////
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//// This file is part of the SPORT Controller ////
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//// http://www.opencores.org/projects/sport/ ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Jeff Anderson ////
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//// jeaander@opencores.org ////
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//// ////
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//// ////
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//// All additional information is available in the README.txt ////
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//// file. ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2013 Authors ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// Revisions at end of file
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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//WB interface definitions imported from wiegand_defines
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`include "sport_defines.v"
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module wb_interface_sport (
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// WB bus
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wb_rst_i,
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wb_clk_i,
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wb_stb_i,
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wb_ack_o,
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wb_addr_i,
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wb_we_i,
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wb_dat_i,
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wb_sel_i,
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wb_dat_o,
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wb_cyc_i,
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wb_cti_i,
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wb_err_o,
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wb_rty_o,
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rxsampleCnt,
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rxpacketCnt,
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txsampleCnt,
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txpacketCnt,
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dat_i,
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dat_o,
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rxsecEn,
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rxlateFS_earlyFSn,
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txsecEn,
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txlateFS_earlyFSn,
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tx_actHi,
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rx_actHi,
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msbFirst,
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tx_start,
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rx_start,
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rx_int
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);
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//--------------------------------------
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// Wish Bone Interface
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// -------------------------------------
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input wb_rst_i;
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input wb_clk_i;
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input wb_stb_i;
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output wb_ack_o;
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input [`WB_ADDR_WIDTH-1:0] wb_addr_i;
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input wb_we_i; // 1 - Write , 0 - Read
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input [`WB_WIDTH-1:0] wb_dat_i;
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input [(`WB_WIDTH/8)-1:0] wb_sel_i; // Byte enable
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output [`WB_WIDTH-1:0] dat_o;
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input [`WB_WIDTH-1:0] dat_i; //data to and from WB interface, but not on WB
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output [`WB_WIDTH-1:0] wb_dat_o;
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input wb_cyc_i;
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input [2:0] wb_cti_i;
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output wb_err_o;
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output wb_rty_o;
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//----------------------------------------
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// interface to SPORT control logic
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//----------------------------------------
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output [4:0] rxsampleCnt;
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output [`SPORT_FIFODEPTH-1:0] rxpacketCnt;
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output [4:0] txsampleCnt;
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output [`SPORT_FIFODEPTH-1:0] txpacketCnt;
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output rxsecEn;
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output rxlateFS_earlyFSn;
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output txsecEn;
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output txlateFS_earlyFSn;
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output tx_actHi;
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output rx_actHi;
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output msbFirst;
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output tx_start, rx_start;
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output rx_int;
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reg [`WB_WIDTH-1:0] rxreg;
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reg [`WB_WIDTH-1:0] txreg;
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wire err_int;
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wire rty_int;
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wire full;
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/************************ standard WB stuff ***************************/
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reg ack,err,rty;
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assign wb_ack_o = ack;
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assign wb_err_o = err;
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assign wb_rty_o = rty;
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assign rst_o = wb_rst_i;
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assign rst = wb_rst_i;
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assign dat_o = wb_dat_i;
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assign ack_o = ack;
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assign stb_o = wb_stb_i;
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assign cyc_o = wb_cyc_i;
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assign we_o = wb_we_i;
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//ACK logic
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always @(posedge wb_clk_i or posedge rst) begin
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if (rst) ack <= 1'b0;
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else ack <= (~|(`SPORT_ADDR_MASK & wb_addr_i) & wb_stb_i & wb_cyc_i & ~err_int & ~rty_int);
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end
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//ERR logic if the FIFO is full
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assign err_int = (~(wb_addr_i ^ `SPORT_ADDR) & wb_stb_i & wb_cyc_i & wb_we_i & full);
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always @(posedge wb_clk_i or posedge rst) begin
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if (rst) err <= 1'b0;
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else err <= err_int;
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end
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//retry if we're in the middle of a write cycle
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assign rty_int = (~|(`SPORT_ADDR_MASK & wb_addr_i) & wb_stb_i & wb_cyc_i & wb_we_i);
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always @(posedge wb_clk_i or posedge rst) begin
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if (rst) rty <= 1'b0;
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else rty <= rty_int;
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end
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//pass-thru clock
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assign clk_o = wb_clk_i;
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/************************ configuration registers *************************/
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assign lock_cfg_rx = rxreg[`SPORT_FIFODEPTH+10];
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assign lock_cfg_tx = txreg[`SPORT_FIFODEPTH+10];
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assign rxsecEn = rxreg[`SPORT_FIFODEPTH+9];
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assign rxlateFS_earlyFSn = rxreg[`SPORT_FIFODEPTH+8];
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assign txsecEn = txreg[`SPORT_FIFODEPTH+9];
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assign txlateFS_earlyFSn = txreg[`SPORT_FIFODEPTH+8];
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assign tx_actHi = txreg[`SPORT_FIFODEPTH+7];
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assign rx_actHi = rxreg[`SPORT_FIFODEPTH+7];
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assign tx_start = txreg[`SPORT_FIFODEPTH+6];
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assign msbFirst = txreg[`SPORT_FIFODEPTH+5];
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assign rx_start = rxreg[`SPORT_FIFODEPTH+6];
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assign rx_int = rxreg[`SPORT_FIFODEPTH+5];
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assign rxsampleCnt = rxreg[`SPORT_FIFODEPTH+4:`SPORT_FIFODEPTH];
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assign rxpacketCnt = rxreg[`SPORT_FIFODEPTH-1:0];
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assign txsampleCnt = txreg[`SPORT_FIFODEPTH+4:`SPORT_FIFODEPTH];
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assign txpacketCnt = txreg[`SPORT_FIFODEPTH-1:0];
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//defines the pulse width of the controller
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always @(negedge wb_clk_i or posedge rst) begin
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if (rst) rxreg <= `WB_WIDTH'hA;
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else if ((wb_addr_i == `WB_CNFG_RX) && (wb_stb_i & wb_cyc_i & wb_we_i & ~lock_cfg_rx)) rxreg <= wb_dat_i;
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end
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//defines the pulse to pulse delayof the controller
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always @(negedge wb_clk_i or posedge rst) begin
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if (rst) txreg <= `WB_WIDTH'h0;
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else if ((wb_addr_i == `WB_CNFG_TX) && (wb_stb_i & wb_cyc_i & wb_we_i & ~lock_cfg_tx)) txreg <= wb_dat_i;
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end
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//readback registers on valid WB read cycle
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assign wb_dat_rdbk = ((wb_addr_i == `WB_CNFG_RX)? rxreg : txreg);
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assign wb_dat_o = (wb_stb_i & wb_cyc_i & ~wb_we_i)? wb_dat_rdbk : `WB_WIDTH'hz;
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/******************************* DATA FIFO ********************************************/
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//fifo for TX data.
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assign wb_wr_en = (wb_addr_i == `SPORT_ADDR) && (wb_stb_i & wb_cyc_i & wb_we_i & ~full);
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assign wb_rd_en = (wb_addr_i == `SPORT_ADDR) && (wb_stb_i & wb_cyc_i & ~wb_we_i);
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endmodule
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: $
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//
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