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[/] [srdydrdy_lib/] [trunk/] [examples/] [bridge/] [rtl/] [control_pipe.v] - Blame information for rev 31

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module control_pipe
  (
   input  [`PM2F_SZ-1:0]  pm2f_data_0,            // To fib_arb of sd_rrmux.v
   input  [`PM2F_SZ-1:0]  pm2f_data_1,            // To fib_arb of sd_rrmux.v
   input  [`PM2F_SZ-1:0]  pm2f_data_2,            // To fib_arb of sd_rrmux.v
   input  [`PM2F_SZ-1:0]  pm2f_data_3,            // To fib_arb of sd_rrmux.v
   /*AUTOINPUT*/
   // Beginning of automatic inputs (from unused autoinst inputs)
   input                clk,                    // To fib_arb of sd_rrmux.v, ...
   input [`NUM_PORTS*`LL_PG_ASZ*2-1:0] drf_page_list,// To lm of llmanager.v
   input [(`NUM_PORTS)-1:0] drf_srdy,           // To lm of llmanager.v
   input [3:0]          f2d_drdy,               // To cq0 of sd_fifo_s.v, ...
   input [`LL_LNP_SZ*4-1:0] lnp_pnp,            // To lm of llmanager.v
   input [(`NUM_PORTS)-1:0] lnp_srdy,           // To lm of llmanager.v
   input [(`NUM_PORTS)-1:0] par_srdy,           // To lm of llmanager.v
   input [(`NUM_PORTS)-1:0] parr_drdy,          // To lm of llmanager.v
   input [`NUM_PORTS-1:0] pm2f_srdy,            // To fib_arb of sd_rrmux.v
   input                reset,                  // To fib_arb of sd_rrmux.v, ...
   input [(`NUM_PORTS)*(`LL_PG_ASZ)-1:0] rlp_rd_page,// To lm of llmanager.v
   input [(`NUM_PORTS)-1:0] rlp_srdy,           // To lm of llmanager.v
   input [(`NUM_PORTS)-1:0] rlpr_drdy,          // To lm of llmanager.v
   // End of automatics
   /*AUTOOUTPUT*/
   // Beginning of automatic outputs (from unused autoinst outputs)
   output [(`NUM_PORTS)-1:0] drf_drdy,          // From lm of llmanager.v
   output [`LL_PG_ASZ-1:0] f2d_data_0,          // From cq0 of sd_fifo_s.v
   output [`LL_PG_ASZ-1:0] f2d_data_1,          // From cq1 of sd_fifo_s.v
   output [`LL_PG_ASZ-1:0] f2d_data_2,          // From cq2 of sd_fifo_s.v
   output [`LL_PG_ASZ-1:0] f2d_data_3,          // From cq3 of sd_fifo_s.v
   output [3:0]         f2d_srdy,               // From cq0 of sd_fifo_s.v, ...
   output [(`NUM_PORTS)-1:0] lnp_drdy,          // From lm of llmanager.v
   output [(`NUM_PORTS)-1:0] par_drdy,          // From lm of llmanager.v
   output [(`LL_PG_ASZ)-1:0] parr_page,         // From lm of llmanager.v
   output [(`NUM_PORTS)-1:0] parr_srdy,         // From lm of llmanager.v
   output [`NUM_PORTS-1:0] pm2f_drdy,           // From fib_arb of sd_rrmux.v
   output [(`NUM_PORTS)-1:0] rlp_drdy,          // From lm of llmanager.v
   output [(`LL_PG_ASZ+1)-1:0] rlpr_data,       // From lm of llmanager.v
   output [(`NUM_PORTS)-1:0] rlpr_srdy         // From lm of llmanager.v
   // End of automatics
   );
 
  /*AUTOWIRE*/
  // Beginning of automatic wires (for undeclared instantiated-module outputs)
  wire [`LL_PG_ASZ-1:0] flo_data;               // From fib_lookup of fib_lookup.v
  wire [3:0]            flo_drdy;               // From cq0 of sd_fifo_s.v, ...
  wire [`NUM_PORTS-1:0] flo_srdy;               // From fib_lookup of fib_lookup.v
  wire [(`LL_PG_ASZ)-1:0] pgmem_rd_addr;        // From lm of llmanager.v
  wire [(`LL_PG_ASZ+1)-1:0] pgmem_rd_data;      // From pglist_mem of behave2p_mem.v
  wire                  pgmem_rd_en;            // From lm of llmanager.v
  wire [(`LL_PG_ASZ)-1:0] pgmem_wr_addr;        // From lm of llmanager.v
  wire [(`LL_PG_ASZ+1)-1:0] pgmem_wr_data;      // From lm of llmanager.v
  wire                  pgmem_wr_en;            // From lm of llmanager.v
  wire [`PM2F_SZ-1:0]   ppi_data;               // From fib_arb of sd_rrmux.v
  wire                  ppi_drdy;               // From fib_lookup of fib_lookup.v
  wire                  ppi_srdy;               // From fib_arb of sd_rrmux.v
  wire [(`LL_PG_ASZ)-1:0] ref_rd_addr;          // From lm of llmanager.v
  wire [(`LL_REFSZ)-1:0] ref_rd_data;           // From ref_mem of behave2p_mem.v
  wire                  ref_rd_en;              // From lm of llmanager.v
  wire [(`LL_PG_ASZ)-1:0] ref_wr_addr;          // From lm of llmanager.v
  wire [(`LL_REFSZ)-1:0] ref_wr_data;           // From lm of llmanager.v
  wire                  ref_wr_en;              // From lm of llmanager.v
  wire [`LL_REFSZ-1:0]  refup_count;            // From fib_lookup of fib_lookup.v
  wire                  refup_drdy;             // From lm of llmanager.v
  wire [`LL_PG_ASZ-1:0] refup_page;             // From fib_lookup of fib_lookup.v
  wire                  refup_srdy;             // From fib_lookup of fib_lookup.v
  // End of automatics
 
/*  sd_rrmux AUTO_TEMPLATE
 (
 .p_grant (),
 .p_data  (ppi_data[`PM2F_SZ-1:0]),
 .c_data  ({pm2f_data_3,pm2f_data_2,pm2f_data_1,pm2f_data_0}),
 .c_srdy  (pm2f_srdy[`NUM_PORTS-1:0]),
 .c_drdy  (pm2f_drdy[`NUM_PORTS-1:0]),
 .c_rearb                           (1'b1),
 .c_\(.*\)   (pm2f_\1[]),
 .p_\(.*\)   (ppi_\1[]),
 );
 */
  sd_rrmux #(
              // Parameters
              .width                    (`PM2F_SZ),
              .inputs                   (`NUM_PORTS),
              .mode                     (0),
              .fast_arb                 (1)) fib_arb
    (/*AUTOINST*/
     // Outputs
     .c_drdy                            (pm2f_drdy[`NUM_PORTS-1:0]), // Templated
     .p_data                            (ppi_data[`PM2F_SZ-1:0]), // Templated
     .p_grant                           (),                      // Templated
     .p_srdy                            (ppi_srdy),              // Templated
     // Inputs
     .clk                               (clk),
     .reset                             (reset),
     .c_data                            ({pm2f_data_3,pm2f_data_2,pm2f_data_1,pm2f_data_0}), // Templated
     .c_srdy                            (pm2f_srdy[`NUM_PORTS-1:0]), // Templated
     .c_rearb                           (1'b1),                  // Templated
     .p_drdy                            (ppi_drdy));              // Templated
 
  fib_lookup fib_lookup
    (/*AUTOINST*/
     // Outputs
     .flo_data                          (flo_data[`LL_PG_ASZ-1:0]),
     .flo_srdy                          (flo_srdy[`NUM_PORTS-1:0]),
     .ppi_drdy                          (ppi_drdy),
     .refup_count                       (refup_count[`LL_REFSZ-1:0]),
     .refup_page                        (refup_page[`LL_PG_ASZ-1:0]),
     .refup_srdy                        (refup_srdy),
     // Inputs
     .clk                               (clk),
     .reset                             (reset),
     .ppi_data                          (ppi_data[`PM2F_SZ-1:0]),
     .flo_drdy                          (flo_drdy[`NUM_PORTS-1:0]),
     .ppi_srdy                          (ppi_srdy),
     .refup_drdy                        (refup_drdy));
 
/* llmanager AUTO_TEMPLATE
 (
  .lnp_pnp                       (lnp_pnp[`LL_LNP_SZ*4-1:0]),
  .drf_page_list              (drf_page_list[`NUM_PORTS*`LL_PG_ASZ*2-1:0]),
  .free_count                 (),
 );
 */
  llmanager #(
              // Parameters
              .lpsz                     (`LL_PG_ASZ),
              .lpdsz                    (`LL_PG_ASZ+1),
              .pages                    (`LL_PAGES),
              .sources                  (`NUM_PORTS),
              .maxref                   (`LL_MAX_REF),
              .refsz                    (`LL_REFSZ),
              .sinks                    (`NUM_PORTS),
              .sksz                     (2)) lm
    (/*AUTOINST*/
     // Outputs
     .par_drdy                          (par_drdy[(`NUM_PORTS)-1:0]),
     .parr_srdy                         (parr_srdy[(`NUM_PORTS)-1:0]),
     .parr_page                         (parr_page[(`LL_PG_ASZ)-1:0]),
     .lnp_drdy                          (lnp_drdy[(`NUM_PORTS)-1:0]),
     .rlp_drdy                          (rlp_drdy[(`NUM_PORTS)-1:0]),
     .rlpr_srdy                         (rlpr_srdy[(`NUM_PORTS)-1:0]),
     .rlpr_data                         (rlpr_data[(`LL_PG_ASZ+1)-1:0]),
     .drf_drdy                          (drf_drdy[(`NUM_PORTS)-1:0]),
     .refup_drdy                        (refup_drdy),
     .pgmem_wr_en                       (pgmem_wr_en),
     .pgmem_wr_addr                     (pgmem_wr_addr[(`LL_PG_ASZ)-1:0]),
     .pgmem_wr_data                     (pgmem_wr_data[(`LL_PG_ASZ+1)-1:0]),
     .pgmem_rd_addr                     (pgmem_rd_addr[(`LL_PG_ASZ)-1:0]),
     .pgmem_rd_en                       (pgmem_rd_en),
     .ref_wr_en                         (ref_wr_en),
     .ref_wr_addr                       (ref_wr_addr[(`LL_PG_ASZ)-1:0]),
     .ref_wr_data                       (ref_wr_data[(`LL_REFSZ)-1:0]),
     .ref_rd_addr                       (ref_rd_addr[(`LL_PG_ASZ)-1:0]),
     .ref_rd_en                         (ref_rd_en),
     .free_count                        (),                      // Templated
     // Inputs
     .clk                               (clk),
     .reset                             (reset),
     .par_srdy                          (par_srdy[(`NUM_PORTS)-1:0]),
     .parr_drdy                         (parr_drdy[(`NUM_PORTS)-1:0]),
     .lnp_srdy                          (lnp_srdy[(`NUM_PORTS)-1:0]),
     .lnp_pnp                           (lnp_pnp[`LL_LNP_SZ*4-1:0]), // Templated
     .rlp_srdy                          (rlp_srdy[(`NUM_PORTS)-1:0]),
     .rlp_rd_page                       (rlp_rd_page[(`NUM_PORTS)*(`LL_PG_ASZ)-1:0]),
     .rlpr_drdy                         (rlpr_drdy[(`NUM_PORTS)-1:0]),
     .drf_srdy                          (drf_srdy[(`NUM_PORTS)-1:0]),
     .drf_page_list                     (drf_page_list[`NUM_PORTS*`LL_PG_ASZ*2-1:0]), // Templated
     .refup_srdy                        (refup_srdy),
     .refup_page                        (refup_page[(`LL_PG_ASZ)-1:0]),
     .refup_count                       (refup_count[(`LL_REFSZ)-1:0]),
     .pgmem_rd_data                     (pgmem_rd_data[(`LL_PG_ASZ+1)-1:0]),
     .ref_rd_data                       (ref_rd_data[(`LL_REFSZ)-1:0]));
 
/* behave2p_mem AUTO_TEMPLATE
 (
 
     .wr_clk         (clk),
     .rd_clk         (clk),
 
     .wr_en          (pgmem_wr_en),
     .d_in           (pgmem_wr_data[]),
     .wr_addr        (pgmem_wr_addr[]),
 
     .rd_en          (pgmem_rd_en),
     .rd_addr        (pgmem_rd_addr[]),
     .d_out          (pgmem_rd_data[]),
 );
 */
  behave2p_mem #(.depth   (`LL_PAGES),
                 .addr_sz (`LL_PG_ASZ),
                 .width   (`LL_PG_ASZ+1)) pglist_mem
    (/*AUTOINST*/
     // Outputs
     .d_out                             (pgmem_rd_data[(`LL_PG_ASZ+1)-1:0]), // Templated
     // Inputs
     .wr_en                             (pgmem_wr_en),           // Templated
     .rd_en                             (pgmem_rd_en),           // Templated
     .wr_clk                            (clk),                   // Templated
     .rd_clk                            (clk),                   // Templated
     .d_in                              (pgmem_wr_data[(`LL_PG_ASZ+1)-1:0]), // Templated
     .rd_addr                           (pgmem_rd_addr[(`LL_PG_ASZ)-1:0]), // Templated
     .wr_addr                           (pgmem_wr_addr[(`LL_PG_ASZ)-1:0])); // Templated
 
/* behave2p_mem AUTO_TEMPLATE
 (
 
     .wr_clk         (clk),
     .rd_clk         (clk),
 
     .wr_en          (ref_wr_en),
     .d_in           (ref_wr_data[]),
     .wr_addr        (ref_wr_addr[]),
 
     .rd_en          (ref_rd_en),
     .rd_addr        (ref_rd_addr[]),
     .d_out          (ref_rd_data[]),
 );
 */
  behave2p_mem #(.depth   (`LL_PAGES),
                 .addr_sz (`LL_PG_ASZ),
                 .width   (`LL_REFSZ)) ref_mem
    (/*AUTOINST*/
     // Outputs
     .d_out                             (ref_rd_data[(`LL_REFSZ)-1:0]), // Templated
     // Inputs
     .wr_en                             (ref_wr_en),             // Templated
     .rd_en                             (ref_rd_en),             // Templated
     .wr_clk                            (clk),                   // Templated
     .rd_clk                            (clk),                   // Templated
     .d_in                              (ref_wr_data[(`LL_REFSZ)-1:0]), // Templated
     .rd_addr                           (ref_rd_addr[(`LL_PG_ASZ)-1:0]), // Templated
     .wr_addr                           (ref_wr_addr[(`LL_PG_ASZ)-1:0])); // Templated
 
/* sd_fifo_s AUTO_TEMPLATE
 (
  .c_clk (clk),
  .c_reset (reset),
  .p_clk (clk),
  .p_reset (reset),
  .c_data     (flo_data[`LL_PG_ASZ-1:0]),
  .c_\(.*\)   (flo_\1[@]),
  .p_\(.*\)   (f2d_\1[@]),
  .p_data     (f2d_data_@[`LL_PG_ASZ-1:0]),
 );
 */
  sd_fifo_s #(.width(`LL_PG_ASZ), .depth(8)) cq0
    (/*AUTOINST*/
     // Outputs
     .c_drdy                            (flo_drdy[0]),           // Templated
     .p_srdy                            (f2d_srdy[0]),           // Templated
     .p_data                            (f2d_data_0[`LL_PG_ASZ-1:0]), // Templated
     // Inputs
     .c_clk                             (clk),                   // Templated
     .c_reset                           (reset),                 // Templated
     .c_srdy                            (flo_srdy[0]),           // Templated
     .c_data                            (flo_data[`LL_PG_ASZ-1:0]), // Templated
     .p_clk                             (clk),                   // Templated
     .p_reset                           (reset),                 // Templated
     .p_drdy                            (f2d_drdy[0]));           // Templated
 
  sd_fifo_s #(.width(`LL_PG_ASZ), .depth(8)) cq1
    (/*AUTOINST*/
     // Outputs
     .c_drdy                            (flo_drdy[1]),           // Templated
     .p_srdy                            (f2d_srdy[1]),           // Templated
     .p_data                            (f2d_data_1[`LL_PG_ASZ-1:0]), // Templated
     // Inputs
     .c_clk                             (clk),                   // Templated
     .c_reset                           (reset),                 // Templated
     .c_srdy                            (flo_srdy[1]),           // Templated
     .c_data                            (flo_data[`LL_PG_ASZ-1:0]), // Templated
     .p_clk                             (clk),                   // Templated
     .p_reset                           (reset),                 // Templated
     .p_drdy                            (f2d_drdy[1]));           // Templated
 
  sd_fifo_s #(.width(`LL_PG_ASZ), .depth(8)) cq2
    (/*AUTOINST*/
     // Outputs
     .c_drdy                            (flo_drdy[2]),           // Templated
     .p_srdy                            (f2d_srdy[2]),           // Templated
     .p_data                            (f2d_data_2[`LL_PG_ASZ-1:0]), // Templated
     // Inputs
     .c_clk                             (clk),                   // Templated
     .c_reset                           (reset),                 // Templated
     .c_srdy                            (flo_srdy[2]),           // Templated
     .c_data                            (flo_data[`LL_PG_ASZ-1:0]), // Templated
     .p_clk                             (clk),                   // Templated
     .p_reset                           (reset),                 // Templated
     .p_drdy                            (f2d_drdy[2]));           // Templated
 
  sd_fifo_s #(.width(`LL_PG_ASZ), .depth(8)) cq3
    (/*AUTOINST*/
     // Outputs
     .c_drdy                            (flo_drdy[3]),           // Templated
     .p_srdy                            (f2d_srdy[3]),           // Templated
     .p_data                            (f2d_data_3[`LL_PG_ASZ-1:0]), // Templated
     // Inputs
     .c_clk                             (clk),                   // Templated
     .c_reset                           (reset),                 // Templated
     .c_srdy                            (flo_srdy[3]),           // Templated
     .c_data                            (flo_data[`LL_PG_ASZ-1:0]), // Templated
     .p_clk                             (clk),                   // Templated
     .p_reset                           (reset),                 // Templated
     .p_drdy                            (f2d_drdy[3]));           // Templated
 
 
endmodule // control_pipe
// Local Variables:
// verilog-library-directories:("." "../../../rtl/verilog/closure" "../../../rtl/verilog/buffers" "../../../rtl/verilog/forks" "../../../rtl/verilog/memory" "../../llmanager")
// End:  

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Subversion Repositories srdydrdy_lib

[/] [srdydrdy_lib/] [trunk/] [examples/] [bridge/] [rtl/] [control_pipe.v] - Blame information for rev 31

Line No.	Rev	Author	Line
1	31	ghutchis	`module control_pipe`
2			`(`
3			input [`PM2F_SZ-1:0] pm2f_data_0, // To fib_arb of sd_rrmux.v
4			input [`PM2F_SZ-1:0] pm2f_data_1, // To fib_arb of sd_rrmux.v
5			input [`PM2F_SZ-1:0] pm2f_data_2, // To fib_arb of sd_rrmux.v
6			input [`PM2F_SZ-1:0] pm2f_data_3, // To fib_arb of sd_rrmux.v
7			`/AUTOINPUT/`
8			`// Beginning of automatic inputs (from unused autoinst inputs)`
9			`input clk, // To fib_arb of sd_rrmux.v, ...`
10			input [`NUM_PORTS`LL_PG_ASZ2-1:0] drf_page_list,// To lm of llmanager.v
11			input [(`NUM_PORTS)-1:0] drf_srdy, // To lm of llmanager.v
12			`input [3:0] f2d_drdy, // To cq0 of sd_fifo_s.v, ...`
13			input [`LL_LNP_SZ*4-1:0] lnp_pnp, // To lm of llmanager.v
14			input [(`NUM_PORTS)-1:0] lnp_srdy, // To lm of llmanager.v
15			input [(`NUM_PORTS)-1:0] par_srdy, // To lm of llmanager.v
16			input [(`NUM_PORTS)-1:0] parr_drdy, // To lm of llmanager.v
17			input [`NUM_PORTS-1:0] pm2f_srdy, // To fib_arb of sd_rrmux.v
18			`input reset, // To fib_arb of sd_rrmux.v, ...`
19			input [(`NUM_PORTS)*(`LL_PG_ASZ)-1:0] rlp_rd_page,// To lm of llmanager.v
20			input [(`NUM_PORTS)-1:0] rlp_srdy, // To lm of llmanager.v
21			input [(`NUM_PORTS)-1:0] rlpr_drdy, // To lm of llmanager.v
22			`// End of automatics`
23			`/AUTOOUTPUT/`
24			`// Beginning of automatic outputs (from unused autoinst outputs)`
25			output [(`NUM_PORTS)-1:0] drf_drdy, // From lm of llmanager.v
26			output [`LL_PG_ASZ-1:0] f2d_data_0, // From cq0 of sd_fifo_s.v
27			output [`LL_PG_ASZ-1:0] f2d_data_1, // From cq1 of sd_fifo_s.v
28			output [`LL_PG_ASZ-1:0] f2d_data_2, // From cq2 of sd_fifo_s.v
29			output [`LL_PG_ASZ-1:0] f2d_data_3, // From cq3 of sd_fifo_s.v
30			`output [3:0] f2d_srdy, // From cq0 of sd_fifo_s.v, ...`
31			output [(`NUM_PORTS)-1:0] lnp_drdy, // From lm of llmanager.v
32			output [(`NUM_PORTS)-1:0] par_drdy, // From lm of llmanager.v
33			output [(`LL_PG_ASZ)-1:0] parr_page, // From lm of llmanager.v
34			output [(`NUM_PORTS)-1:0] parr_srdy, // From lm of llmanager.v
35			output [`NUM_PORTS-1:0] pm2f_drdy, // From fib_arb of sd_rrmux.v
36			output [(`NUM_PORTS)-1:0] rlp_drdy, // From lm of llmanager.v
37			output [(`LL_PG_ASZ+1)-1:0] rlpr_data, // From lm of llmanager.v
38			output [(`NUM_PORTS)-1:0] rlpr_srdy // From lm of llmanager.v
39			`// End of automatics`
40			`);`
41
42			`/AUTOWIRE/`
43			`// Beginning of automatic wires (for undeclared instantiated-module outputs)`
44			wire [`LL_PG_ASZ-1:0] flo_data; // From fib_lookup of fib_lookup.v
45			`wire [3:0] flo_drdy; // From cq0 of sd_fifo_s.v, ...`
46			wire [`NUM_PORTS-1:0] flo_srdy; // From fib_lookup of fib_lookup.v
47			wire [(`LL_PG_ASZ)-1:0] pgmem_rd_addr; // From lm of llmanager.v
48			wire [(`LL_PG_ASZ+1)-1:0] pgmem_rd_data; // From pglist_mem of behave2p_mem.v
49			`wire pgmem_rd_en; // From lm of llmanager.v`
50			wire [(`LL_PG_ASZ)-1:0] pgmem_wr_addr; // From lm of llmanager.v
51			wire [(`LL_PG_ASZ+1)-1:0] pgmem_wr_data; // From lm of llmanager.v
52			`wire pgmem_wr_en; // From lm of llmanager.v`
53			wire [`PM2F_SZ-1:0] ppi_data; // From fib_arb of sd_rrmux.v
54			`wire ppi_drdy; // From fib_lookup of fib_lookup.v`
55			`wire ppi_srdy; // From fib_arb of sd_rrmux.v`
56			wire [(`LL_PG_ASZ)-1:0] ref_rd_addr; // From lm of llmanager.v
57			wire [(`LL_REFSZ)-1:0] ref_rd_data; // From ref_mem of behave2p_mem.v
58			`wire ref_rd_en; // From lm of llmanager.v`
59			wire [(`LL_PG_ASZ)-1:0] ref_wr_addr; // From lm of llmanager.v
60			wire [(`LL_REFSZ)-1:0] ref_wr_data; // From lm of llmanager.v
61			`wire ref_wr_en; // From lm of llmanager.v`
62			wire [`LL_REFSZ-1:0] refup_count; // From fib_lookup of fib_lookup.v
63			`wire refup_drdy; // From lm of llmanager.v`
64			wire [`LL_PG_ASZ-1:0] refup_page; // From fib_lookup of fib_lookup.v
65			`wire refup_srdy; // From fib_lookup of fib_lookup.v`
66			`// End of automatics`
67
68			`/* sd_rrmux AUTO_TEMPLATE`
69			`(`
70			`.p_grant (),`
71			.p_data (ppi_data[`PM2F_SZ-1:0]),
72			`.c_data ({pm2f_data_3,pm2f_data_2,pm2f_data_1,pm2f_data_0}),`
73			.c_srdy (pm2f_srdy[`NUM_PORTS-1:0]),
74			.c_drdy (pm2f_drdy[`NUM_PORTS-1:0]),
75			`.c_rearb (1'b1),`
76			`.c_\(.*\) (pm2f_\1[]),`
77			`.p_\(.*\) (ppi_\1[]),`
78			`);`
79			`*/`
80			`sd_rrmux #(`
81			`// Parameters`
82			.width (`PM2F_SZ),
83			.inputs (`NUM_PORTS),
84			`.mode (0),`
85			`.fast_arb (1)) fib_arb`
86			`(/AUTOINST/`
87			`// Outputs`
88			.c_drdy (pm2f_drdy[`NUM_PORTS-1:0]), // Templated
89			.p_data (ppi_data[`PM2F_SZ-1:0]), // Templated
90			`.p_grant (), // Templated`
91			`.p_srdy (ppi_srdy), // Templated`
92			`// Inputs`
93			`.clk (clk),`
94			`.reset (reset),`
95			`.c_data ({pm2f_data_3,pm2f_data_2,pm2f_data_1,pm2f_data_0}), // Templated`
96			.c_srdy (pm2f_srdy[`NUM_PORTS-1:0]), // Templated
97			`.c_rearb (1'b1), // Templated`
98			`.p_drdy (ppi_drdy)); // Templated`
99
100			`fib_lookup fib_lookup`
101			`(/AUTOINST/`
102			`// Outputs`
103			.flo_data (flo_data[`LL_PG_ASZ-1:0]),
104			.flo_srdy (flo_srdy[`NUM_PORTS-1:0]),
105			`.ppi_drdy (ppi_drdy),`
106			.refup_count (refup_count[`LL_REFSZ-1:0]),
107			.refup_page (refup_page[`LL_PG_ASZ-1:0]),
108			`.refup_srdy (refup_srdy),`
109			`// Inputs`
110			`.clk (clk),`
111			`.reset (reset),`
112			.ppi_data (ppi_data[`PM2F_SZ-1:0]),
113			.flo_drdy (flo_drdy[`NUM_PORTS-1:0]),
114			`.ppi_srdy (ppi_srdy),`
115			`.refup_drdy (refup_drdy));`
116
117			`/* llmanager AUTO_TEMPLATE`
118			`(`
119			.lnp_pnp (lnp_pnp[`LL_LNP_SZ*4-1:0]),
120			.drf_page_list (drf_page_list[`NUM_PORTS`LL_PG_ASZ2-1:0]),
121			`.free_count (),`
122			`);`
123			`*/`
124			`llmanager #(`
125			`// Parameters`
126			.lpsz (`LL_PG_ASZ),
127			.lpdsz (`LL_PG_ASZ+1),
128			.pages (`LL_PAGES),
129			.sources (`NUM_PORTS),
130			.maxref (`LL_MAX_REF),
131			.refsz (`LL_REFSZ),
132			.sinks (`NUM_PORTS),
133			`.sksz (2)) lm`
134			`(/AUTOINST/`
135			`// Outputs`
136			.par_drdy (par_drdy[(`NUM_PORTS)-1:0]),
137			.parr_srdy (parr_srdy[(`NUM_PORTS)-1:0]),
138			.parr_page (parr_page[(`LL_PG_ASZ)-1:0]),
139			.lnp_drdy (lnp_drdy[(`NUM_PORTS)-1:0]),
140			.rlp_drdy (rlp_drdy[(`NUM_PORTS)-1:0]),
141			.rlpr_srdy (rlpr_srdy[(`NUM_PORTS)-1:0]),
142			.rlpr_data (rlpr_data[(`LL_PG_ASZ+1)-1:0]),
143			.drf_drdy (drf_drdy[(`NUM_PORTS)-1:0]),
144			`.refup_drdy (refup_drdy),`
145			`.pgmem_wr_en (pgmem_wr_en),`
146			.pgmem_wr_addr (pgmem_wr_addr[(`LL_PG_ASZ)-1:0]),
147			.pgmem_wr_data (pgmem_wr_data[(`LL_PG_ASZ+1)-1:0]),
148			.pgmem_rd_addr (pgmem_rd_addr[(`LL_PG_ASZ)-1:0]),
149			`.pgmem_rd_en (pgmem_rd_en),`
150			`.ref_wr_en (ref_wr_en),`
151			.ref_wr_addr (ref_wr_addr[(`LL_PG_ASZ)-1:0]),
152			.ref_wr_data (ref_wr_data[(`LL_REFSZ)-1:0]),
153			.ref_rd_addr (ref_rd_addr[(`LL_PG_ASZ)-1:0]),
154			`.ref_rd_en (ref_rd_en),`
155			`.free_count (), // Templated`
156			`// Inputs`
157			`.clk (clk),`
158			`.reset (reset),`
159			.par_srdy (par_srdy[(`NUM_PORTS)-1:0]),
160			.parr_drdy (parr_drdy[(`NUM_PORTS)-1:0]),
161			.lnp_srdy (lnp_srdy[(`NUM_PORTS)-1:0]),
162			.lnp_pnp (lnp_pnp[`LL_LNP_SZ*4-1:0]), // Templated
163			.rlp_srdy (rlp_srdy[(`NUM_PORTS)-1:0]),
164			.rlp_rd_page (rlp_rd_page[(`NUM_PORTS)*(`LL_PG_ASZ)-1:0]),
165			.rlpr_drdy (rlpr_drdy[(`NUM_PORTS)-1:0]),
166			.drf_srdy (drf_srdy[(`NUM_PORTS)-1:0]),
167			.drf_page_list (drf_page_list[`NUM_PORTS`LL_PG_ASZ2-1:0]), // Templated
168			`.refup_srdy (refup_srdy),`
169			.refup_page (refup_page[(`LL_PG_ASZ)-1:0]),
170			.refup_count (refup_count[(`LL_REFSZ)-1:0]),
171			.pgmem_rd_data (pgmem_rd_data[(`LL_PG_ASZ+1)-1:0]),
172			.ref_rd_data (ref_rd_data[(`LL_REFSZ)-1:0]));
173
174			`/* behave2p_mem AUTO_TEMPLATE`
175			`(`
176
177			`.wr_clk (clk),`
178			`.rd_clk (clk),`
179
180			`.wr_en (pgmem_wr_en),`
181			`.d_in (pgmem_wr_data[]),`
182			`.wr_addr (pgmem_wr_addr[]),`
183
184			`.rd_en (pgmem_rd_en),`
185			`.rd_addr (pgmem_rd_addr[]),`
186			`.d_out (pgmem_rd_data[]),`
187			`);`
188			`*/`
189			behave2p_mem #(.depth (`LL_PAGES),
190			.addr_sz (`LL_PG_ASZ),
191			.width (`LL_PG_ASZ+1)) pglist_mem
192			`(/AUTOINST/`
193			`// Outputs`
194			.d_out (pgmem_rd_data[(`LL_PG_ASZ+1)-1:0]), // Templated
195			`// Inputs`
196			`.wr_en (pgmem_wr_en), // Templated`
197			`.rd_en (pgmem_rd_en), // Templated`
198			`.wr_clk (clk), // Templated`
199			`.rd_clk (clk), // Templated`
200			.d_in (pgmem_wr_data[(`LL_PG_ASZ+1)-1:0]), // Templated
201			.rd_addr (pgmem_rd_addr[(`LL_PG_ASZ)-1:0]), // Templated
202			.wr_addr (pgmem_wr_addr[(`LL_PG_ASZ)-1:0])); // Templated
203
204			`/* behave2p_mem AUTO_TEMPLATE`
205			`(`
206
207			`.wr_clk (clk),`
208			`.rd_clk (clk),`
209
210			`.wr_en (ref_wr_en),`
211			`.d_in (ref_wr_data[]),`
212			`.wr_addr (ref_wr_addr[]),`
213
214			`.rd_en (ref_rd_en),`
215			`.rd_addr (ref_rd_addr[]),`
216			`.d_out (ref_rd_data[]),`
217			`);`
218			`*/`
219			behave2p_mem #(.depth (`LL_PAGES),
220			.addr_sz (`LL_PG_ASZ),
221			.width (`LL_REFSZ)) ref_mem
222			`(/AUTOINST/`
223			`// Outputs`
224			.d_out (ref_rd_data[(`LL_REFSZ)-1:0]), // Templated
225			`// Inputs`
226			`.wr_en (ref_wr_en), // Templated`
227			`.rd_en (ref_rd_en), // Templated`
228			`.wr_clk (clk), // Templated`
229			`.rd_clk (clk), // Templated`
230			.d_in (ref_wr_data[(`LL_REFSZ)-1:0]), // Templated
231			.rd_addr (ref_rd_addr[(`LL_PG_ASZ)-1:0]), // Templated
232			.wr_addr (ref_wr_addr[(`LL_PG_ASZ)-1:0])); // Templated
233
234			`/* sd_fifo_s AUTO_TEMPLATE`
235			`(`
236			`.c_clk (clk),`
237			`.c_reset (reset),`
238			`.p_clk (clk),`
239			`.p_reset (reset),`
240			.c_data (flo_data[`LL_PG_ASZ-1:0]),
241			`.c_\(.*\) (flo_\1[@]),`
242			`.p_\(.*\) (f2d_\1[@]),`
243			.p_data (f2d_data_@[`LL_PG_ASZ-1:0]),
244			`);`
245			`*/`
246			sd_fifo_s #(.width(`LL_PG_ASZ), .depth(8)) cq0
247			`(/AUTOINST/`
248			`// Outputs`
249			`.c_drdy (flo_drdy[0]), // Templated`
250			`.p_srdy (f2d_srdy[0]), // Templated`
251			.p_data (f2d_data_0[`LL_PG_ASZ-1:0]), // Templated
252			`// Inputs`
253			`.c_clk (clk), // Templated`
254			`.c_reset (reset), // Templated`
255			`.c_srdy (flo_srdy[0]), // Templated`
256			.c_data (flo_data[`LL_PG_ASZ-1:0]), // Templated
257			`.p_clk (clk), // Templated`
258			`.p_reset (reset), // Templated`
259			`.p_drdy (f2d_drdy[0])); // Templated`
260
261			sd_fifo_s #(.width(`LL_PG_ASZ), .depth(8)) cq1
262			`(/AUTOINST/`
263			`// Outputs`
264			`.c_drdy (flo_drdy[1]), // Templated`
265			`.p_srdy (f2d_srdy[1]), // Templated`
266			.p_data (f2d_data_1[`LL_PG_ASZ-1:0]), // Templated
267			`// Inputs`
268			`.c_clk (clk), // Templated`
269			`.c_reset (reset), // Templated`
270			`.c_srdy (flo_srdy[1]), // Templated`
271			.c_data (flo_data[`LL_PG_ASZ-1:0]), // Templated
272			`.p_clk (clk), // Templated`
273			`.p_reset (reset), // Templated`
274			`.p_drdy (f2d_drdy[1])); // Templated`
275
276			sd_fifo_s #(.width(`LL_PG_ASZ), .depth(8)) cq2
277			`(/AUTOINST/`
278			`// Outputs`
279			`.c_drdy (flo_drdy[2]), // Templated`
280			`.p_srdy (f2d_srdy[2]), // Templated`
281			.p_data (f2d_data_2[`LL_PG_ASZ-1:0]), // Templated
282			`// Inputs`
283			`.c_clk (clk), // Templated`
284			`.c_reset (reset), // Templated`
285			`.c_srdy (flo_srdy[2]), // Templated`
286			.c_data (flo_data[`LL_PG_ASZ-1:0]), // Templated
287			`.p_clk (clk), // Templated`
288			`.p_reset (reset), // Templated`
289			`.p_drdy (f2d_drdy[2])); // Templated`
290
291			sd_fifo_s #(.width(`LL_PG_ASZ), .depth(8)) cq3
292			`(/AUTOINST/`
293			`// Outputs`
294			`.c_drdy (flo_drdy[3]), // Templated`
295			`.p_srdy (f2d_srdy[3]), // Templated`
296			.p_data (f2d_data_3[`LL_PG_ASZ-1:0]), // Templated
297			`// Inputs`
298			`.c_clk (clk), // Templated`
299			`.c_reset (reset), // Templated`
300			`.c_srdy (flo_srdy[3]), // Templated`
301			.c_data (flo_data[`LL_PG_ASZ-1:0]), // Templated
302			`.p_clk (clk), // Templated`
303			`.p_reset (reset), // Templated`
304			`.p_drdy (f2d_drdy[3])); // Templated`
305
306
307			`endmodule // control_pipe`
308			`// Local Variables:`
309			`// verilog-library-directories:("." "../../../rtl/verilog/closure" "../../../rtl/verilog/buffers" "../../../rtl/verilog/forks" "../../../rtl/verilog/memory" "../../llmanager")`
310			`// End:`