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[/] [srdydrdy_lib/] [trunk/] [examples/] [bridge/] [rtl/] [port_macro.v] - Blame information for rev 31

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module port_macro
  #(parameter port_num = 0,
    parameter lpsz = 12,
    parameter lpdsz = 13)
  (input         clk,
   input         reset,
 
   /*AUTOINPUT*/
   // Beginning of automatic inputs (from unused autoinst inputs)
   input                drf_drdy,               // To dealloc of deallocator.v
   input [`LL_PG_ASZ-1:0] f2d_data,             // To dealloc of deallocator.v
   input                f2d_srdy,               // To dealloc of deallocator.v
   input                gmii_rx_clk,            // To port_clocking of port_clocking.v, ...
   input                gmii_rx_dv,             // To rx_gigmac of sd_rx_gigmac.v
   input [7:0]          gmii_rxd,               // To rx_gigmac of sd_rx_gigmac.v
   input                lnp_drdy,               // To alloc of allocator.v
   input                par_drdy,               // To alloc of allocator.v
   input [`LL_PG_ASZ-1:0] parr_page,            // To alloc of allocator.v
   input                parr_srdy,              // To alloc of allocator.v
   input                pbra_drdy,              // To alloc of allocator.v
   input                pbrd_drdy,              // To dealloc of deallocator.v
   input [`PFW_SZ-1:0]  pbrr_data,              // To dealloc of deallocator.v
   input                pbrr_srdy,              // To dealloc of deallocator.v
   input                pm2f_drdy,              // To pm2f_join of sd_ajoin2.v
   input                rlp_drdy,               // To dealloc of deallocator.v
   input [`LL_PG_ASZ:0] rlpr_data,              // To dealloc of deallocator.v
   input                rlpr_srdy,              // To dealloc of deallocator.v
   // End of automatics
   /*AUTOOUTPUT*/
   // Beginning of automatic outputs (from unused autoinst outputs)
   output [`LL_PG_ASZ*2-1:0] drf_page_list,     // From dealloc of deallocator.v
   output               drf_srdy,               // From dealloc of deallocator.v
   output               f2d_drdy,               // From dealloc of deallocator.v
   output               gmii_tx_en,             // From tx_gmii of sd_tx_gigmac.v
   output [7:0]         gmii_txd,               // From tx_gmii of sd_tx_gigmac.v
   output [`LL_LNP_SZ-1:0] lnp_pnp,             // From alloc of allocator.v
   output               lnp_srdy,               // From alloc of allocator.v
   output               par_srdy,               // From alloc of allocator.v
   output               parr_drdy,              // From alloc of allocator.v
   output [`PBR_SZ-1:0] pbra_data,              // From alloc of allocator.v
   output               pbra_srdy,              // From alloc of allocator.v
   output [`PBR_SZ-1:0] pbrd_data,              // From dealloc of deallocator.v
   output               pbrd_srdy,              // From dealloc of deallocator.v
   output               pbrr_drdy,              // From dealloc of deallocator.v
   output [(`PAR_DATA_SZ)+(`LL_PG_ASZ*2)-1:0] pm2f_data,// From pm2f_join of sd_ajoin2.v
   output               pm2f_srdy,              // From pm2f_join of sd_ajoin2.v
   output [`LL_PG_ASZ-1:0] rlp_rd_page,         // From dealloc of deallocator.v
   output               rlp_srdy,               // From dealloc of deallocator.v
   output               rlpr_drdy              // From dealloc of deallocator.v
   // End of automatics
   );
 
  wire [`RX_USG_SZ-1:0] rx_usage;
  wire [`TX_USG_SZ-1:0] tx_usage;
  wire [`PFW_SZ-1:0]     prx_data;               // From fifo_rx of sd_fifo_b.v
  wire [`PFW_SZ-1:0]     ptx_data;               // From fifo_tx of sd_fifo_b.v
  wire [`PFW_SZ-1:0]     rttx_data;              // From ring_tap of port_ring_tap.v
  wire [1:0]             rxg_code;               // From rx_sync_fifo of sd_fifo_s.v
  wire [7:0]             rxg_data;               // From rx_sync_fifo of sd_fifo_s.v
  wire [`PFW_SZ-1:0]     ctx_data;               // From oflow of egr_oflow.v
  /*AUTOWIRE*/
  // Beginning of automatic wires (for undeclared instantiated-module outputs)
  wire                  a2f_drdy;               // From pm2f_join of sd_ajoin2.v
  wire [`LL_PG_ASZ-1:0] a2f_end;                // From alloc of allocator.v
  wire                  a2f_srdy;               // From alloc of allocator.v
  wire [`LL_PG_ASZ-1:0] a2f_start;              // From alloc of allocator.v
  wire                  crx_abort;              // From con of concentrator.v
  wire                  crx_commit;             // From con of concentrator.v
  wire [`PFW_SZ-1:0]    crx_data;               // From con of concentrator.v
  wire                  crx_drdy;               // From alloc of allocator.v
  wire                  crx_srdy;               // From con of concentrator.v
  wire                  gmii_rx_reset;          // From port_clocking of port_clocking.v
  wire [`PAR_DATA_SZ-1:0] p2f_data;             // From pkt_parse of pkt_parse.v
  wire                  p2f_drdy;               // From pm2f_join of sd_ajoin2.v
  wire                  p2f_srdy;               // From pkt_parse of pkt_parse.v
  wire [1:0]            pdo_code;               // From pkt_parse of pkt_parse.v
  wire [7:0]            pdo_data;               // From pkt_parse of pkt_parse.v
  wire                  pdo_drdy;               // From con of concentrator.v
  wire                  pdo_srdy;               // From pkt_parse of pkt_parse.v
  wire                  ptx_drdy;               // From dst of distributor.v
  wire                  ptx_srdy;               // From dealloc of deallocator.v
  wire [1:0]            rxc_rxg_code;           // From rx_gigmac of sd_rx_gigmac.v
  wire [7:0]            rxc_rxg_data;           // From rx_gigmac of sd_rx_gigmac.v
  wire                  rxc_rxg_drdy;           // From rx_sync_fifo of sd_fifo_s.v
  wire                  rxc_rxg_srdy;           // From rx_gigmac of sd_rx_gigmac.v
  wire                  rxg_drdy;               // From pkt_parse of pkt_parse.v
  wire                  rxg_srdy;               // From rx_sync_fifo of sd_fifo_s.v
  wire [1:0]            txg_code;               // From dst of distributor.v
  wire [7:0]            txg_data;               // From dst of distributor.v
  wire                  txg_drdy;               // From tx_gmii of sd_tx_gigmac.v
  wire                  txg_srdy;               // From dst of distributor.v
  // End of automatics
 
 
  port_clocking port_clocking
    (/*AUTOINST*/
     // Outputs
     .gmii_rx_reset                     (gmii_rx_reset),
     // Inputs
     .clk                               (clk),
     .reset                             (reset),
     .gmii_rx_clk                       (gmii_rx_clk));
 
/*  sd_rx_gigmac AUTO_TEMPLATE
 (
   .clk                         (gmii_rx_clk),
   .reset                       (gmii_rx_reset),
   .rxg_\(.*\)                  (rxc_rxg_\1[]),
 );
 */
  sd_rx_gigmac rx_gigmac
    (
     .cfg_check_crc (1'b0),
     /*AUTOINST*/
     // Outputs
     .rxg_srdy                          (rxc_rxg_srdy),          // Templated
     .rxg_code                          (rxc_rxg_code[1:0]),     // Templated
     .rxg_data                          (rxc_rxg_data[7:0]),     // Templated
     // Inputs
     .clk                               (gmii_rx_clk),           // Templated
     .reset                             (gmii_rx_reset),         // Templated
     .gmii_rx_dv                        (gmii_rx_dv),
     .gmii_rxd                          (gmii_rxd[7:0]),
     .rxg_drdy                          (rxc_rxg_drdy));          // Templated
 
/* sd_fifo_s AUTO_TEMPLATE
 (
     .c_clk                             (gmii_rx_clk),
     .c_reset                           (gmii_rx_reset),
     .c_data                            ({rxc_rxg_code,rxc_rxg_data}),
     .p_data                            ({rxg_code,rxg_data}),
     .p_clk                             (clk),
     .p_reset                           (reset),
  .c_\(.*\)                     (rxc_rxg_\1[]),
  .p_\(.*\)                     (rxg_\1[]),
 );
 */
  sd_fifo_s #(8+2,16,1) rx_sync_fifo
    (/*AUTOINST*/
     // Outputs
     .c_drdy                            (rxc_rxg_drdy),          // Templated
     .p_srdy                            (rxg_srdy),              // Templated
     .p_data                            ({rxg_code,rxg_data}),   // Templated
     // Inputs
     .c_clk                             (gmii_rx_clk),           // Templated
     .c_reset                           (gmii_rx_reset),         // Templated
     .c_srdy                            (rxc_rxg_srdy),          // Templated
     .c_data                            ({rxc_rxg_code,rxc_rxg_data}), // Templated
     .p_clk                             (clk),                   // Templated
     .p_reset                           (reset),                 // Templated
     .p_drdy                            (rxg_drdy));              // Templated
 
  pkt_parse #(port_num) pkt_parse
    (
     /*AUTOINST*/
     // Outputs
     .rxg_drdy                          (rxg_drdy),
     .p2f_srdy                          (p2f_srdy),
     .p2f_data                          (p2f_data[`PAR_DATA_SZ-1:0]),
     .pdo_srdy                          (pdo_srdy),
     .pdo_code                          (pdo_code[1:0]),
     .pdo_data                          (pdo_data[7:0]),
     // Inputs
     .clk                               (clk),
     .reset                             (reset),
     .rxg_srdy                          (rxg_srdy),
     .rxg_code                          (rxg_code[1:0]),
     .rxg_data                          (rxg_data[7:0]),
     .p2f_drdy                          (p2f_drdy),
     .pdo_drdy                          (pdo_drdy));
 
/* concentrator AUTO_TEMPLATE
 (
    .c_\(.*\)     (pdo_\1[]),
    .p_\(.*\)     (crx_\1[]),
 );
 */
  concentrator con
    (/*AUTOINST*/
     // Outputs
     .c_drdy                            (pdo_drdy),              // Templated
     .p_data                            (crx_data[`PFW_SZ-1:0]), // Templated
     .p_srdy                            (crx_srdy),              // Templated
     .p_commit                          (crx_commit),            // Templated
     .p_abort                           (crx_abort),             // Templated
     // Inputs
     .clk                               (clk),
     .reset                             (reset),
     .c_data                            (pdo_data[7:0]),         // Templated
     .c_code                            (pdo_code[1:0]),         // Templated
     .c_srdy                            (pdo_srdy),              // Templated
     .p_drdy                            (crx_drdy));              // Templated
 
/* allocator AUTO_TEMPLATE
 (
 );
 */
  allocator alloc
    (/*AUTOINST*/
     // Outputs
     .crx_drdy                          (crx_drdy),
     .par_srdy                          (par_srdy),
     .parr_drdy                         (parr_drdy),
     .lnp_srdy                          (lnp_srdy),
     .lnp_pnp                           (lnp_pnp[`LL_LNP_SZ-1:0]),
     .pbra_data                         (pbra_data[`PBR_SZ-1:0]),
     .pbra_srdy                         (pbra_srdy),
     .a2f_start                         (a2f_start[`LL_PG_ASZ-1:0]),
     .a2f_end                           (a2f_end[`LL_PG_ASZ-1:0]),
     .a2f_srdy                          (a2f_srdy),
     // Inputs
     .clk                               (clk),
     .reset                             (reset),
     .crx_abort                         (crx_abort),
     .crx_commit                        (crx_commit),
     .crx_data                          (crx_data[`PFW_SZ-1:0]),
     .crx_srdy                          (crx_srdy),
     .par_drdy                          (par_drdy),
     .parr_srdy                         (parr_srdy),
     .parr_page                         (parr_page[`LL_PG_ASZ-1:0]),
     .lnp_drdy                          (lnp_drdy),
     .pbra_drdy                         (pbra_drdy),
     .a2f_drdy                          (a2f_drdy));
 
/* sd_ajoin2 AUTO_TEMPLATE
 (
   .c2_data                     ({a2f_end,a2f_start}),
   .c1_\(.*\)                   (p2f_\1[]),
   .c2_\(.*\)                   (a2f_\1[]),
   .p_\(.*\)                    (pm2f_\1[]),
 );
 */
  sd_ajoin2 #(.c1_width(`PAR_DATA_SZ), .c2_width(`LL_PG_ASZ*2)) pm2f_join
    (/*AUTOINST*/
     // Outputs
     .c1_drdy                           (p2f_drdy),              // Templated
     .c2_drdy                           (a2f_drdy),              // Templated
     .p_srdy                            (pm2f_srdy),             // Templated
     .p_data                            (pm2f_data[(`PAR_DATA_SZ)+(`LL_PG_ASZ*2)-1:0]), // Templated
     // Inputs
     .clk                               (clk),
     .reset                             (reset),
     .c1_srdy                           (p2f_srdy),              // Templated
     .c1_data                           (p2f_data[(`PAR_DATA_SZ)-1:0]), // Templated
     .c2_srdy                           (a2f_srdy),              // Templated
     .c2_data                           ({a2f_end,a2f_start}),   // Templated
     .p_drdy                            (pm2f_drdy));             // Templated
 
  deallocator dealloc
    (/*AUTOINST*/
     // Outputs
     .f2d_drdy                          (f2d_drdy),
     .rlp_srdy                          (rlp_srdy),
     .rlp_rd_page                       (rlp_rd_page[`LL_PG_ASZ-1:0]),
     .rlpr_drdy                         (rlpr_drdy),
     .drf_srdy                          (drf_srdy),
     .drf_page_list                     (drf_page_list[`LL_PG_ASZ*2-1:0]),
     .pbrd_data                         (pbrd_data[`PBR_SZ-1:0]),
     .pbrd_srdy                         (pbrd_srdy),
     .pbrr_drdy                         (pbrr_drdy),
     .ptx_srdy                          (ptx_srdy),
     .ptx_data                          (ptx_data[`PFW_SZ-1:0]),
     // Inputs
     .clk                               (clk),
     .reset                             (reset),
     .port_num                          (port_num[1:0]),
     .f2d_srdy                          (f2d_srdy),
     .f2d_data                          (f2d_data[`LL_PG_ASZ-1:0]),
     .rlp_drdy                          (rlp_drdy),
     .rlpr_srdy                         (rlpr_srdy),
     .rlpr_data                         (rlpr_data[`LL_PG_ASZ:0]),
     .drf_drdy                          (drf_drdy),
     .pbrd_drdy                         (pbrd_drdy),
     .pbrr_srdy                         (pbrr_srdy),
     .pbrr_data                         (pbrr_data[`PFW_SZ-1:0]),
     .ptx_drdy                          (ptx_drdy));
 
/* distributor AUTO_TEMPLATE
 (
    .p_\(.*\)    (txg_\1[]),
 );
 */
  distributor dst
    (/*AUTOINST*/
     // Outputs
     .ptx_drdy                          (ptx_drdy),
     .p_srdy                            (txg_srdy),              // Templated
     .p_code                            (txg_code[1:0]),         // Templated
     .p_data                            (txg_data[7:0]),         // Templated
     // Inputs
     .clk                               (clk),
     .reset                             (reset),
     .ptx_srdy                          (ptx_srdy),
     .ptx_data                          (ptx_data[`PFW_SZ-1:0]),
     .p_drdy                            (txg_drdy));              // Templated
 
  sd_tx_gigmac tx_gmii
    (/*AUTOINST*/
     // Outputs
     .gmii_tx_en                        (gmii_tx_en),
     .gmii_txd                          (gmii_txd[7:0]),
     .txg_drdy                          (txg_drdy),
     // Inputs
     .clk                               (clk),
     .reset                             (reset),
     .txg_srdy                          (txg_srdy),
     .txg_code                          (txg_code[1:0]),
     .txg_data                          (txg_data[7:0]));
 
endmodule // port_macro
// Local Variables:
// verilog-library-directories:("." "../../../rtl/verilog/closure" "../../../rtl/verilog/buffers" "../../../rtl/verilog/forks")
// End:  

Line No.	Rev	Author	Line
1	8	ghutchis	`module port_macro`
2	31	ghutchis	`#(parameter port_num = 0,`
3			`parameter lpsz = 12,`
4			`parameter lpdsz = 13)`
5	8	ghutchis	`(input clk,`
6			`input reset,`
7
8			`/AUTOINPUT/`
9			`// Beginning of automatic inputs (from unused autoinst inputs)`
10	31	ghutchis	`input drf_drdy, // To dealloc of deallocator.v`
11			input [`LL_PG_ASZ-1:0] f2d_data, // To dealloc of deallocator.v
12			`input f2d_srdy, // To dealloc of deallocator.v`
13			`input gmii_rx_clk, // To port_clocking of port_clocking.v, ...`
14			`input gmii_rx_dv, // To rx_gigmac of sd_rx_gigmac.v`
15			`input [7:0] gmii_rxd, // To rx_gigmac of sd_rx_gigmac.v`
16			`input lnp_drdy, // To alloc of allocator.v`
17			`input par_drdy, // To alloc of allocator.v`
18			input [`LL_PG_ASZ-1:0] parr_page, // To alloc of allocator.v
19			`input parr_srdy, // To alloc of allocator.v`
20			`input pbra_drdy, // To alloc of allocator.v`
21			`input pbrd_drdy, // To dealloc of deallocator.v`
22			input [`PFW_SZ-1:0] pbrr_data, // To dealloc of deallocator.v
23			`input pbrr_srdy, // To dealloc of deallocator.v`
24			`input pm2f_drdy, // To pm2f_join of sd_ajoin2.v`
25			`input rlp_drdy, // To dealloc of deallocator.v`
26			input [`LL_PG_ASZ:0] rlpr_data, // To dealloc of deallocator.v
27			`input rlpr_srdy, // To dealloc of deallocator.v`
28	8	ghutchis	`// End of automatics`
29	31	ghutchis	`/AUTOOUTPUT/`
30			`// Beginning of automatic outputs (from unused autoinst outputs)`
31			output [`LL_PG_ASZ*2-1:0] drf_page_list, // From dealloc of deallocator.v
32			`output drf_srdy, // From dealloc of deallocator.v`
33			`output f2d_drdy, // From dealloc of deallocator.v`
34			`output gmii_tx_en, // From tx_gmii of sd_tx_gigmac.v`
35			`output [7:0] gmii_txd, // From tx_gmii of sd_tx_gigmac.v`
36			output [`LL_LNP_SZ-1:0] lnp_pnp, // From alloc of allocator.v
37			`output lnp_srdy, // From alloc of allocator.v`
38			`output par_srdy, // From alloc of allocator.v`
39			`output parr_drdy, // From alloc of allocator.v`
40			output [`PBR_SZ-1:0] pbra_data, // From alloc of allocator.v
41			`output pbra_srdy, // From alloc of allocator.v`
42			output [`PBR_SZ-1:0] pbrd_data, // From dealloc of deallocator.v
43			`output pbrd_srdy, // From dealloc of deallocator.v`
44			`output pbrr_drdy, // From dealloc of deallocator.v`
45			output [(`PAR_DATA_SZ)+(`LL_PG_ASZ*2)-1:0] pm2f_data,// From pm2f_join of sd_ajoin2.v
46			`output pm2f_srdy, // From pm2f_join of sd_ajoin2.v`
47			output [`LL_PG_ASZ-1:0] rlp_rd_page, // From dealloc of deallocator.v
48			`output rlp_srdy, // From dealloc of deallocator.v`
49			`output rlpr_drdy // From dealloc of deallocator.v`
50			`// End of automatics`
51	8	ghutchis	`);`
52
53			wire [`RX_USG_SZ-1:0] rx_usage;
54			wire [`TX_USG_SZ-1:0] tx_usage;
55			wire [`PFW_SZ-1:0] prx_data; // From fifo_rx of sd_fifo_b.v
56			wire [`PFW_SZ-1:0] ptx_data; // From fifo_tx of sd_fifo_b.v
57			wire [`PFW_SZ-1:0] rttx_data; // From ring_tap of port_ring_tap.v
58			`wire [1:0] rxg_code; // From rx_sync_fifo of sd_fifo_s.v`
59			`wire [7:0] rxg_data; // From rx_sync_fifo of sd_fifo_s.v`
60			wire [`PFW_SZ-1:0] ctx_data; // From oflow of egr_oflow.v
61			`/AUTOWIRE/`
62			`// Beginning of automatic wires (for undeclared instantiated-module outputs)`
63	31	ghutchis	`wire a2f_drdy; // From pm2f_join of sd_ajoin2.v`
64			wire [`LL_PG_ASZ-1:0] a2f_end; // From alloc of allocator.v
65			`wire a2f_srdy; // From alloc of allocator.v`
66			wire [`LL_PG_ASZ-1:0] a2f_start; // From alloc of allocator.v
67			`wire crx_abort; // From con of concentrator.v`
68			`wire crx_commit; // From con of concentrator.v`
69			wire [`PFW_SZ-1:0] crx_data; // From con of concentrator.v
70			`wire crx_drdy; // From alloc of allocator.v`
71			`wire crx_srdy; // From con of concentrator.v`
72			`wire gmii_rx_reset; // From port_clocking of port_clocking.v`
73			wire [`PAR_DATA_SZ-1:0] p2f_data; // From pkt_parse of pkt_parse.v
74			`wire p2f_drdy; // From pm2f_join of sd_ajoin2.v`
75			`wire p2f_srdy; // From pkt_parse of pkt_parse.v`
76			`wire [1:0] pdo_code; // From pkt_parse of pkt_parse.v`
77			`wire [7:0] pdo_data; // From pkt_parse of pkt_parse.v`
78			`wire pdo_drdy; // From con of concentrator.v`
79			`wire pdo_srdy; // From pkt_parse of pkt_parse.v`
80			`wire ptx_drdy; // From dst of distributor.v`
81			`wire ptx_srdy; // From dealloc of deallocator.v`
82			`wire [1:0] rxc_rxg_code; // From rx_gigmac of sd_rx_gigmac.v`
83			`wire [7:0] rxc_rxg_data; // From rx_gigmac of sd_rx_gigmac.v`
84			`wire rxc_rxg_drdy; // From rx_sync_fifo of sd_fifo_s.v`
85			`wire rxc_rxg_srdy; // From rx_gigmac of sd_rx_gigmac.v`
86			`wire rxg_drdy; // From pkt_parse of pkt_parse.v`
87			`wire rxg_srdy; // From rx_sync_fifo of sd_fifo_s.v`
88			`wire [1:0] txg_code; // From dst of distributor.v`
89			`wire [7:0] txg_data; // From dst of distributor.v`
90			`wire txg_drdy; // From tx_gmii of sd_tx_gigmac.v`
91			`wire txg_srdy; // From dst of distributor.v`
92	8	ghutchis	`// End of automatics`
93
94
95			`port_clocking port_clocking`
96			`(/AUTOINST/`
97			`// Outputs`
98	31	ghutchis	`.gmii_rx_reset (gmii_rx_reset),`
99	8	ghutchis	`// Inputs`
100	31	ghutchis	`.clk (clk),`
101			`.reset (reset),`
102			`.gmii_rx_clk (gmii_rx_clk));`
103	8	ghutchis
104			`/* sd_rx_gigmac AUTO_TEMPLATE`
105			`(`
106			`.clk (gmii_rx_clk),`
107			`.reset (gmii_rx_reset),`
108			`.rxg_\(.*\) (rxc_rxg_\1[]),`
109			`);`
110			`*/`
111			`sd_rx_gigmac rx_gigmac`
112	31	ghutchis	`(`
113			`.cfg_check_crc (1'b0),`
114			`/AUTOINST/`
115	8	ghutchis	`// Outputs`
116	31	ghutchis	`.rxg_srdy (rxc_rxg_srdy), // Templated`
117			`.rxg_code (rxc_rxg_code[1:0]), // Templated`
118			`.rxg_data (rxc_rxg_data[7:0]), // Templated`
119	8	ghutchis	`// Inputs`
120	31	ghutchis	`.clk (gmii_rx_clk), // Templated`
121			`.reset (gmii_rx_reset), // Templated`
122			`.gmii_rx_dv (gmii_rx_dv),`
123			`.gmii_rxd (gmii_rxd[7:0]),`
124			`.rxg_drdy (rxc_rxg_drdy)); // Templated`
125	8	ghutchis
126			`/* sd_fifo_s AUTO_TEMPLATE`
127			`(`
128			`.c_clk (gmii_rx_clk),`
129			`.c_reset (gmii_rx_reset),`
130			`.c_data ({rxc_rxg_code,rxc_rxg_data}),`
131			`.p_data ({rxg_code,rxg_data}),`
132			`.p_clk (clk),`
133			`.p_reset (reset),`
134			`.c_\(.*\) (rxc_rxg_\1[]),`
135			`.p_\(.*\) (rxg_\1[]),`
136			`);`
137			`*/`
138			`sd_fifo_s #(8+2,16,1) rx_sync_fifo`
139			`(/AUTOINST/`
140			`// Outputs`
141	31	ghutchis	`.c_drdy (rxc_rxg_drdy), // Templated`
142			`.p_srdy (rxg_srdy), // Templated`
143			`.p_data ({rxg_code,rxg_data}), // Templated`
144	8	ghutchis	`// Inputs`
145	31	ghutchis	`.c_clk (gmii_rx_clk), // Templated`
146			`.c_reset (gmii_rx_reset), // Templated`
147			`.c_srdy (rxc_rxg_srdy), // Templated`
148			`.c_data ({rxc_rxg_code,rxc_rxg_data}), // Templated`
149			`.p_clk (clk), // Templated`
150			`.p_reset (reset), // Templated`
151			`.p_drdy (rxg_drdy)); // Templated`
152	8	ghutchis
153	11	ghutchis	`pkt_parse #(port_num) pkt_parse`
154	31	ghutchis	`(`
155			`/AUTOINST/`
156	8	ghutchis	`// Outputs`
157	31	ghutchis	`.rxg_drdy (rxg_drdy),`
158			`.p2f_srdy (p2f_srdy),`
159			.p2f_data (p2f_data[`PAR_DATA_SZ-1:0]),
160			`.pdo_srdy (pdo_srdy),`
161			`.pdo_code (pdo_code[1:0]),`
162			`.pdo_data (pdo_data[7:0]),`
163	8	ghutchis	`// Inputs`
164	31	ghutchis	`.clk (clk),`
165			`.reset (reset),`
166			`.rxg_srdy (rxg_srdy),`
167			`.rxg_code (rxg_code[1:0]),`
168			`.rxg_data (rxg_data[7:0]),`
169			`.p2f_drdy (p2f_drdy),`
170			`.pdo_drdy (pdo_drdy));`
171	8	ghutchis
172			`/* concentrator AUTO_TEMPLATE`
173			`(`
174			`.c_\(.*\) (pdo_\1[]),`
175			`.p_\(.*\) (crx_\1[]),`
176			`);`
177			`*/`
178			`concentrator con`
179			`(/AUTOINST/`
180			`// Outputs`
181	31	ghutchis	`.c_drdy (pdo_drdy), // Templated`
182			.p_data (crx_data[`PFW_SZ-1:0]), // Templated
183			`.p_srdy (crx_srdy), // Templated`
184			`.p_commit (crx_commit), // Templated`
185			`.p_abort (crx_abort), // Templated`
186	8	ghutchis	`// Inputs`
187	31	ghutchis	`.clk (clk),`
188			`.reset (reset),`
189			`.c_data (pdo_data[7:0]), // Templated`
190			`.c_code (pdo_code[1:0]), // Templated`
191			`.c_srdy (pdo_srdy), // Templated`
192			`.p_drdy (crx_drdy)); // Templated`
193	8	ghutchis
194	31	ghutchis	`/* allocator AUTO_TEMPLATE`
195			`(`
196			`);`
197			`*/`
198			`allocator alloc`
199	8	ghutchis	`(/AUTOINST/`
200			`// Outputs`
201	31	ghutchis	`.crx_drdy (crx_drdy),`
202			`.par_srdy (par_srdy),`
203			`.parr_drdy (parr_drdy),`
204			`.lnp_srdy (lnp_srdy),`
205			.lnp_pnp (lnp_pnp[`LL_LNP_SZ-1:0]),
206			.pbra_data (pbra_data[`PBR_SZ-1:0]),
207			`.pbra_srdy (pbra_srdy),`
208			.a2f_start (a2f_start[`LL_PG_ASZ-1:0]),
209			.a2f_end (a2f_end[`LL_PG_ASZ-1:0]),
210			`.a2f_srdy (a2f_srdy),`
211	8	ghutchis	`// Inputs`
212	31	ghutchis	`.clk (clk),`
213			`.reset (reset),`
214			`.crx_abort (crx_abort),`
215			`.crx_commit (crx_commit),`
216			.crx_data (crx_data[`PFW_SZ-1:0]),
217			`.crx_srdy (crx_srdy),`
218			`.par_drdy (par_drdy),`
219			`.parr_srdy (parr_srdy),`
220			.parr_page (parr_page[`LL_PG_ASZ-1:0]),
221			`.lnp_drdy (lnp_drdy),`
222			`.pbra_drdy (pbra_drdy),`
223			`.a2f_drdy (a2f_drdy));`
224	8	ghutchis
225	31	ghutchis	`/* sd_ajoin2 AUTO_TEMPLATE`
226	8	ghutchis	`(`
227	31	ghutchis	`.c2_data ({a2f_end,a2f_start}),`
228			`.c1_\(.*\) (p2f_\1[]),`
229			`.c2_\(.*\) (a2f_\1[]),`
230			`.p_\(.*\) (pm2f_\1[]),`
231			`);`
232	8	ghutchis	`*/`
233	31	ghutchis	sd_ajoin2 #(.c1_width(`PAR_DATA_SZ), .c2_width(`LL_PG_ASZ*2)) pm2f_join
234	8	ghutchis	`(/AUTOINST/`
235			`// Outputs`
236	31	ghutchis	`.c1_drdy (p2f_drdy), // Templated`
237			`.c2_drdy (a2f_drdy), // Templated`
238			`.p_srdy (pm2f_srdy), // Templated`
239			.p_data (pm2f_data[(`PAR_DATA_SZ)+(`LL_PG_ASZ*2)-1:0]), // Templated
240	8	ghutchis	`// Inputs`
241	31	ghutchis	`.clk (clk),`
242			`.reset (reset),`
243			`.c1_srdy (p2f_srdy), // Templated`
244			.c1_data (p2f_data[(`PAR_DATA_SZ)-1:0]), // Templated
245			`.c2_srdy (a2f_srdy), // Templated`
246			`.c2_data ({a2f_end,a2f_start}), // Templated`
247			`.p_drdy (pm2f_drdy)); // Templated`
248	8	ghutchis
249	31	ghutchis	`deallocator dealloc`
250	8	ghutchis	`(/AUTOINST/`
251			`// Outputs`
252	31	ghutchis	`.f2d_drdy (f2d_drdy),`
253			`.rlp_srdy (rlp_srdy),`
254			.rlp_rd_page (rlp_rd_page[`LL_PG_ASZ-1:0]),
255			`.rlpr_drdy (rlpr_drdy),`
256			`.drf_srdy (drf_srdy),`
257			.drf_page_list (drf_page_list[`LL_PG_ASZ*2-1:0]),
258			.pbrd_data (pbrd_data[`PBR_SZ-1:0]),
259			`.pbrd_srdy (pbrd_srdy),`
260			`.pbrr_drdy (pbrr_drdy),`
261			`.ptx_srdy (ptx_srdy),`
262			.ptx_data (ptx_data[`PFW_SZ-1:0]),
263	8	ghutchis	`// Inputs`
264	31	ghutchis	`.clk (clk),`
265			`.reset (reset),`
266			`.port_num (port_num[1:0]),`
267			`.f2d_srdy (f2d_srdy),`
268			.f2d_data (f2d_data[`LL_PG_ASZ-1:0]),
269			`.rlp_drdy (rlp_drdy),`
270			`.rlpr_srdy (rlpr_srdy),`
271			.rlpr_data (rlpr_data[`LL_PG_ASZ:0]),
272			`.drf_drdy (drf_drdy),`
273			`.pbrd_drdy (pbrd_drdy),`
274			`.pbrr_srdy (pbrr_srdy),`
275			.pbrr_data (pbrr_data[`PFW_SZ-1:0]),
276			`.ptx_drdy (ptx_drdy));`
277	8	ghutchis
278			`/* distributor AUTO_TEMPLATE`
279			`(`
280			`.p_\(.*\) (txg_\1[]),`
281			`);`
282			`*/`
283			`distributor dst`
284			`(/AUTOINST/`
285			`// Outputs`
286	31	ghutchis	`.ptx_drdy (ptx_drdy),`
287			`.p_srdy (txg_srdy), // Templated`
288			`.p_code (txg_code[1:0]), // Templated`
289			`.p_data (txg_data[7:0]), // Templated`
290	8	ghutchis	`// Inputs`
291	31	ghutchis	`.clk (clk),`
292			`.reset (reset),`
293			`.ptx_srdy (ptx_srdy),`
294			.ptx_data (ptx_data[`PFW_SZ-1:0]),
295			`.p_drdy (txg_drdy)); // Templated`
296	8	ghutchis
297			`sd_tx_gigmac tx_gmii`
298			`(/AUTOINST/`
299			`// Outputs`
300	31	ghutchis	`.gmii_tx_en (gmii_tx_en),`
301			`.gmii_txd (gmii_txd[7:0]),`
302			`.txg_drdy (txg_drdy),`
303	8	ghutchis	`// Inputs`
304	31	ghutchis	`.clk (clk),`
305			`.reset (reset),`
306			`.txg_srdy (txg_srdy),`
307			`.txg_code (txg_code[1:0]),`
308			`.txg_data (txg_data[7:0]));`
309	8	ghutchis
310			`endmodule // port_macro`
311			`// Local Variables:`
312			`// verilog-library-directories:("." "../../../rtl/verilog/closure" "../../../rtl/verilog/buffers" "../../../rtl/verilog/forks")`
313			`// End:`

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