Subversion Repositories ssbcc

#!/bin/bash

#

# Script to build the micro controller for various 7-series FPGA.

#

# Usage:

#   ./make -v 2014.2 -d xc7a35t-3cpg236 -p 100 [-o "-propconst -sweep -remap -resynth_area"]

# Note:  See the pinouts directory for a list of available devices.

while getopts "hd:o:p:v:" OPTNAME; do

  case ${OPTNAME} in

    ( h ) echo "Usage:  run [-t uc_name] [-v ISE_version]" > /dev/stderr;

          echo "Where:" > /dev/stderr;

          echo "  uc_name is one of the .9x8 files in ../uc" > /dev/stderr;

          echo "  ISE_version is an ISE version number" > /dev/stderr;

          exit 0;;

    ( d ) DEVICE="${OPTARG}";;

    ( o ) OPTPAR="${OPTARG}";;

    ( p ) PERIOD="${OPTARG}";;

    ( v ) VERSION="${OPTARG}";;

  esac

done

VERSION="/opt/Xilinx/Vivado/${VERSION}";

if [ ! -d "${VERSION}" ]; then

  echo "FATAL ERROR:  \"${VERSION}\" not found" > /dev/stderr;

  exit 1;

fi

source "${VERSION}/settings64.sh";

# Ensure a version of vivado has been specified.

if [ -z "`which vivado 2> /dev/null`" ]; then

  echo "FATAL ERROR:  Vivado version not specified" > /dev/stderr;

  exit 1;

fi

# Build the micro controller and convert it to a Vivado IP.

( cd ../uc_led; ./make ) || { echo "FATAL ERROR -- uc build failed" > /dev/stderr; exit 1; }

#

# Run the Vivado TCL script.

#

cat < clock.xdc

create_clock -period ${PERIOD} [get_ports {pi_clk}]

EOF

time vivado -mode tcl <

# Create the project.

create_project build . -part ${DEVICE} -force

set_property constrs_type XDC [current_fileset -constrset]

# Create the top-level design

set_property ip_repo_paths { ../uc_led } [current_fileset];

update_ip_catalog

remove_files -quiet build.scrs/sources_1/bd/top/top.bd

create_bd_design "top"

create_bd_cell -type ip -vlnv sinclairrf.com:none:uc_led:1.0 uc_led

create_bd_port -dir I pi_clk

create_bd_port -dir I pi_rst

create_bd_port -dir O po_led

foreach {sig1 sig2} {

  pi_clk        uc_led/i_clk

  pi_rst        uc_led/i_rst

  uc_led/o_led  po_led

} {

  connect_bd_net [get_bd_pins \$sig1] [get_bd_pins \$sig2];

}

save_bd_design

# Prepare for synthesis.

generate_target {Synthesis} [get_files build.srcs/sources_1/bd/top/top.bd]

generate_target {Implementation} [get_files build.srcs/sources_1/bd/top/top.bd]

set_property top top [current_fileset]

# Run synthesis.

read_xdc clock.xdc

synth_design

report_clocks

# Incorporate device-dependent pinout.

read_xdc pinouts/${DEVICE}.xdc

# Place and route the design.

opt_design ${OPTPAR}

place_design

route_design

# Performance reports.

report_utilization

report_timing_summary

EOF

#

# Extract desired performance statistics from the log file.

#

gawk '

BEGIN { usage_match=0; slack=999999; }

/^1\. Slice Logic/ || /^2\. Slice Logic Distribution/ || /^3\. Memory/ {usage_match=1; next; }

/^[0-9]\./ { usage_match=0; next; }

usage_match && /Slice LUTs/ { LUTs=$5; }

usage_match && ($2 == "Slice") { slices=$4; }

usage_match && ($2 == "RAMB18") { ramb18=$4; }

/^Slack/ { this_slack=1*$4; if (this_slack < slack) slack=this_slack; }

END {

  print "*** Performance Statistics ***";

  print "LUTs   =",LUTs;

  print "Slices =",slices;

  print "Slack  =",slack;

  print "RAMB18 =",ramb18;

}

' vivado.log