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[/] [ssbcc/] [trunk/] [core/] [9x8/] [peripherals/] [latch.v] - Blame information for rev 10

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Line No. Rev Author Line
1 2 sinclairrf
//
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// latch peripheral for @INSIGNAL@
3 10 sinclairrf
// Copyright 2013, Sinclair R.F., Inc.
4 2 sinclairrf
//
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generate
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// Register the input signal when  commanded.
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reg [@LATCH_WIDTH@-1:0] s__latch = {(@LATCH_WIDTH@){1'b0}};
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always @ (posedge i_clk)
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  if (i_rst)
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    s__latch <= {(@LATCH_WIDTH@){1'b0}};
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  else if (s_outport && (s_T == 8'd@IX_O_LATCH@))
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    s__latch[0+:@WIDTH@] <= @INSIGNAL@;
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  else
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    s__latch <= s__latch;
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// Latch the mux address when commanded.
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reg [@ADDR_WIDTH@-1:0] s__addr = {(@ADDR_WIDTH@){1'b0}};
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always @ (posedge i_clk)
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  if (i_rst)
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    s__addr <= {(@ADDR_WIDTH@){1'b0}};
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  else if (s_outport && (s_T == 8'd@IX_O_ADDR@))
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    s__addr <= s_N[0+:@ADDR_WIDTH@];
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  else
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    s__addr <= s__addr;
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// Run the mux.
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integer ix;
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always @ (posedge i_clk)
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  if (i_rst)
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    s__select <= 8'h00;
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  else begin
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    s__select <= 8'h00;
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    for (ix=0; ix<@LATCH_WIDTH@/8; ix=ix+1)
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      if (ix[0+:@ADDR_WIDTH@] == s__addr)
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        s__select <= s__latch[8*ix+:8];
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  end
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endgenerate

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