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#

# Copyright 2014, Sinclair R.F., Inc.

#

# Test bench for wide_strobe peripheral.

#

ARCHITECTURE    core/9x8 Verilog

INSTRUCTION     64

DATA_STACK      32

RETURN_STACK    16

PORTCOMMENT     narrow strobe bus

PERIPHERAL      wide_strobe     outport=O_MIN   \

                                outsignal=o_min \

                                width=1

PORTCOMMENT     medium-width strobe bus

PERIPHERAL      wide_strobe     outport=O_MED   \

                                outsignal=o_med \

                                width=4

PORTCOMMENT     maximum-width strobe bus

PERIPHERAL      wide_strobe     outport=O_MAX   \

                                outsignal=o_max \

                                width=8

PORTCOMMENT termination signal

OUTPORT 1-bit o_done O_DONE

ASSEMBLY tb_wide_strobe.s