Subversion Repositories ssbcc

# Copyright 2013, Sinclair R.F., Inc.

# Test Bench for conditional compilation

ARCHITECTURE core/9x8 Verilog

ASSEMBLY uc.s

INSTRUCTION     2048

DATA_STACK      32

RETURN_STACK    32

PARAMETER G_CLK_FREQ_HZ 50_000_000

.IFDEF D_INCLUDE_UART

PORTCOMMENT UART

PERIPHERAL      UART_Tx outport=O_UART_TX \

                        outstatus=I_UART_TX_BUSY \

                        baudmethod=G_CLK_FREQ_HZ/115200 \

                        outsignal=o_uart_tx

.ENDIF

.IFNDEF D_INCLUDE_I2C

PORTCOMMENT WARNING -- NO I2C BUS

.ELSE

PORTCOMMENT I2C bus

PERIPHERAL open_drain   inport=I_SCL \

                        outport=O_SCL \

                        iosignal=io_scl

PERIPHERAL open_drain   inport=I_SDA \

                        outport=O_SDA \

                        iosignal=io_sda

.ENDIF