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// ------------------------- CONFIDENTIAL ------------------------------------
//
//  Copyright 2008-2011 by Michael A. Morris, dba M. A. Morris & Associates
//
//  All rights reserved.  No part of this source code may be reproduced or
//  transmitted in any form or by any means, electronic or mechanical,
//  including photocopying, recording, or any information storage and
//  retrieval system, without permission in writing from Michael A. Morris, 
//  dba M. A. Morris & Associates.
//
//  Further, no use of this source code is permitted in any form or means
//  without a valid, written license agreement with Michael A. Morris, dba
//  M. A. Morris & Associates.
//
//  Michael A. Morris
//  dba M. A. Morris & Associates
//  164 Raleigh Way
//  Huntsville, AL 35811, USA
//  Ph.  +1 256 508 5869
//
// Licensed To:     DopplerTech, Inc. (DTI)
//                  9345 E. South Frontage Rd.
//                  Yuma, AZ 85365
//
// ----------------------------------------------------------------------------
 
`timescale 1ns / 1ps
 
///////////////////////////////////////////////////////////////////////////////
// Company:         M. A. Morris & Associates
// Engineer:        Michael A. Morris
//
// Create Date:     07:33 05/10/2008 
// Design Name:     LTAS 
// Module Name:     C:/XProjects/ISE10.1i/LTAS/LTAS_Top.v
// Project Name:    LTAS 
// Target Devices:  XC3S700AN-5FFG484I 
// Tool versions:   ISE 10.1i SP3 
//
// Description:
//
//  This module implements a full-duplex (Slave) SSP interface for 16-bit 
//  frames. In accordance to standard SPI practice, the module expects that
//  data is shifted into it MSB first. The first three bits are address bits,
//  the fourth bit is a command (WnR) bit which determines the operations to
//  be performed on the register, and the final twelve (12) bits are data bits.
//
// Dependencies:    None
//
// Revision History:
//
//  0.01    08E10   MAM     File Created
//
//  1.00    08E10   MAM     Initial Release
//
//  1.10    08G24   MAM     Modified the interface to operate with registered
//                          shift register data to eliminate transitions on
//                          MISO after risisng edge of SCK when input register
//                          written. Register RA[3:0] during fourth clock, and
//                          register DO[11:0] on falling edge of SCK after RA
//                          registered. This holds output data constant for the
//                          entire shift cycle.
//
//  1.11    11B01   MAM     Corrected #1 delay statement placement in register
//
//  2.00    11B06   MAM     Modified the interface to separate RA[3:1] and 
//                          RA[0] into RA[2:0] address port and a WnR command
//                          port. This makes the operation of the SSP/SPI I/F
//                          more clear.
//                          
//
// Additional Comments: 
//
///////////////////////////////////////////////////////////////////////////////
 
module SSPx_Slv(
    input   Rst,            // System Reset
//
    input   SSEL,           // Slave Select
    input   SCK,            // Shift Clock
    input   MOSI,           // Master Out, Slave In: Serial Data In
    output  reg MISO,       // Master In, Slave Out: Serial Data Out
//
    output  reg [2:0] RA,   // SSP Register Address output
    output  reg WnR,        // SSP Command: 1 - Write, 0 - Read
    output  En,             // SSP Enable - asserted during field
    output  reg EOC,        // SSP End of Cycle - asserted on last bit of frame
    output  reg [11:0] DI,  // Input shift register output
    input   [11:0] DO,      // Output shift register input
//
    output  reg [3:0] BC    // Bit Count, 0 - MSB; 15 - LSB
);
 
///////////////////////////////////////////////////////////////////////////////    
//
//  Local Declarations
//
 
    reg     [15:1] RDI; // Serial Input Shift Register
    reg     [11:0] rDO; // output data register
 
///////////////////////////////////////////////////////////////////////////////
//
//  Implementation
//
 
//  Module Reset - asynchronous because SCK not continuous
 
assign Rst_SSP = (Rst | ~SSEL);
 
//  Bit Counter, count from 0 to 15
//      Clock on negedge SCK to align MISO in bit cell
 
always @(negedge SCK or posedge Rst_SSP)
begin
    if(Rst_SSP)
        BC <= #1 4'd0;
    else
        BC <= #1 (BC + 1);
end
 
//  End-Of-Cycle, asserted during last bit of transfer (bit 15)
//      Clock on negedge SCK to center rising edge in bit cell
 
always @(negedge SCK or posedge Rst_SSP)
begin
    if(Rst_SSP)
        EOC <= #1 1'b0;
    else
        EOC <= #1 (BC == 14);
end
 
//  Generate SSP Enable, require four bits for internal addressing
 
assign En = BC[3] | BC[2];
 
//  Load MOSI into RDI using BC to select the active register
//      Use posedge SCK to sample in middle of bit cell
 
always @(posedge SCK or posedge Rst_SSP)
begin
    if(Rst_SSP)
        RDI <= #1 15'b0;
    else
        case(BC)
            4'b0000 :   RDI[15] <= #1 MOSI;
            4'b0001 :   RDI[14] <= #1 MOSI;
            4'b0010 :   RDI[13] <= #1 MOSI;
            4'b0011 :   RDI[12] <= #1 MOSI;
            4'b0100 :   RDI[11] <= #1 MOSI;
            4'b0101 :   RDI[10] <= #1 MOSI;
            4'b0110 :   RDI[ 9] <= #1 MOSI;
            4'b0111 :   RDI[ 8] <= #1 MOSI;
            4'b1000 :   RDI[ 7] <= #1 MOSI;
            4'b1001 :   RDI[ 6] <= #1 MOSI;
            4'b1010 :   RDI[ 5] <= #1 MOSI;
            4'b1011 :   RDI[ 4] <= #1 MOSI;
            4'b1100 :   RDI[ 3] <= #1 MOSI;
            4'b1101 :   RDI[ 2] <= #1 MOSI;
            4'b1110 :   RDI[ 1] <= #1 MOSI;
        endcase
end
 
//  Assign RA, WnR, and DI bus from RDI and MOSI
 
//always @(posedge SCK or posedge Rst)
//begin
//    if(Rst)
//        RA <= #1 0;
//    else if(BC == 2)
//        RA <= #1 {RDI[15:14], MOSI};
//end
//
//always @(posedge SCK or posedge Rst)
//begin
//    if(Rst)
//        WnR <= #1 0;
//    else if(BC == 3)
//        WnR <= #1 MOSI;
//end
 
always @(negedge SCK or posedge Rst)
begin
    if(Rst)
        RA <= #1 0;
    else if(BC == 2)
        RA <= #1 RDI[15:13];
end
 
always @(negedge SCK or posedge Rst)
begin
    if(Rst)
        WnR <= #1 0;
    else if(EOC)
        WnR <= #1 0;
    else if(BC == 3)
        WnR <= #1 RDI[12];
end
 
always @(posedge SCK or posedge Rst)
begin
    if(Rst)
        DI <= #1 0;
    else if(EOC)
        DI <= #1 {RDI[11:1], MOSI};
end
 
always @(negedge SCK or posedge Rst)
begin
    if(Rst)
        rDO <= #1 0;
    else if(BC == 3)
        rDO <= #1 DO;
end
 
// Generate MISO: multiplex MOSI and DO using En and BC
 
always @(BC or rDO or MOSI)
begin
    case(BC)
        4'b0000 :   MISO <= MOSI;
        4'b0001 :   MISO <= MOSI;
        4'b0010 :   MISO <= MOSI;
        4'b0011 :   MISO <= MOSI;
        4'b0100 :   MISO <= rDO[11];
        4'b0101 :   MISO <= rDO[10];
        4'b0110 :   MISO <= rDO[ 9];
        4'b0111 :   MISO <= rDO[ 8];
        4'b1000 :   MISO <= rDO[ 7];
        4'b1001 :   MISO <= rDO[ 6];
        4'b1010 :   MISO <= rDO[ 5];
        4'b1011 :   MISO <= rDO[ 4];
        4'b1100 :   MISO <= rDO[ 3];
        4'b1101 :   MISO <= rDO[ 2];
        4'b1110 :   MISO <= rDO[ 1];
        4'b1111 :   MISO <= rDO[ 0];
    endcase
end
 
endmodule

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Subversion Repositories ssp_slv

[/] [ssp_slv/] [trunk/] [RTL/] [SSPx_Slv.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	MichaelA	`// ------------------------- CONFIDENTIAL ------------------------------------`
2			`//`
3			`// Copyright 2008-2011 by Michael A. Morris, dba M. A. Morris & Associates`
4			`//`
5			`// All rights reserved. No part of this source code may be reproduced or`
6			`// transmitted in any form or by any means, electronic or mechanical,`
7			`// including photocopying, recording, or any information storage and`
8			`// retrieval system, without permission in writing from Michael A. Morris,`
9			`// dba M. A. Morris & Associates.`
10			`//`
11			`// Further, no use of this source code is permitted in any form or means`
12			`// without a valid, written license agreement with Michael A. Morris, dba`
13			`// M. A. Morris & Associates.`
14			`//`
15			`// Michael A. Morris`
16			`// dba M. A. Morris & Associates`
17			`// 164 Raleigh Way`
18			`// Huntsville, AL 35811, USA`
19			`// Ph. +1 256 508 5869`
20			`//`
21			`// Licensed To: DopplerTech, Inc. (DTI)`
22			`// 9345 E. South Frontage Rd.`
23			`// Yuma, AZ 85365`
24			`//`
25			`// ----------------------------------------------------------------------------`
26
27			`timescale 1ns / 1ps
28
29			`///////////////////////////////////////////////////////////////////////////////`
30			`// Company: M. A. Morris & Associates`
31			`// Engineer: Michael A. Morris`
32			`//`
33			`// Create Date: 07:33 05/10/2008`
34			`// Design Name: LTAS`
35			`// Module Name: C:/XProjects/ISE10.1i/LTAS/LTAS_Top.v`
36			`// Project Name: LTAS`
37			`// Target Devices: XC3S700AN-5FFG484I`
38			`// Tool versions: ISE 10.1i SP3`
39			`//`
40			`// Description:`
41			`//`
42			`// This module implements a full-duplex (Slave) SSP interface for 16-bit`
43			`// frames. In accordance to standard SPI practice, the module expects that`
44			`// data is shifted into it MSB first. The first three bits are address bits,`
45			`// the fourth bit is a command (WnR) bit which determines the operations to`
46			`// be performed on the register, and the final twelve (12) bits are data bits.`
47			`//`
48			`// Dependencies: None`
49			`//`
50			`// Revision History:`
51			`//`
52			`// 0.01 08E10 MAM File Created`
53			`//`
54			`// 1.00 08E10 MAM Initial Release`
55			`//`
56			`// 1.10 08G24 MAM Modified the interface to operate with registered`
57			`// shift register data to eliminate transitions on`
58			`// MISO after risisng edge of SCK when input register`
59			`// written. Register RA[3:0] during fourth clock, and`
60			`// register DO[11:0] on falling edge of SCK after RA`
61			`// registered. This holds output data constant for the`
62			`// entire shift cycle.`
63			`//`
64			`// 1.11 11B01 MAM Corrected #1 delay statement placement in register`
65			`//`
66			`// 2.00 11B06 MAM Modified the interface to separate RA[3:1] and`
67			`// RA[0] into RA[2:0] address port and a WnR command`
68			`// port. This makes the operation of the SSP/SPI I/F`
69			`// more clear.`
70			`//`
71			`//`
72			`// Additional Comments:`
73			`//`
74			`///////////////////////////////////////////////////////////////////////////////`
75
76			`module SSPx_Slv(`
77			`input Rst, // System Reset`
78			`//`
79			`input SSEL, // Slave Select`
80			`input SCK, // Shift Clock`
81			`input MOSI, // Master Out, Slave In: Serial Data In`
82			`output reg MISO, // Master In, Slave Out: Serial Data Out`
83			`//`
84			`output reg [2:0] RA, // SSP Register Address output`
85			`output reg WnR, // SSP Command: 1 - Write, 0 - Read`
86			`output En, // SSP Enable - asserted during field`
87			`output reg EOC, // SSP End of Cycle - asserted on last bit of frame`
88			`output reg [11:0] DI, // Input shift register output`
89			`input [11:0] DO, // Output shift register input`
90			`//`
91			`output reg [3:0] BC // Bit Count, 0 - MSB; 15 - LSB`
92			`);`
93
94			`///////////////////////////////////////////////////////////////////////////////`
95			`//`
96			`// Local Declarations`
97			`//`
98
99			`reg [15:1] RDI; // Serial Input Shift Register`
100			`reg [11:0] rDO; // output data register`
101
102			`///////////////////////////////////////////////////////////////////////////////`
103			`//`
104			`// Implementation`
105			`//`
106
107			`// Module Reset - asynchronous because SCK not continuous`
108
109			`assign Rst_SSP = (Rst \| ~SSEL);`
110
111			`// Bit Counter, count from 0 to 15`
112			`// Clock on negedge SCK to align MISO in bit cell`
113
114			`always @(negedge SCK or posedge Rst_SSP)`
115			`begin`
116			`if(Rst_SSP)`
117			`BC <= #1 4'd0;`
118			`else`
119			`BC <= #1 (BC + 1);`
120			`end`
121
122			`// End-Of-Cycle, asserted during last bit of transfer (bit 15)`
123			`// Clock on negedge SCK to center rising edge in bit cell`
124
125			`always @(negedge SCK or posedge Rst_SSP)`
126			`begin`
127			`if(Rst_SSP)`
128			`EOC <= #1 1'b0;`
129			`else`
130			`EOC <= #1 (BC == 14);`
131			`end`
132
133			`// Generate SSP Enable, require four bits for internal addressing`
134
135			`assign En = BC[3] \| BC[2];`
136
137			`// Load MOSI into RDI using BC to select the active register`
138			`// Use posedge SCK to sample in middle of bit cell`
139
140			`always @(posedge SCK or posedge Rst_SSP)`
141			`begin`
142			`if(Rst_SSP)`
143			`RDI <= #1 15'b0;`
144			`else`
145			`case(BC)`
146			`4'b0000 : RDI[15] <= #1 MOSI;`
147			`4'b0001 : RDI[14] <= #1 MOSI;`
148			`4'b0010 : RDI[13] <= #1 MOSI;`
149			`4'b0011 : RDI[12] <= #1 MOSI;`
150			`4'b0100 : RDI[11] <= #1 MOSI;`
151			`4'b0101 : RDI[10] <= #1 MOSI;`
152			`4'b0110 : RDI[ 9] <= #1 MOSI;`
153			`4'b0111 : RDI[ 8] <= #1 MOSI;`
154			`4'b1000 : RDI[ 7] <= #1 MOSI;`
155			`4'b1001 : RDI[ 6] <= #1 MOSI;`
156			`4'b1010 : RDI[ 5] <= #1 MOSI;`
157			`4'b1011 : RDI[ 4] <= #1 MOSI;`
158			`4'b1100 : RDI[ 3] <= #1 MOSI;`
159			`4'b1101 : RDI[ 2] <= #1 MOSI;`
160			`4'b1110 : RDI[ 1] <= #1 MOSI;`
161			`endcase`
162			`end`
163
164			`// Assign RA, WnR, and DI bus from RDI and MOSI`
165
166			`//always @(posedge SCK or posedge Rst)`
167			`//begin`
168			`// if(Rst)`
169			`// RA <= #1 0;`
170			`// else if(BC == 2)`
171			`// RA <= #1 {RDI[15:14], MOSI};`
172			`//end`
173			`//`
174			`//always @(posedge SCK or posedge Rst)`
175			`//begin`
176			`// if(Rst)`
177			`// WnR <= #1 0;`
178			`// else if(BC == 3)`
179			`// WnR <= #1 MOSI;`
180			`//end`
181
182			`always @(negedge SCK or posedge Rst)`
183			`begin`
184			`if(Rst)`
185			`RA <= #1 0;`
186			`else if(BC == 2)`
187			`RA <= #1 RDI[15:13];`
188			`end`
189
190			`always @(negedge SCK or posedge Rst)`
191			`begin`
192			`if(Rst)`
193			`WnR <= #1 0;`
194			`else if(EOC)`
195			`WnR <= #1 0;`
196			`else if(BC == 3)`
197			`WnR <= #1 RDI[12];`
198			`end`
199
200			`always @(posedge SCK or posedge Rst)`
201			`begin`
202			`if(Rst)`
203			`DI <= #1 0;`
204			`else if(EOC)`
205			`DI <= #1 {RDI[11:1], MOSI};`
206			`end`
207
208			`always @(negedge SCK or posedge Rst)`
209			`begin`
210			`if(Rst)`
211			`rDO <= #1 0;`
212			`else if(BC == 3)`
213			`rDO <= #1 DO;`
214			`end`
215
216			`// Generate MISO: multiplex MOSI and DO using En and BC`
217
218			`always @(BC or rDO or MOSI)`
219			`begin`
220			`case(BC)`
221			`4'b0000 : MISO <= MOSI;`
222			`4'b0001 : MISO <= MOSI;`
223			`4'b0010 : MISO <= MOSI;`
224			`4'b0011 : MISO <= MOSI;`
225			`4'b0100 : MISO <= rDO[11];`
226			`4'b0101 : MISO <= rDO[10];`
227			`4'b0110 : MISO <= rDO[ 9];`
228			`4'b0111 : MISO <= rDO[ 8];`
229			`4'b1000 : MISO <= rDO[ 7];`
230			`4'b1001 : MISO <= rDO[ 6];`
231			`4'b1010 : MISO <= rDO[ 5];`
232			`4'b1011 : MISO <= rDO[ 4];`
233			`4'b1100 : MISO <= rDO[ 3];`
234			`4'b1101 : MISO <= rDO[ 2];`
235			`4'b1110 : MISO <= rDO[ 1];`
236			`4'b1111 : MISO <= rDO[ 0];`
237			`endcase`
238			`end`
239
240			`endmodule`