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[/] [statled/] [trunk/] [rtl/] [statled.v] - Blame information for rev 2

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Line No.	Rev	Author	Line
1	2	mitko	`timescale 1ns / 100ps
2			`/******************************************************************************`
3			`* Status LED module`
4			`*`
5			`* Use single LED ouput to displays various internal states as blink codes.`
6			`* http://www.opencores.org/cores/statled`
7			`*`
8			`******************************************************************************/`
9			`module statled (`
10			`input clk,`
11			`input rst,`
12			`input [3:0] status,`
13			`output led`
14			`);`
15
16			`include "statled_par.v"
17
18			`reg [32:0] pre; // Prescaler`
19			`reg [7:0] bcnt; // Bit counter`
20			`reg [15:0] lsr; // LED shift register`
21			`reg [15:0] cr; // Code register`
22			`reg [3:0] str; // Status register`
23			`wire rate; // LED rate`
24
25			`//-----------------------------------------------------------------------------`
26			`// LED rate`
27			`//`
28			`always @(posedge clk or posedge rst)`
29			`if (rst)`
30			`pre <= #tDLY 0;`
31			`else if (rate)`
32			`pre <= #tDLY 0;`
33			`else`
34			`pre <= #tDLY pre + 1;`
35
36			`assign rate = (pre == STATLED_PULSE_CLKCNT);`
37
38			`//-----------------------------------------------------------------------------`
39			`// Capture status inputs`
40			`//`
41			`always @(posedge clk or posedge rst)`
42			`if (rst)`
43			`str <= #tDLY 0;`
44			`else`
45			`str <= #tDLY status;`
46
47			`//-----------------------------------------------------------------------------`
48			`// Shift register and bit counter`
49			`//`
50			`always @(posedge clk or posedge rst)`
51			`if (rst)`
52			`bcnt <= #tDLY 15;`
53			`else if (bcnt == 16)`
54			`bcnt <= #tDLY 0;`
55			`else if (rate)`
56			`bcnt <= #tDLY bcnt + 1;`
57
58			`always @(posedge clk or posedge rst)`
59			`if (rst)`
60			`lsr <= #tDLY 0;`
61			`else if (bcnt == 16)`
62			`lsr <= #tDLY cr;`
63			`else if (rate)`
64			`lsr <= #tDLY lsr << 1;`
65
66			`assign led = rst? 1 : lsr[15];`
67
68			`//-----------------------------------------------------------------------------`
69			`// Codes`
70			`//`
71			`always @*`
72			`case(str)`
73			`0: cr = CODE_50_50; // Default code`
74			`1: cr = CODE_ONE; // State 1`
75			`2: cr = CODE_TWO; // State 2`
76			`3: cr = CODE_THREE; // ....`
77			`4: cr = CODE_FOUR; //`
78			`5: cr = CODE_FIVE; //`
79			`6: cr = CODE_SIX; //`
80
81			`default: cr = 0;`
82			`endcase`
83
84			`endmodule`

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[/] [statled/] [trunk/] [rtl/] [statled.v] - Blame information for rev 2