| 1 |
2 |
hiroshi |
/* *****************************************************************************
|
| 2 |
|
|
* title: uart_16550_rll module *
|
| 3 |
|
|
* description: RS232 Protocol 16550D uart (mostly supported) *
|
| 4 |
|
|
* languages: systemVerilog *
|
| 5 |
|
|
* *
|
| 6 |
|
|
* Copyright (C) 2010 miyagi.hiroshi *
|
| 7 |
|
|
* *
|
| 8 |
|
|
* This library is free software; you can redistribute it and/or *
|
| 9 |
|
|
* modify it under the terms of the GNU Lesser General Public *
|
| 10 |
|
|
* License as published by the Free Software Foundation; either *
|
| 11 |
|
|
* version 2.1 of the License, or (at your option) any later version. *
|
| 12 |
|
|
* *
|
| 13 |
|
|
* This library is distributed in the hope that it will be useful, *
|
| 14 |
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
|
| 15 |
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU *
|
| 16 |
|
|
* Lesser General Public License for more details. *
|
| 17 |
|
|
* *
|
| 18 |
|
|
* You should have received a copy of the GNU Lesser General Public *
|
| 19 |
|
|
* License along with this library; if not, write to the Free Software *
|
| 20 |
|
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111*1307 USA *
|
| 21 |
|
|
* *
|
| 22 |
|
|
* *** GNU LESSER GENERAL PUBLIC LICENSE *** *
|
| 23 |
|
|
* from http://www.gnu.org/licenses/lgpl.txt *
|
| 24 |
|
|
*****************************************************************************
|
| 25 |
|
|
* redleaflogic,ltd *
|
| 26 |
|
|
* miyagi.hiroshi@redleaflogic.biz *
|
| 27 |
|
|
* $Id: uart_16550_rll.sv 108 2010-03-30 02:56:26Z hiroshi $ *
|
| 28 |
|
|
***************************************************************************** */
|
| 29 |
|
|
|
| 30 |
|
|
`ifdef SYN
|
| 31 |
|
|
/* empty */
|
| 32 |
|
|
`else
|
| 33 |
|
|
timeunit 1ps ;
|
| 34 |
|
|
timeprecision 1ps ;
|
| 35 |
|
|
`endif
|
| 36 |
|
|
|
| 37 |
|
|
module uart_16550_rll(interface wb_bus, uart_bus uart_bus) ;
|
| 38 |
|
|
import uart_package:: * ;
|
| 39 |
|
|
|
| 40 |
|
|
wire clk_i = wb_bus.clk_i ;
|
| 41 |
|
|
wire nrst_i = wb_bus.nrst_i ;
|
| 42 |
|
|
wire overrun ;
|
| 43 |
|
|
wire rec_buf_empty ;
|
| 44 |
|
|
wire trans_buf_empty ;
|
| 45 |
|
|
wire rec_clk_en ;
|
| 46 |
|
|
wire rec_sample_pulse ;
|
| 47 |
|
|
wire leading_edge ;
|
| 48 |
|
|
wire trans_clk_en ;
|
| 49 |
|
|
wire txd_out ;
|
| 50 |
|
|
wire rxd_clean ;
|
| 51 |
|
|
wire rxd_clean_out ;
|
| 52 |
|
|
wire timeout_signal ;
|
| 53 |
|
|
|
| 54 |
|
|
fifo_bus
|
| 55 |
|
|
fifo_pop_trans(.clk_i(clk_i)),
|
| 56 |
|
|
fifo_push_rec(.clk_i(clk_i)) ;
|
| 57 |
|
|
|
| 58 |
|
|
// uart_bus uart_bus() ;
|
| 59 |
|
|
u_reg_t u_reg ;
|
| 60 |
|
|
codec_state_t rec_next_state ;
|
| 61 |
|
|
u_codec_t trans_codec ;
|
| 62 |
|
|
|
| 63 |
|
|
// -- loopback mode --
|
| 64 |
|
|
assign uart_bus.stx_o = u_reg.modem_control_reg.loopback == 1'b1 ? 1'b1 : txd_out ;
|
| 65 |
|
|
assign rxd_clean = u_reg.modem_control_reg.loopback == 1'b1 ? txd_out : rxd_clean_out ;
|
| 66 |
|
|
|
| 67 |
|
|
uart_register u_register(.clk_i(clk_i),
|
| 68 |
|
|
.nrst_i(nrst_i),
|
| 69 |
|
|
.wb_bus(wb_bus),
|
| 70 |
|
|
.uart_bus(uart_bus),
|
| 71 |
|
|
.u_reg(u_reg),
|
| 72 |
|
|
.fifo_pop_trans(fifo_pop_trans),
|
| 73 |
|
|
.fifo_push_rec(fifo_push_rec),
|
| 74 |
|
|
.timeout_signal(timeout_signal),
|
| 75 |
|
|
.overrun(overrun),
|
| 76 |
|
|
.rec_buf_empty(rec_buf_empty),
|
| 77 |
|
|
.trans_buf_empty(trans_buf_empty)) ;
|
| 78 |
|
|
|
| 79 |
|
|
uart_transmitter u_trans(.clk_i(clk_i),
|
| 80 |
|
|
.nrst_i(nrst_i),
|
| 81 |
|
|
.trans_clk_en(trans_clk_en),
|
| 82 |
|
|
.txd_out(txd_out),
|
| 83 |
|
|
.fifo_pop(fifo_pop_trans.pop_master_mp),
|
| 84 |
|
|
.u_reg(u_reg),
|
| 85 |
|
|
.trans_codec(trans_codec),
|
| 86 |
|
|
.trans_buf_empty(trans_buf_empty)) ;
|
| 87 |
|
|
|
| 88 |
|
|
uart_receiver u_rec(.clk_i(clk_i),
|
| 89 |
|
|
.nrst_i(nrst_i),
|
| 90 |
|
|
.rec_clk_en(rec_clk_en),
|
| 91 |
|
|
.rec_sample_pulse(rec_sample_pulse),
|
| 92 |
|
|
.rxd_clean(rxd_clean),
|
| 93 |
|
|
.leading_edge(leading_edge),
|
| 94 |
|
|
.timeout_signal(timeout_signal),
|
| 95 |
|
|
.fifo_push(fifo_push_rec.push_master_mp),
|
| 96 |
|
|
.u_reg(u_reg),
|
| 97 |
|
|
.next_state(rec_next_state),
|
| 98 |
|
|
.overrun(overrun),
|
| 99 |
|
|
.rec_buf_empty(rec_buf_empty)) ;
|
| 100 |
|
|
|
| 101 |
|
|
uart_baud u_baud(.clk_i(clk_i),
|
| 102 |
|
|
.nrst_i(nrst_i),
|
| 103 |
|
|
.u_reg(u_reg),
|
| 104 |
|
|
.rec_next_state(rec_next_state),
|
| 105 |
|
|
.trans_codec(trans_codec),
|
| 106 |
|
|
.rxd_clean(rxd_clean),
|
| 107 |
|
|
.rec_clk_en(rec_clk_en),
|
| 108 |
|
|
.rec_sample_pulse(rec_sample_pulse),
|
| 109 |
|
|
.leading_edge(leading_edge),
|
| 110 |
|
|
.timeout_signal(timeout_signal),
|
| 111 |
|
|
.trans_clk_en(trans_clk_en)) ;
|
| 112 |
|
|
|
| 113 |
|
|
uart_noize_shaver u_shaver(.clk_i(clk_i),
|
| 114 |
|
|
.nrst_i(nrst_i),
|
| 115 |
|
|
.rxd_i(uart_bus.srx_i),
|
| 116 |
|
|
.rxd_clean(rxd_clean_out)) ;
|
| 117 |
|
|
|
| 118 |
|
|
endmodule
|
| 119 |
|
|
|
| 120 |
|
|
/// END OF FILE ///
|
