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#!/usr/bin/env python
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"""A C to Verilog compiler"""
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__author__ = "Jon Dawson"
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__copyright__ = "Copyright (C) 2013, Jonathan P Dawson"
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__version__ = "0.1"
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import fpu
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def unique(l):
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"""In the absence of set in older python implementations, make list values unique"""
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return dict(zip(l, l)).keys()
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def log2(frames):
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"""Integer only algorithm to calculate the number of bits needed to store a number"""
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bits = 1
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power = 2
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while power < frames:
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bits += 1
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power *= 2
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return bits
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def to_gray(i):
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"""Convert integer to gray code"""
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return (i >> 1) ^ i
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def sign_extend(value, bytes_):
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bits = bytes_*8
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mask = (1<<bits)-1
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mask = ~mask
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if value & 1<<(bits-1):
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return value | mask
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else:
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return value
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def floating_point_enables(frames):
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enable_adder = False
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enable_multiplier = False
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enable_divider = False
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enable_int_to_float = False
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enable_float_to_int = False
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for frame in frames:
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for i in frame:
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if i["op"] == "+" and "type" in i and i["type"] == "float":
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enable_adder = True
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if i["op"] == "-" and "type" in i and i["type"] == "float":
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enable_adder = True
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if i["op"] == "*" and "type" in i and i["type"] == "float":
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enable_multiplier = True
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if i["op"] == "/" and "type" in i and i["type"] == "float":
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enable_divider = True
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if i["op"] == "int_to_float":
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enable_int_to_float = True
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if i["op"] == "float_to_int":
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enable_float_to_int = True
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return (
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enable_adder,
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enable_multiplier,
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enable_divider,
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enable_int_to_float,
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enable_float_to_int)
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def generate_CHIP(input_file,
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name,
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frames,
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output_file,
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registers,
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memory_size_2,
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memory_size_4,
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initialize_memory,
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memory_content_2,
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memory_content_4,
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no_tb_mode=False):
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"""A big ugly function to crunch through all the instructions and generate the CHIP equivilent"""
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#calculate the values of jump locations
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location = 0
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labels = {}
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new_frames = []
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for frame in frames:
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if frame[0]["op"] == "label":
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labels[frame[0]["label"]] = location
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else:
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new_frames.append(frame)
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location += 1
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frames = new_frames
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#substitue real values for labeled jump locations
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for frame in frames:
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for instruction in frame:
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if "label" in instruction:
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instruction["label"]=labels[instruction["label"]]
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#list all inputs and outputs used in the program
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inputs = unique([i["input"] for frame in frames for i in frame if "input" in i])
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outputs = unique([i["output"] for frame in frames for i in frame if "output" in i])
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input_files = unique([i["file_name"] for frame in frames for i in frame if "file_read" == i["op"]])
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output_files = unique([i["file_name"] for frame in frames for i in frame if "file_write" == i["op"]])
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testbench = not inputs and not outputs and not no_tb_mode
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enable_adder, enable_multiplier, enable_divider, enable_int_to_float, enable_float_to_int = floating_point_enables(frames)
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#Do not generate a port in testbench mode
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inports = [
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("input_" + i, 16) for i in inputs
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] + [
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("input_" + i + "_stb", 1) for i in inputs
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] + [
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("output_" + i + "_ack", 1) for i in outputs
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]
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outports = [
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("output_" + i, 16) for i in outputs
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] + [
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("output_" + i + "_stb", 1) for i in outputs
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] + [
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("input_" + i + "_ack", 1) for i in inputs
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]
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#create list of signals
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signals = [
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("timer", 16),
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("program_counter", log2(len(frames))),
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("address_2", 16),
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("data_out_2", 16),
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("data_in_2", 16),
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("write_enable_2", 1),
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("address_4", 16),
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("data_out_4", 32),
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("data_in_4", 32),
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("write_enable_4", 1),
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] + [
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("register_%s"%(register), definition[1]*8) for register, definition in registers.iteritems()
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] + [
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("s_output_" + i + "_stb", 16) for i in outputs
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] + [
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("s_output_" + i, 16) for i in outputs
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] + [
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("s_input_" + i + "_ack", 16) for i in inputs
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]
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if testbench:
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signals.append(("clk", 1))
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signals.append(("rst", 1))
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else:
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inports.append(("clk", 1))
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inports.append(("rst", 1))
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if enable_adder:
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output_file.write(fpu.adder)
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if enable_divider:
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output_file.write(fpu.divider)
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if enable_multiplier:
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output_file.write(fpu.multiplier)
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if enable_int_to_float:
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output_file.write(fpu.int_to_float)
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if enable_float_to_int:
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output_file.write(fpu.float_to_int)
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#output the code in verilog
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output_file.write("//name : %s\n"%name)
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output_file.write("//tag : c components\n")
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for i in inputs:
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output_file.write("//input : input_%s:16\n"%i)
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for i in outputs:
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output_file.write("//output : output_%s:16\n"%i)
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output_file.write("//source_file : %s\n"%input_file)
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output_file.write("///%s\n"%"".join(["=" for i in name]))
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output_file.write("///\n")
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output_file.write("///*Created by C2CHIP*\n\n")
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output_file.write("// Register Allocation\n")
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output_file.write("// ===================\n")
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output_file.write("// %s %s %s \n"%("Register".center(20), "Name".center(20), "Size".center(20)))
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for register, definition in registers.iteritems():
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register_name, size = definition
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output_file.write("// %s %s %s \n"%(str(register).center(20), register_name.center(20), str(size).center(20)))
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output_file.write(" \n`timescale 1ns/1ps\n")
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output_file.write("module %s"%name)
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all_ports = [name for name, size in inports + outports]
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if all_ports:
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output_file.write("(")
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output_file.write(",".join(all_ports))
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output_file.write(");\n")
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else:
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output_file.write(";\n")
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output_file.write(" integer file_count;\n")
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if enable_adder:
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generate_adder_signals(output_file)
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if enable_multiplier:
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generate_multiplier_signals(output_file)
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if enable_divider:
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generate_divider_signals(output_file)
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if enable_int_to_float:
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generate_int_to_float_signals(output_file)
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if enable_float_to_int:
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generate_float_to_int_signals(output_file)
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output_file.write(" real fp_value;\n")
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if enable_adder or enable_multiplier or enable_divider or enable_int_to_float or enable_float_to_int:
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output_file.write(" parameter wait_go = 3'd0,\n")
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output_file.write(" write_a = 3'd1,\n")
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output_file.write(" write_b = 3'd2,\n")
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output_file.write(" read_z = 3'd3,\n")
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output_file.write(" wait_next = 3'd4;\n")
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input_files = dict(zip(input_files, ["input_file_%s"%i for i, j in enumerate(input_files)]))
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for i in input_files.values():
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output_file.write(" integer %s;\n"%i)
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output_files = dict(zip(output_files, ["output_file_%s"%i for i, j in enumerate(output_files)]))
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for i in output_files.values():
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output_file.write(" integer %s;\n"%i)
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def write_declaration(object_type, name, size, value=None):
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if size == 1:
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output_file.write(object_type)
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output_file.write(name)
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if value is not None:
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output_file.write("= %s'd%s"%(size,value))
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output_file.write(";\n")
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else:
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output_file.write(object_type)
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output_file.write("[%i:0]"%(size-1))
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output_file.write(" ")
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output_file.write(name)
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if value is not None:
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output_file.write("= %s'd%s"%(size,value))
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output_file.write(";\n")
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for name, size in inports:
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write_declaration(" input ", name, size)
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for name, size in outports:
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write_declaration(" output ", name, size)
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for name, size in signals:
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write_declaration(" reg ", name, size)
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memory_size_2 = int(memory_size_2)
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memory_size_4 = int(memory_size_4)
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if memory_size_2:
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output_file.write(" reg [15:0] memory_2 [%i:0];\n"%(memory_size_2-1))
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if memory_size_4:
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output_file.write(" reg [31:0] memory_4 [%i:0];\n"%(memory_size_4-1))
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jondawson |
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4 |
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#generate clock and reset in testbench mode
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if testbench:
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jondawson |
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4 |
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output_file.write("\n //////////////////////////////////////////////////////////////////////////////\n")
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output_file.write(" // CLOCK AND RESET GENERATION \n")
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output_file.write(" // \n")
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output_file.write(" // This file was generated in test bench mode. In this mode, the verilog \n")
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output_file.write(" // output file can be executed directly within a verilog simulator. \n")
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output_file.write(" // In test bench mode, a simulated clock and reset signal are generated within\n")
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output_file.write(" // the output file. \n")
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output_file.write(" // Verilog files generated in testbecnch mode are not suitable for synthesis, \n")
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output_file.write(" // or for instantiation within a larger design.\n")
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jondawson |
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output_file.write(" \n initial\n")
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output_file.write(" begin\n")
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output_file.write(" rst <= 1'b1;\n")
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output_file.write(" #50 rst <= 1'b0;\n")
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output_file.write(" end\n\n")
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jondawson |
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4 |
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output_file.write(" \n initial\n")
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output_file.write(" begin\n")
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output_file.write(" clk <= 1'b0;\n")
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output_file.write(" while (1) begin\n")
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output_file.write(" #5 clk <= ~clk;\n")
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output_file.write(" end\n")
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output_file.write(" end\n\n")
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2 |
jondawson |
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4 |
jondawson |
#Instance Floating Point Arithmetic
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if enable_adder or enable_multiplier or enable_divider or enable_int_to_float or enable_float_to_int:
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2 |
jondawson |
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4 |
jondawson |
output_file.write("\n //////////////////////////////////////////////////////////////////////////////\n")
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output_file.write(" // Floating Point Arithmetic \n")
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output_file.write(" // \n")
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output_file.write(" // Generate IEEE 754 single precision divider, adder and multiplier \n")
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output_file.write(" // \n")
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2 |
jondawson |
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4 |
jondawson |
if enable_divider:
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connect_divider(output_file)
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if enable_multiplier:
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connect_multiplier(output_file)
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if enable_adder:
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connect_adder(output_file)
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if enable_int_to_float:
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connect_int_to_float(output_file)
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if enable_float_to_int:
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connect_float_to_int(output_file)
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2 |
jondawson |
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4 |
jondawson |
#Generate a state machine to execute the instructions
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binary_operators = ["+", "-", "*", "/", "|", "&", "^", "<<", ">>", "<",">", ">=",
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"<=", "==", "!="]
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| 310 |
2 |
jondawson |
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4 |
jondawson |
if initialize_memory and (memory_content_2 or memory_content_4):
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2 |
jondawson |
|
| 314 |
4 |
jondawson |
output_file.write("\n //////////////////////////////////////////////////////////////////////////////\n")
|
| 315 |
|
|
output_file.write(" // MEMORY INITIALIZATION \n")
|
| 316 |
|
|
output_file.write(" // \n")
|
| 317 |
|
|
output_file.write(" // In order to reduce program size, array contents have been stored into \n")
|
| 318 |
|
|
output_file.write(" // memory at initialization. In an FPGA, this will result in the memory being \n")
|
| 319 |
|
|
output_file.write(" // initialized when the FPGA configures. \n")
|
| 320 |
|
|
output_file.write(" // Memory will not be re-initialized at reset. \n")
|
| 321 |
|
|
output_file.write(" // Dissable this behaviour using the no_initialize_memory switch \n")
|
| 322 |
2 |
jondawson |
|
| 323 |
4 |
jondawson |
output_file.write(" \n initial\n")
|
| 324 |
|
|
output_file.write(" begin\n")
|
| 325 |
|
|
for location, content in memory_content_2.iteritems():
|
| 326 |
|
|
output_file.write(" memory_2[%s] = %s;\n"%(location, content))
|
| 327 |
|
|
for location, content in memory_content_4.iteritems():
|
| 328 |
|
|
output_file.write(" memory_4[%s] = %s;\n"%(location, content))
|
| 329 |
|
|
output_file.write(" end\n\n")
|
| 330 |
2 |
jondawson |
|
| 331 |
4 |
jondawson |
if input_files or output_files:
|
| 332 |
2 |
jondawson |
|
| 333 |
4 |
jondawson |
output_file.write("\n //////////////////////////////////////////////////////////////////////////////\n")
|
| 334 |
|
|
output_file.write(" // OPEN FILES \n")
|
| 335 |
|
|
output_file.write(" // \n")
|
| 336 |
|
|
output_file.write(" // Open all files used at the start of the process \n")
|
| 337 |
2 |
jondawson |
|
| 338 |
4 |
jondawson |
output_file.write(" \n initial\n")
|
| 339 |
|
|
output_file.write(" begin\n")
|
| 340 |
|
|
for file_name, file_ in input_files.iteritems():
|
| 341 |
|
|
output_file.write(" %s = $fopenr(\"%s\");\n"%(file_, file_name))
|
| 342 |
|
|
for file_name, file_ in output_files.iteritems():
|
| 343 |
|
|
output_file.write(" %s = $fopen(\"%s\");\n"%(file_, file_name))
|
| 344 |
|
|
output_file.write(" end\n\n")
|
| 345 |
2 |
jondawson |
|
| 346 |
4 |
jondawson |
output_file.write("\n //////////////////////////////////////////////////////////////////////////////\n")
|
| 347 |
|
|
output_file.write(" // FSM IMPLEMENTAION OF C PROCESS \n")
|
| 348 |
|
|
output_file.write(" // \n")
|
| 349 |
|
|
output_file.write(" // This section of the file contains a Finite State Machine (FSM) implementing\n")
|
| 350 |
|
|
output_file.write(" // the C process. In general execution is sequential, but the compiler will \n")
|
| 351 |
|
|
output_file.write(" // attempt to execute instructions in parallel if the instruction dependencies\n")
|
| 352 |
|
|
output_file.write(" // allow. Further concurrency can be achieved by executing multiple C \n")
|
| 353 |
|
|
output_file.write(" // processes concurrently within the device. \n")
|
| 354 |
2 |
jondawson |
|
| 355 |
4 |
jondawson |
output_file.write(" \n always @(posedge clk)\n")
|
| 356 |
|
|
output_file.write(" begin\n\n")
|
| 357 |
2 |
jondawson |
|
| 358 |
4 |
jondawson |
if memory_size_2:
|
| 359 |
|
|
output_file.write(" //implement memory for 2 byte x n arrays\n")
|
| 360 |
|
|
output_file.write(" if (write_enable_2 == 1'b1) begin\n")
|
| 361 |
|
|
output_file.write(" memory_2[address_2] <= data_in_2;\n")
|
| 362 |
|
|
output_file.write(" end\n")
|
| 363 |
|
|
output_file.write(" data_out_2 <= memory_2[address_2];\n")
|
| 364 |
|
|
output_file.write(" write_enable_2 <= 1'b0;\n\n")
|
| 365 |
2 |
jondawson |
|
| 366 |
4 |
jondawson |
if memory_size_4:
|
| 367 |
|
|
output_file.write(" //implement memory for 4 byte x n arrays\n")
|
| 368 |
|
|
output_file.write(" if (write_enable_4 == 1'b1) begin\n")
|
| 369 |
|
|
output_file.write(" memory_4[address_4] <= data_in_4;\n")
|
| 370 |
|
|
output_file.write(" end\n")
|
| 371 |
|
|
output_file.write(" data_out_4 <= memory_4[address_4];\n")
|
| 372 |
|
|
output_file.write(" write_enable_4 <= 1'b0;\n\n")
|
| 373 |
2 |
jondawson |
|
| 374 |
4 |
jondawson |
output_file.write(" //implement timer\n")
|
| 375 |
|
|
output_file.write(" timer <= 16'h0000;\n\n")
|
| 376 |
|
|
output_file.write(" case(program_counter)\n\n")
|
| 377 |
2 |
jondawson |
|
| 378 |
4 |
jondawson |
#A frame is executed in each state
|
| 379 |
|
|
for location, frame in enumerate(frames):
|
| 380 |
|
|
output_file.write(" 16'd%s:\n"%to_gray(location))
|
| 381 |
|
|
output_file.write(" begin\n")
|
| 382 |
|
|
output_file.write(" program_counter <= 16'd%s;\n"%to_gray(location+1))
|
| 383 |
|
|
for instruction in frame:
|
| 384 |
2 |
jondawson |
|
| 385 |
4 |
jondawson |
if instruction["op"] == "literal":
|
| 386 |
|
|
output_file.write(
|
| 387 |
|
|
" register_%s <= %s;\n"%(
|
| 388 |
|
|
instruction["dest"],
|
| 389 |
|
|
instruction["literal"]))
|
| 390 |
2 |
jondawson |
|
| 391 |
4 |
jondawson |
elif instruction["op"] == "move":
|
| 392 |
|
|
output_file.write(
|
| 393 |
|
|
" register_%s <= register_%s;\n"%(
|
| 394 |
|
|
instruction["dest"],
|
| 395 |
|
|
instruction["src"]))
|
| 396 |
2 |
jondawson |
|
| 397 |
4 |
jondawson |
elif instruction["op"] in ["~"]:
|
| 398 |
|
|
output_file.write(
|
| 399 |
|
|
" register_%s <= ~register_%s;\n"%(
|
| 400 |
|
|
instruction["dest"],
|
| 401 |
|
|
instruction["src"]))
|
| 402 |
2 |
jondawson |
|
| 403 |
4 |
jondawson |
elif instruction["op"] in ["int_to_float"]:
|
| 404 |
|
|
output_file.write(" int_to <= register_%s;\n"%(instruction["src"]))
|
| 405 |
|
|
output_file.write(" register_%s <= to_float;\n"%(instruction["dest"]))
|
| 406 |
|
|
output_file.write(" program_counter <= %s;\n"%to_gray(location))
|
| 407 |
|
|
output_file.write(" int_to_float_go <= 1;\n")
|
| 408 |
|
|
output_file.write(" if (int_to_float_done) begin\n")
|
| 409 |
|
|
output_file.write(" int_to_float_go <= 0;\n")
|
| 410 |
|
|
output_file.write(" program_counter <= 16'd%s;\n"%to_gray(location+1))
|
| 411 |
|
|
output_file.write(" end\n")
|
| 412 |
2 |
jondawson |
|
| 413 |
4 |
jondawson |
elif instruction["op"] in ["float_to_int"]:
|
| 414 |
|
|
output_file.write(" float_to <= register_%s;\n"%(instruction["src"]))
|
| 415 |
|
|
output_file.write(" register_%s <= to_int;\n"%(instruction["dest"]))
|
| 416 |
|
|
output_file.write(" program_counter <= %s;\n"%to_gray(location))
|
| 417 |
|
|
output_file.write(" float_to_int_go <= 1;\n")
|
| 418 |
|
|
output_file.write(" if (float_to_int_done) begin\n")
|
| 419 |
|
|
output_file.write(" float_to_int_go <= 0;\n")
|
| 420 |
|
|
output_file.write(" program_counter <= 16'd%s;\n"%to_gray(location+1))
|
| 421 |
|
|
output_file.write(" end\n")
|
| 422 |
2 |
jondawson |
|
| 423 |
4 |
jondawson |
elif instruction["op"] in binary_operators and "left" in instruction:
|
| 424 |
|
|
if ("type" in instruction and
|
| 425 |
|
|
instruction["type"] == "float" and
|
| 426 |
|
|
instruction["op"] in ["+", "-", "*", "/"]):
|
| 427 |
2 |
jondawson |
|
| 428 |
4 |
jondawson |
if instruction["op"] == "+":
|
| 429 |
|
|
output_file.write(" adder_a <= %s;\n"%(instruction["left"]))
|
| 430 |
|
|
output_file.write(" adder_b <= register_%s;\n"%(instruction["src"]))
|
| 431 |
|
|
output_file.write(" register_%s <= adder_z;\n"%(instruction["dest"]))
|
| 432 |
|
|
output_file.write(" program_counter <= %s;\n"%to_gray(location))
|
| 433 |
|
|
output_file.write(" adder_go <= 1;\n")
|
| 434 |
|
|
output_file.write(" if (adder_done) begin\n")
|
| 435 |
|
|
output_file.write(" adder_go <= 0;\n")
|
| 436 |
|
|
output_file.write(" program_counter <= 16'd%s;\n"%to_gray(location+1))
|
| 437 |
|
|
output_file.write(" end\n")
|
| 438 |
|
|
if instruction["op"] == "-":
|
| 439 |
|
|
output_file.write(" adder_a <= %s;\n"%(instruction["left"]))
|
| 440 |
|
|
output_file.write(" adder_b <= {~register_%s[31], register_%s[30:0]};\n"%(
|
| 441 |
|
|
instruction["src"],
|
| 442 |
|
|
instruction["src"]))
|
| 443 |
|
|
output_file.write(" register_%s <= adder_z;\n"%(instruction["dest"]))
|
| 444 |
|
|
output_file.write(" program_counter <= %s;\n"%to_gray(location))
|
| 445 |
|
|
output_file.write(" adder_go <= 1;\n")
|
| 446 |
|
|
output_file.write( " if (adder_done) begin\n")
|
| 447 |
|
|
output_file.write(" adder_go <= 0;\n")
|
| 448 |
|
|
output_file.write(" program_counter <= 16'd%s;\n"%to_gray(location+1))
|
| 449 |
|
|
output_file.write(" end\n")
|
| 450 |
|
|
elif instruction["op"] == "*":
|
| 451 |
|
|
output_file.write(" multiplier_a <= %s;\n"%(instruction["left"]))
|
| 452 |
|
|
output_file.write(" multiplier_b <= register_%s;\n"%(instruction["src"]))
|
| 453 |
|
|
output_file.write(" register_%s <= multiplier_z;\n"%(instruction["dest"]))
|
| 454 |
|
|
output_file.write(" program_counter <= %s;\n"%to_gray(location))
|
| 455 |
|
|
output_file.write(" multiplier_go <= 1;\n")
|
| 456 |
|
|
output_file.write( " if (multiplier_done) begin\n")
|
| 457 |
|
|
output_file.write(" multiplier_go <= 0;\n")
|
| 458 |
|
|
output_file.write(" program_counter <= 16'd%s;\n"%to_gray(location+1))
|
| 459 |
|
|
output_file.write(" end\n")
|
| 460 |
|
|
elif instruction["op"] == "/":
|
| 461 |
|
|
output_file.write(" divider_a <= %s;\n"%(instruction["left"]))
|
| 462 |
|
|
output_file.write(" divider_b <= register_%s;\n"%(instruction["src"]))
|
| 463 |
|
|
output_file.write(" register_%s <= divider_z;\n"%(instruction["dest"]))
|
| 464 |
|
|
output_file.write(" program_counter <= %s;\n"%to_gray(location))
|
| 465 |
|
|
output_file.write(" divider_go <= 1;\n")
|
| 466 |
|
|
output_file.write(" if (divider_done) begin\n")
|
| 467 |
|
|
output_file.write(" divider_go <= 0;\n")
|
| 468 |
|
|
output_file.write(" program_counter <= 16'd%s;\n"%to_gray(location+1))
|
| 469 |
|
|
output_file.write(" end\n")
|
| 470 |
|
|
elif not instruction["signed"]:
|
| 471 |
|
|
output_file.write(
|
| 472 |
|
|
" register_%s <= %s %s $unsigned(register_%s);\n"%(
|
| 473 |
|
|
instruction["dest"],
|
| 474 |
|
|
instruction["left"],
|
| 475 |
|
|
instruction["op"],
|
| 476 |
|
|
instruction["src"]))
|
| 477 |
|
|
else:
|
| 478 |
|
|
#Verilog uses >>> as an arithmetic right shift
|
| 479 |
|
|
if instruction["op"] == ">>":
|
| 480 |
|
|
instruction["op"] = ">>>"
|
| 481 |
|
|
output_file.write(
|
| 482 |
|
|
" register_%s <= %s %s $signed(register_%s);\n"%(
|
| 483 |
|
|
instruction["dest"],
|
| 484 |
|
|
sign_extend(instruction["left"], instruction["size"]),
|
| 485 |
|
|
instruction["op"],
|
| 486 |
|
|
instruction["src"]))
|
| 487 |
2 |
jondawson |
|
| 488 |
4 |
jondawson |
elif instruction["op"] in binary_operators and "right" in instruction:
|
| 489 |
|
|
if ("type" in instruction and
|
| 490 |
|
|
instruction["type"] == "float" and
|
| 491 |
|
|
instruction["op"] in ["+", "-", "*", "/"]):
|
| 492 |
2 |
jondawson |
|
| 493 |
4 |
jondawson |
if instruction["op"] == "+":
|
| 494 |
|
|
output_file.write(" adder_b <= %s;\n"%(instruction["right"]))
|
| 495 |
|
|
output_file.write(" adder_a <= register_%s;\n"%(instruction["src"]))
|
| 496 |
|
|
output_file.write(" register_%s <= adder_z;\n"%(instruction["dest"]))
|
| 497 |
|
|
output_file.write(" program_counter <= %s;\n"%to_gray(location))
|
| 498 |
|
|
output_file.write(" adder_go <= 1;\n")
|
| 499 |
|
|
output_file.write(" if (adder_done) begin\n")
|
| 500 |
|
|
output_file.write(" adder_go <= 0;\n")
|
| 501 |
|
|
output_file.write(" program_counter <= 16'd%s;\n"%to_gray(location+1))
|
| 502 |
|
|
output_file.write(" end\n")
|
| 503 |
|
|
if instruction["op"] == "-":
|
| 504 |
|
|
output_file.write(" adder_b <= %s;\n"%(
|
| 505 |
|
|
instruction["right"] ^ 0x80000000))
|
| 506 |
|
|
output_file.write(" adder_a <= register_%s;\n"%(
|
| 507 |
|
|
instruction["src"]))
|
| 508 |
|
|
output_file.write(" register_%s <= adder_z;\n"%(instruction["dest"]))
|
| 509 |
|
|
output_file.write(" program_counter <= %s;\n"%to_gray(location))
|
| 510 |
|
|
output_file.write(" adder_go <= 1;\n")
|
| 511 |
|
|
output_file.write(" if (adder_done) begin\n")
|
| 512 |
|
|
output_file.write(" adder_go <= 0;\n")
|
| 513 |
|
|
output_file.write(" program_counter <= 16'd%s;\n"%to_gray(location+1))
|
| 514 |
|
|
output_file.write(" end\n")
|
| 515 |
|
|
elif instruction["op"] == "*":
|
| 516 |
|
|
output_file.write(" multiplier_b <= %s;\n"%(instruction["right"]))
|
| 517 |
|
|
output_file.write(" multiplier_a <= register_%s;\n"%(instruction["src"]))
|
| 518 |
|
|
output_file.write(" register_%s <= multiplier_z;\n"%(instruction["dest"]))
|
| 519 |
|
|
output_file.write(" program_counter <= %s;\n"%to_gray(location))
|
| 520 |
|
|
output_file.write(" multiplier_go <= 1;\n")
|
| 521 |
|
|
output_file.write(" if (multiplier_done) begin\n")
|
| 522 |
|
|
output_file.write(" multiplier_go <= 0;\n")
|
| 523 |
|
|
output_file.write(" program_counter <= 16'd%s;\n"%to_gray(location+1))
|
| 524 |
|
|
output_file.write(" end\n")
|
| 525 |
|
|
elif instruction["op"] == "/":
|
| 526 |
|
|
output_file.write(" divider_b <= %s;\n"%(instruction["right"]))
|
| 527 |
|
|
output_file.write(" divider_a <= register_%s;\n"%(instruction["src"]))
|
| 528 |
|
|
output_file.write(" register_%s <= divider_z;\n"%(instruction["dest"]))
|
| 529 |
|
|
output_file.write(" program_counter <= %s;\n"%to_gray(location))
|
| 530 |
|
|
output_file.write(" divider_go <= 1;\n")
|
| 531 |
|
|
output_file.write(" if (divider_done) begin\n")
|
| 532 |
|
|
output_file.write(" divider_go <= 0;\n")
|
| 533 |
|
|
output_file.write(" program_counter <= 16'd%s;\n"%to_gray(location+1))
|
| 534 |
|
|
output_file.write(" end\n")
|
| 535 |
2 |
jondawson |
|
| 536 |
4 |
jondawson |
elif not instruction["signed"]:
|
| 537 |
|
|
output_file.write(
|
| 538 |
|
|
" register_%s <= $unsigned(register_%s) %s %s;\n"%(
|
| 539 |
|
|
instruction["dest"],
|
| 540 |
|
|
instruction["src"],
|
| 541 |
|
|
instruction["op"],
|
| 542 |
|
|
instruction["right"]))
|
| 543 |
|
|
else:
|
| 544 |
|
|
#Verilog uses >>> as an arithmetic right shift
|
| 545 |
|
|
if instruction["op"] == ">>":
|
| 546 |
|
|
instruction["op"] = ">>>"
|
| 547 |
|
|
output_file.write(
|
| 548 |
|
|
" register_%s <= $signed(register_%s) %s %s;\n"%(
|
| 549 |
|
|
instruction["dest"],
|
| 550 |
|
|
instruction["src"],
|
| 551 |
|
|
instruction["op"],
|
| 552 |
|
|
sign_extend(instruction["right"], instruction["size"])))
|
| 553 |
2 |
jondawson |
|
| 554 |
4 |
jondawson |
elif instruction["op"] in binary_operators:
|
| 555 |
|
|
if ("type" in instruction and
|
| 556 |
|
|
instruction["type"] == "float" and
|
| 557 |
|
|
instruction["op"] in ["+", "-", "*", "/"]):
|
| 558 |
2 |
jondawson |
|
| 559 |
4 |
jondawson |
if instruction["op"] == "+":
|
| 560 |
|
|
output_file.write(" adder_a <= register_%s;\n"%(instruction["src"]))
|
| 561 |
|
|
output_file.write(" adder_b <= register_%s;\n"%(instruction["srcb"]))
|
| 562 |
|
|
output_file.write(" register_%s <= adder_z;\n"%(instruction["dest"]))
|
| 563 |
|
|
output_file.write(" program_counter <= %s;\n"%to_gray(location))
|
| 564 |
|
|
output_file.write(" adder_go <= 1;\n")
|
| 565 |
|
|
output_file.write(" if (adder_done) begin\n")
|
| 566 |
|
|
output_file.write(" adder_go <= 0;\n")
|
| 567 |
|
|
output_file.write(" program_counter <= 16'd%s;\n"%to_gray(location+1))
|
| 568 |
|
|
output_file.write(" end\n")
|
| 569 |
|
|
if instruction["op"] == "-":
|
| 570 |
|
|
output_file.write(" adder_a <= register_%s;\n"%(instruction["src"]))
|
| 571 |
|
|
output_file.write(" adder_b <= {~register_%s[31], register_%s[30:0]};\n"%(
|
| 572 |
|
|
instruction["srcb"],
|
| 573 |
|
|
instruction["srcb"]))
|
| 574 |
|
|
output_file.write(" register_%s <= adder_z;\n"%(instruction["dest"]))
|
| 575 |
|
|
output_file.write(" program_counter <= %s;\n"%to_gray(location))
|
| 576 |
|
|
output_file.write(" adder_go <= 1;\n")
|
| 577 |
|
|
output_file.write(" if (adder_done) begin\n")
|
| 578 |
|
|
output_file.write(" adder_go <= 0;\n")
|
| 579 |
|
|
output_file.write(" program_counter <= 16'd%s;\n"%to_gray(location+1))
|
| 580 |
|
|
output_file.write(" end\n")
|
| 581 |
|
|
elif instruction["op"] == "*":
|
| 582 |
|
|
output_file.write(" multiplier_a <= register_%s;\n"%(instruction["src"]))
|
| 583 |
|
|
output_file.write(" multiplier_b <= register_%s;\n"%(instruction["srcb"]))
|
| 584 |
|
|
output_file.write(" register_%s <= multiplier_z;\n"%(instruction["dest"]))
|
| 585 |
|
|
output_file.write(" program_counter <= %s;\n"%to_gray(location))
|
| 586 |
|
|
output_file.write(" multiplier_go <= 1;\n")
|
| 587 |
|
|
output_file.write(" if (multiplier_done) begin\n")
|
| 588 |
|
|
output_file.write(" multiplier_go <= 0;\n")
|
| 589 |
|
|
output_file.write(" program_counter <= 16'd%s;\n"%to_gray(location+1))
|
| 590 |
|
|
output_file.write(" end\n")
|
| 591 |
|
|
elif instruction["op"] == "/":
|
| 592 |
|
|
output_file.write(" divider_a <= register_%s;\n"%(instruction["src"]))
|
| 593 |
|
|
output_file.write(" divider_b <= register_%s;\n"%(instruction["srcb"]))
|
| 594 |
|
|
output_file.write(" register_%s <= divider_z;\n"%(instruction["dest"]))
|
| 595 |
|
|
output_file.write(" program_counter <= %s;\n"%to_gray(location))
|
| 596 |
|
|
output_file.write(" divider_go <= 1;\n")
|
| 597 |
|
|
output_file.write(" if (divider_done) begin\n")
|
| 598 |
|
|
output_file.write(" divider_go <= 0;\n")
|
| 599 |
|
|
output_file.write(" program_counter <= 16'd%s;\n"%to_gray(location+1))
|
| 600 |
|
|
output_file.write(" end\n")
|
| 601 |
2 |
jondawson |
|
| 602 |
4 |
jondawson |
elif not instruction["signed"]:
|
| 603 |
|
|
output_file.write(
|
| 604 |
|
|
" register_%s <= $unsigned(register_%s) %s $unsigned(register_%s);\n"%(
|
| 605 |
|
|
instruction["dest"],
|
| 606 |
|
|
instruction["src"],
|
| 607 |
|
|
instruction["op"],
|
| 608 |
|
|
instruction["srcb"]))
|
| 609 |
|
|
else:
|
| 610 |
|
|
#Verilog uses >>> as an arithmetic right shift
|
| 611 |
|
|
if instruction["op"] == ">>":
|
| 612 |
|
|
instruction["op"] = ">>>"
|
| 613 |
|
|
output_file.write(
|
| 614 |
|
|
" register_%s <= $signed(register_%s) %s $signed(register_%s);\n"%(
|
| 615 |
|
|
instruction["dest"],
|
| 616 |
|
|
instruction["src"],
|
| 617 |
|
|
instruction["op"],
|
| 618 |
|
|
instruction["srcb"]))
|
| 619 |
2 |
jondawson |
|
| 620 |
4 |
jondawson |
elif instruction["op"] == "jmp_if_false":
|
| 621 |
|
|
output_file.write(" if (register_%s == 0)\n"%(instruction["src"]));
|
| 622 |
|
|
output_file.write(" program_counter <= %s;\n"%to_gray(instruction["label"]&0xffff))
|
| 623 |
2 |
jondawson |
|
| 624 |
4 |
jondawson |
elif instruction["op"] == "jmp_if_true":
|
| 625 |
|
|
output_file.write(" if (register_%s != 0)\n"%(instruction["src"]));
|
| 626 |
|
|
output_file.write(" program_counter <= 16'd%s;\n"%to_gray(instruction["label"]&0xffff))
|
| 627 |
2 |
jondawson |
|
| 628 |
4 |
jondawson |
elif instruction["op"] == "jmp_and_link":
|
| 629 |
|
|
output_file.write(" program_counter <= 16'd%s;\n"%to_gray(instruction["label"]&0xffff))
|
| 630 |
|
|
output_file.write(" register_%s <= 16'd%s;\n"%(
|
| 631 |
|
|
instruction["dest"], to_gray((location+1)&0xffff)))
|
| 632 |
2 |
jondawson |
|
| 633 |
4 |
jondawson |
elif instruction["op"] == "jmp_to_reg":
|
| 634 |
|
|
output_file.write(
|
| 635 |
|
|
" program_counter <= register_%s;\n"%instruction["src"])
|
| 636 |
2 |
jondawson |
|
| 637 |
4 |
jondawson |
elif instruction["op"] == "goto":
|
| 638 |
|
|
output_file.write(" program_counter <= 16'd%s;\n"%(to_gray(instruction["label"]&0xffff)))
|
| 639 |
2 |
jondawson |
|
| 640 |
4 |
jondawson |
elif instruction["op"] == "file_read":
|
| 641 |
|
|
output_file.write(" file_count = $fscanf(%s, \"%%d\\n\", register_%s);\n"%(
|
| 642 |
|
|
input_files[instruction["file_name"]], instruction["dest"]))
|
| 643 |
2 |
jondawson |
|
| 644 |
4 |
jondawson |
elif instruction["op"] == "file_write":
|
| 645 |
|
|
if instruction["type"] == "float":
|
| 646 |
|
|
output_file.write(' fp_value = (register_%s[31]?-1.0:1.0) *\n'%instruction["src"])
|
| 647 |
|
|
output_file.write(' (2.0 ** (register_%s[30:23]-127.0)) *\n'%instruction["src"])
|
| 648 |
|
|
output_file.write(' ({1\'d1, register_%s[22:0]} / (2.0**23));\n'%instruction["src"])
|
| 649 |
2 |
jondawson |
|
| 650 |
4 |
jondawson |
output_file.write(' $fdisplay(%s, fp_value);\n'%(
|
| 651 |
|
|
output_files[instruction["file_name"]]))
|
| 652 |
|
|
else:
|
| 653 |
|
|
output_file.write(" $fdisplay(%s, \"%%d\", register_%s);\n"%(
|
| 654 |
|
|
output_files[instruction["file_name"]], instruction["src"]))
|
| 655 |
2 |
jondawson |
|
| 656 |
4 |
jondawson |
elif instruction["op"] == "read":
|
| 657 |
|
|
output_file.write(" register_%s <= input_%s;\n"%(
|
| 658 |
|
|
instruction["dest"], instruction["input"]))
|
| 659 |
|
|
output_file.write(" program_counter <= %s;\n"%to_gray(location))
|
| 660 |
|
|
output_file.write(" s_input_%s_ack <= 1'b1;\n"%instruction["input"])
|
| 661 |
|
|
output_file.write( " if (s_input_%s_ack == 1'b1 && input_%s_stb == 1'b1) begin\n"%(
|
| 662 |
|
|
instruction["input"],
|
| 663 |
|
|
instruction["input"]
|
| 664 |
|
|
))
|
| 665 |
|
|
output_file.write(" s_input_%s_ack <= 1'b0;\n"%instruction["input"])
|
| 666 |
|
|
output_file.write(" program_counter <= 16'd%s;\n"%to_gray(location+1))
|
| 667 |
|
|
output_file.write(" end\n")
|
| 668 |
2 |
jondawson |
|
| 669 |
4 |
jondawson |
elif instruction["op"] == "ready":
|
| 670 |
|
|
output_file.write(" register_%s <= 0;\n"%instruction["dest"])
|
| 671 |
|
|
output_file.write(" register_%s[0] <= input_%s_stb;\n"%(
|
| 672 |
|
|
instruction["dest"], instruction["input"]))
|
| 673 |
2 |
jondawson |
|
| 674 |
4 |
jondawson |
elif instruction["op"] == "write":
|
| 675 |
|
|
output_file.write(" s_output_%s <= register_%s;\n"%(
|
| 676 |
|
|
instruction["output"], instruction["src"]))
|
| 677 |
|
|
output_file.write(" program_counter <= %s;\n"%to_gray(location))
|
| 678 |
|
|
output_file.write(" s_output_%s_stb <= 1'b1;\n"%instruction["output"])
|
| 679 |
|
|
output_file.write(
|
| 680 |
|
|
" if (s_output_%s_stb == 1'b1 && output_%s_ack == 1'b1) begin\n"%(
|
| 681 |
|
|
instruction["output"],
|
| 682 |
|
|
instruction["output"]
|
| 683 |
|
|
))
|
| 684 |
|
|
output_file.write(" s_output_%s_stb <= 1'b0;\n"%instruction["output"])
|
| 685 |
|
|
output_file.write(" program_counter <= %s;\n"%to_gray(location+1))
|
| 686 |
|
|
output_file.write(" end\n")
|
| 687 |
2 |
jondawson |
|
| 688 |
4 |
jondawson |
elif instruction["op"] == "memory_read_request":
|
| 689 |
|
|
output_file.write(
|
| 690 |
|
|
" address_%s <= register_%s;\n"%(
|
| 691 |
|
|
instruction["element_size"],
|
| 692 |
|
|
instruction["src"]))
|
| 693 |
2 |
jondawson |
|
| 694 |
4 |
jondawson |
elif instruction["op"] == "memory_read_wait":
|
| 695 |
|
|
pass
|
| 696 |
|
|
|
| 697 |
|
|
elif instruction["op"] == "memory_read":
|
| 698 |
|
|
output_file.write(
|
| 699 |
|
|
" register_%s <= data_out_%s;\n"%(
|
| 700 |
|
|
instruction["dest"],
|
| 701 |
|
|
instruction["element_size"]))
|
| 702 |
|
|
|
| 703 |
|
|
elif instruction["op"] == "memory_write":
|
| 704 |
|
|
output_file.write(" address_%s <= register_%s;\n"%(
|
| 705 |
|
|
instruction["element_size"],
|
| 706 |
|
|
instruction["src"]))
|
| 707 |
|
|
output_file.write(" data_in_%s <= register_%s;\n"%(
|
| 708 |
|
|
instruction["element_size"],
|
| 709 |
|
|
instruction["srcb"]))
|
| 710 |
|
|
output_file.write(" write_enable_%s <= 1'b1;\n"%(
|
| 711 |
|
|
instruction["element_size"]))
|
| 712 |
|
|
|
| 713 |
|
|
elif instruction["op"] == "memory_write_literal":
|
| 714 |
|
|
output_file.write(" address_%s <= 16'd%s;\n"%(
|
| 715 |
|
|
instruction["element_size"],
|
| 716 |
|
|
instruction["address"]))
|
| 717 |
|
|
output_file.write(" data_in_%s <= %s;\n"%(
|
| 718 |
|
|
instruction["element_size"],
|
| 719 |
|
|
instruction["value"]))
|
| 720 |
|
|
output_file.write(" write_enable_%s <= 1'b1;\n"%(
|
| 721 |
|
|
instruction["element_size"]))
|
| 722 |
|
|
|
| 723 |
|
|
elif instruction["op"] == "assert":
|
| 724 |
|
|
output_file.write( " if (register_%s == 0) begin\n"%instruction["src"])
|
| 725 |
|
|
output_file.write( " $display(\"Assertion failed at line: %s in file: %s\");\n"%(
|
| 726 |
|
|
instruction["line"],
|
| 727 |
|
|
instruction["file"]))
|
| 728 |
|
|
output_file.write( " $finish_and_return(1);\n")
|
| 729 |
|
|
output_file.write( " end\n")
|
| 730 |
|
|
|
| 731 |
|
|
elif instruction["op"] == "wait_clocks":
|
| 732 |
|
|
output_file.write(" if (timer < register_%s) begin\n"%instruction["src"])
|
| 733 |
|
|
output_file.write(" program_counter <= program_counter;\n")
|
| 734 |
|
|
output_file.write(" timer <= timer+1;\n")
|
| 735 |
|
|
output_file.write(" end\n")
|
| 736 |
|
|
|
| 737 |
|
|
elif instruction["op"] == "report":
|
| 738 |
|
|
if instruction["type"] == "float":
|
| 739 |
|
|
output_file.write(' fp_value = (register_%s[31]?-1.0:1.0) *\n'%instruction["src"])
|
| 740 |
|
|
output_file.write(' (2.0 ** (register_%s[30:23]-127.0)) *\n'%instruction["src"])
|
| 741 |
|
|
output_file.write(' ({1\'d1, register_%s[22:0]} / (2.0**23));\n'%instruction["src"])
|
| 742 |
|
|
|
| 743 |
|
|
output_file.write(' $display ("%%f (report at line: %s in file: %s)", fp_value);\n'%(
|
| 744 |
|
|
instruction["line"],
|
| 745 |
|
|
instruction["file"]))
|
| 746 |
|
|
elif not instruction["signed"]:
|
| 747 |
|
|
output_file.write(
|
| 748 |
|
|
' $display ("%%d (report at line: %s in file: %s)", $unsigned(register_%s));\n'%(
|
| 749 |
|
|
instruction["line"],
|
| 750 |
|
|
instruction["file"],
|
| 751 |
|
|
instruction["src"]))
|
| 752 |
|
|
else:
|
| 753 |
|
|
output_file.write(
|
| 754 |
|
|
' $display ("%%d (report at line: %s in file: %s)", $signed(register_%s));\n'%(
|
| 755 |
|
|
instruction["line"],
|
| 756 |
|
|
instruction["file"],
|
| 757 |
|
|
instruction["src"]))
|
| 758 |
|
|
|
| 759 |
|
|
elif instruction["op"] == "stop":
|
| 760 |
|
|
#If we are in testbench mode stop the simulation
|
| 761 |
|
|
#If we are part of a larger design, other C programs may still be running
|
| 762 |
|
|
for file_ in input_files.values():
|
| 763 |
|
|
output_file.write(" $fclose(%s);\n"%file_)
|
| 764 |
|
|
for file_ in output_files.values():
|
| 765 |
|
|
output_file.write(" $fclose(%s);\n"%file_)
|
| 766 |
|
|
if testbench:
|
| 767 |
|
|
output_file.write(' $finish;\n')
|
| 768 |
|
|
output_file.write(" program_counter <= program_counter;\n")
|
| 769 |
|
|
output_file.write(" end\n\n")
|
| 770 |
|
|
|
| 771 |
|
|
output_file.write(" endcase\n")
|
| 772 |
|
|
|
| 773 |
|
|
#Reset program counter and control signals
|
| 774 |
|
|
output_file.write(" if (rst == 1'b1) begin\n")
|
| 775 |
|
|
output_file.write(" program_counter <= 0;\n")
|
| 776 |
|
|
for i in inputs:
|
| 777 |
|
|
output_file.write(" s_input_%s_ack <= 0;\n"%(i))
|
| 778 |
|
|
for i in outputs:
|
| 779 |
|
|
output_file.write(" s_output_%s_stb <= 0;\n"%(i))
|
| 780 |
|
|
output_file.write(" end\n")
|
| 781 |
|
|
output_file.write(" end\n")
|
| 782 |
|
|
for i in inputs:
|
| 783 |
|
|
output_file.write(" assign input_%s_ack = s_input_%s_ack;\n"%(i, i))
|
| 784 |
|
|
for i in outputs:
|
| 785 |
|
|
output_file.write(" assign output_%s_stb = s_output_%s_stb;\n"%(i, i))
|
| 786 |
|
|
output_file.write(" assign output_%s = s_output_%s;\n"%(i, i))
|
| 787 |
|
|
output_file.write("\nendmodule\n")
|
| 788 |
|
|
|
| 789 |
|
|
return inputs, outputs
|
| 790 |
|
|
|
| 791 |
|
|
def connect_float_to_int(output_file):
|
| 792 |
|
|
output_file.write(" \n float_to_int float_to_int_1(\n")
|
| 793 |
|
|
output_file.write(" .clk(clk),\n")
|
| 794 |
|
|
output_file.write(" .rst(rst),\n")
|
| 795 |
|
|
output_file.write(" .input_a(float_to),\n")
|
| 796 |
|
|
output_file.write(" .input_a_stb(float_to_stb),\n")
|
| 797 |
|
|
output_file.write(" .input_a_ack(float_to_ack),\n")
|
| 798 |
|
|
output_file.write(" .output_z(to_int),\n")
|
| 799 |
|
|
output_file.write(" .output_z_stb(to_int_stb),\n")
|
| 800 |
|
|
output_file.write(" .output_z_ack(to_int_ack)\n")
|
| 801 |
|
|
output_file.write(" );\n\n")
|
| 802 |
|
|
output_file.write(" \n always @(posedge clk)\n")
|
| 803 |
|
|
output_file.write(" begin\n\n")
|
| 804 |
|
|
output_file.write(" float_to_int_done <= 0;\n")
|
| 805 |
|
|
output_file.write(" case(float_to_int_state)\n\n")
|
| 806 |
|
|
output_file.write(" wait_go:\n")
|
| 807 |
|
|
output_file.write(" begin\n")
|
| 808 |
|
|
output_file.write(" if (float_to_int_go) begin\n")
|
| 809 |
|
|
output_file.write(" float_to_int_state <= write_a;\n")
|
| 810 |
|
|
output_file.write(" end\n")
|
| 811 |
2 |
jondawson |
output_file.write(" end\n\n")
|
| 812 |
4 |
jondawson |
output_file.write(" write_a:\n")
|
| 813 |
|
|
output_file.write(" begin\n")
|
| 814 |
|
|
output_file.write(" float_to_stb <= 1;\n")
|
| 815 |
|
|
output_file.write(" if (float_to_stb && float_to_ack) begin\n")
|
| 816 |
|
|
output_file.write(" float_to_stb <= 0;\n")
|
| 817 |
|
|
output_file.write(" float_to_int_state <= read_z;\n")
|
| 818 |
|
|
output_file.write(" end\n")
|
| 819 |
|
|
output_file.write(" end\n\n")
|
| 820 |
|
|
output_file.write(" read_z:\n")
|
| 821 |
|
|
output_file.write(" begin\n")
|
| 822 |
|
|
output_file.write(" to_int_ack <= 1;\n")
|
| 823 |
|
|
output_file.write(" if (to_int_stb && to_int_ack) begin\n")
|
| 824 |
|
|
output_file.write(" to_int_ack <= 0;\n")
|
| 825 |
|
|
output_file.write(" float_to_int_state <= wait_next;\n")
|
| 826 |
|
|
output_file.write(" float_to_int_done <= 1;\n")
|
| 827 |
|
|
output_file.write(" end\n")
|
| 828 |
|
|
output_file.write(" end\n")
|
| 829 |
|
|
output_file.write(" wait_next:\n")
|
| 830 |
|
|
output_file.write(" begin\n")
|
| 831 |
|
|
output_file.write(" if (!float_to_int_go) begin\n")
|
| 832 |
|
|
output_file.write(" float_to_int_state <= wait_go;\n")
|
| 833 |
|
|
output_file.write(" end\n")
|
| 834 |
|
|
output_file.write(" end\n")
|
| 835 |
|
|
output_file.write(" endcase\n")
|
| 836 |
|
|
output_file.write(" if (rst) begin\n")
|
| 837 |
|
|
output_file.write(" float_to_int_state <= wait_go;\n")
|
| 838 |
|
|
output_file.write(" float_to_stb <= 0;\n")
|
| 839 |
|
|
output_file.write(" to_int_ack <= 0;\n")
|
| 840 |
|
|
output_file.write(" end\n")
|
| 841 |
|
|
output_file.write(" end\n\n")
|
| 842 |
2 |
jondawson |
|
| 843 |
4 |
jondawson |
def connect_int_to_float(output_file):
|
| 844 |
|
|
output_file.write(" \n int_to_float int_to_float_1(\n")
|
| 845 |
|
|
output_file.write(" .clk(clk),\n")
|
| 846 |
|
|
output_file.write(" .rst(rst),\n")
|
| 847 |
|
|
output_file.write(" .input_a(int_to),\n")
|
| 848 |
|
|
output_file.write(" .input_a_stb(int_to_stb),\n")
|
| 849 |
|
|
output_file.write(" .input_a_ack(int_to_ack),\n")
|
| 850 |
|
|
output_file.write(" .output_z(to_float),\n")
|
| 851 |
|
|
output_file.write(" .output_z_stb(to_float_stb),\n")
|
| 852 |
|
|
output_file.write(" .output_z_ack(to_float_ack)\n")
|
| 853 |
|
|
output_file.write(" );\n\n")
|
| 854 |
|
|
output_file.write(" \n always @(posedge clk)\n")
|
| 855 |
|
|
output_file.write(" begin\n\n")
|
| 856 |
|
|
output_file.write(" int_to_float_done <= 0;\n")
|
| 857 |
|
|
output_file.write(" case(int_to_float_state)\n\n")
|
| 858 |
|
|
output_file.write(" wait_go:\n")
|
| 859 |
|
|
output_file.write(" begin\n")
|
| 860 |
|
|
output_file.write(" if (int_to_float_go) begin\n")
|
| 861 |
|
|
output_file.write(" int_to_float_state <= write_a;\n")
|
| 862 |
|
|
output_file.write(" end\n")
|
| 863 |
|
|
output_file.write(" end\n\n")
|
| 864 |
|
|
output_file.write(" write_a:\n")
|
| 865 |
|
|
output_file.write(" begin\n")
|
| 866 |
|
|
output_file.write(" int_to_stb <= 1;\n")
|
| 867 |
|
|
output_file.write(" if (int_to_stb && int_to_ack) begin\n")
|
| 868 |
|
|
output_file.write(" int_to_stb <= 0;\n")
|
| 869 |
|
|
output_file.write(" int_to_float_state <= read_z;\n")
|
| 870 |
|
|
output_file.write(" end\n")
|
| 871 |
|
|
output_file.write(" end\n\n")
|
| 872 |
|
|
output_file.write(" read_z:\n")
|
| 873 |
|
|
output_file.write(" begin\n")
|
| 874 |
|
|
output_file.write(" to_float_ack <= 1;\n")
|
| 875 |
|
|
output_file.write(" if (to_float_stb && to_float_ack) begin\n")
|
| 876 |
|
|
output_file.write(" to_float_ack <= 0;\n")
|
| 877 |
|
|
output_file.write(" int_to_float_state <= wait_next;\n")
|
| 878 |
|
|
output_file.write(" int_to_float_done <= 1;\n")
|
| 879 |
|
|
output_file.write(" end\n")
|
| 880 |
|
|
output_file.write(" end\n")
|
| 881 |
|
|
output_file.write(" wait_next:\n")
|
| 882 |
|
|
output_file.write(" begin\n")
|
| 883 |
|
|
output_file.write(" if (!int_to_float_go) begin\n")
|
| 884 |
|
|
output_file.write(" int_to_float_state <= wait_go;\n")
|
| 885 |
|
|
output_file.write(" end\n")
|
| 886 |
|
|
output_file.write(" end\n")
|
| 887 |
|
|
output_file.write(" endcase\n")
|
| 888 |
|
|
output_file.write(" if (rst) begin\n")
|
| 889 |
|
|
output_file.write(" int_to_float_state <= wait_go;\n")
|
| 890 |
|
|
output_file.write(" int_to_stb <= 0;\n")
|
| 891 |
|
|
output_file.write(" to_float_ack <= 0;\n")
|
| 892 |
|
|
output_file.write(" end\n")
|
| 893 |
|
|
output_file.write(" end\n\n")
|
| 894 |
2 |
jondawson |
|
| 895 |
4 |
jondawson |
def connect_divider(output_file):
|
| 896 |
|
|
output_file.write(" \n divider divider_1(\n")
|
| 897 |
|
|
output_file.write(" .clk(clk),\n")
|
| 898 |
|
|
output_file.write(" .rst(rst),\n")
|
| 899 |
|
|
output_file.write(" .input_a(divider_a),\n")
|
| 900 |
|
|
output_file.write(" .input_a_stb(divider_a_stb),\n")
|
| 901 |
|
|
output_file.write(" .input_a_ack(divider_a_ack),\n")
|
| 902 |
|
|
output_file.write(" .input_b(divider_b),\n")
|
| 903 |
|
|
output_file.write(" .input_b_stb(divider_b_stb),\n")
|
| 904 |
|
|
output_file.write(" .input_b_ack(divider_b_ack),\n")
|
| 905 |
|
|
output_file.write(" .output_z(divider_z),\n")
|
| 906 |
|
|
output_file.write(" .output_z_stb(divider_z_stb),\n")
|
| 907 |
|
|
output_file.write(" .output_z_ack(divider_z_ack)\n")
|
| 908 |
|
|
output_file.write(" );\n\n")
|
| 909 |
|
|
output_file.write(" \n always @(posedge clk)\n")
|
| 910 |
|
|
output_file.write(" begin\n\n")
|
| 911 |
|
|
output_file.write(" divider_done <= 0;\n")
|
| 912 |
|
|
output_file.write(" case(div_state)\n\n")
|
| 913 |
|
|
output_file.write(" wait_go:\n")
|
| 914 |
|
|
output_file.write(" begin\n")
|
| 915 |
|
|
output_file.write(" if (divider_go) begin\n")
|
| 916 |
|
|
output_file.write(" div_state <= write_a;\n")
|
| 917 |
|
|
output_file.write(" end\n")
|
| 918 |
|
|
output_file.write(" end\n\n")
|
| 919 |
|
|
output_file.write(" write_a:\n")
|
| 920 |
|
|
output_file.write(" begin\n")
|
| 921 |
|
|
output_file.write(" divider_a_stb <= 1;\n")
|
| 922 |
|
|
output_file.write(" if (divider_a_stb && divider_a_ack) begin\n")
|
| 923 |
|
|
output_file.write(" divider_a_stb <= 0;\n")
|
| 924 |
|
|
output_file.write(" div_state <= write_b;\n")
|
| 925 |
|
|
output_file.write(" end\n")
|
| 926 |
|
|
output_file.write(" end\n\n")
|
| 927 |
|
|
output_file.write(" write_b:\n")
|
| 928 |
|
|
output_file.write(" begin\n")
|
| 929 |
|
|
output_file.write(" divider_b_stb <= 1;\n")
|
| 930 |
|
|
output_file.write(" if (divider_b_stb && divider_b_ack) begin\n")
|
| 931 |
|
|
output_file.write(" divider_b_stb <= 0;\n")
|
| 932 |
|
|
output_file.write(" div_state <= read_z;\n")
|
| 933 |
|
|
output_file.write(" end\n")
|
| 934 |
|
|
output_file.write(" end\n\n")
|
| 935 |
|
|
output_file.write(" read_z:\n")
|
| 936 |
|
|
output_file.write(" begin\n")
|
| 937 |
|
|
output_file.write(" divider_z_ack <= 1;\n")
|
| 938 |
|
|
output_file.write(" if (divider_z_stb && divider_z_ack) begin\n")
|
| 939 |
|
|
output_file.write(" divider_z_ack <= 0;\n")
|
| 940 |
|
|
output_file.write(" div_state <= wait_next;\n")
|
| 941 |
|
|
output_file.write(" divider_done <= 1;\n")
|
| 942 |
|
|
output_file.write(" end\n")
|
| 943 |
|
|
output_file.write(" end\n")
|
| 944 |
|
|
output_file.write(" wait_next:\n")
|
| 945 |
|
|
output_file.write(" begin\n")
|
| 946 |
|
|
output_file.write(" if (!divider_go) begin\n")
|
| 947 |
|
|
output_file.write(" div_state <= wait_go;\n")
|
| 948 |
|
|
output_file.write(" end\n")
|
| 949 |
|
|
output_file.write(" end\n")
|
| 950 |
|
|
output_file.write(" endcase\n")
|
| 951 |
|
|
output_file.write(" if (rst) begin\n")
|
| 952 |
|
|
output_file.write(" div_state <= wait_go;\n")
|
| 953 |
|
|
output_file.write(" divider_a_stb <= 0;\n")
|
| 954 |
|
|
output_file.write(" divider_b_stb <= 0;\n")
|
| 955 |
|
|
output_file.write(" divider_z_ack <= 0;\n")
|
| 956 |
|
|
output_file.write(" end\n")
|
| 957 |
|
|
output_file.write(" end\n\n")
|
| 958 |
2 |
jondawson |
|
| 959 |
4 |
jondawson |
def connect_multiplier(output_file):
|
| 960 |
|
|
output_file.write(" \n multiplier multiplier_1(\n")
|
| 961 |
|
|
output_file.write(" .clk(clk),\n")
|
| 962 |
|
|
output_file.write(" .rst(rst),\n")
|
| 963 |
|
|
output_file.write(" .input_a(multiplier_a),\n")
|
| 964 |
|
|
output_file.write(" .input_a_stb(multiplier_a_stb),\n")
|
| 965 |
|
|
output_file.write(" .input_a_ack(multiplier_a_ack),\n")
|
| 966 |
|
|
output_file.write(" .input_b(multiplier_b),\n")
|
| 967 |
|
|
output_file.write(" .input_b_stb(multiplier_b_stb),\n")
|
| 968 |
|
|
output_file.write(" .input_b_ack(multiplier_b_ack),\n")
|
| 969 |
|
|
output_file.write(" .output_z(multiplier_z),\n")
|
| 970 |
|
|
output_file.write(" .output_z_stb(multiplier_z_stb),\n")
|
| 971 |
|
|
output_file.write(" .output_z_ack(multiplier_z_ack)\n")
|
| 972 |
|
|
output_file.write(" );\n\n")
|
| 973 |
|
|
output_file.write(" \n always @(posedge clk)\n")
|
| 974 |
|
|
output_file.write(" begin\n\n")
|
| 975 |
|
|
output_file.write(" multiplier_done <= 0;\n")
|
| 976 |
|
|
output_file.write(" case(mul_state)\n\n")
|
| 977 |
|
|
output_file.write(" wait_go:\n")
|
| 978 |
|
|
output_file.write(" begin\n")
|
| 979 |
|
|
output_file.write(" if (multiplier_go) begin\n")
|
| 980 |
|
|
output_file.write(" mul_state <= write_a;\n")
|
| 981 |
|
|
output_file.write(" end\n")
|
| 982 |
|
|
output_file.write(" end\n\n")
|
| 983 |
|
|
output_file.write(" write_a:\n")
|
| 984 |
|
|
output_file.write(" begin\n")
|
| 985 |
|
|
output_file.write(" multiplier_a_stb <= 1;\n")
|
| 986 |
|
|
output_file.write(" if (multiplier_a_stb && multiplier_a_ack) begin\n")
|
| 987 |
|
|
output_file.write(" multiplier_a_stb <= 0;\n")
|
| 988 |
|
|
output_file.write(" mul_state <= write_b;\n")
|
| 989 |
|
|
output_file.write(" end\n")
|
| 990 |
|
|
output_file.write(" end\n\n")
|
| 991 |
|
|
output_file.write(" write_b:\n")
|
| 992 |
|
|
output_file.write(" begin\n")
|
| 993 |
|
|
output_file.write(" multiplier_b_stb <= 1;\n")
|
| 994 |
|
|
output_file.write(" if (multiplier_b_stb && multiplier_b_ack) begin\n")
|
| 995 |
|
|
output_file.write(" multiplier_b_stb <= 0;\n")
|
| 996 |
|
|
output_file.write(" mul_state <= read_z;\n")
|
| 997 |
|
|
output_file.write(" end\n")
|
| 998 |
|
|
output_file.write(" end\n\n")
|
| 999 |
|
|
output_file.write(" read_z:\n")
|
| 1000 |
|
|
output_file.write(" begin\n")
|
| 1001 |
|
|
output_file.write(" multiplier_z_ack <= 1;\n")
|
| 1002 |
|
|
output_file.write(" if (multiplier_z_stb && multiplier_z_ack) begin\n")
|
| 1003 |
|
|
output_file.write(" multiplier_z_ack <= 0;\n")
|
| 1004 |
|
|
output_file.write(" mul_state <= wait_next;\n")
|
| 1005 |
|
|
output_file.write(" multiplier_done <= 1;\n")
|
| 1006 |
|
|
output_file.write(" end\n")
|
| 1007 |
|
|
output_file.write(" end\n\n")
|
| 1008 |
|
|
output_file.write(" wait_next:\n")
|
| 1009 |
|
|
output_file.write(" begin\n")
|
| 1010 |
|
|
output_file.write(" if (!multiplier_go) begin\n")
|
| 1011 |
|
|
output_file.write(" mul_state <= wait_go;\n")
|
| 1012 |
|
|
output_file.write(" end\n")
|
| 1013 |
|
|
output_file.write(" end\n")
|
| 1014 |
|
|
output_file.write(" endcase\n\n")
|
| 1015 |
|
|
output_file.write(" if (rst) begin\n")
|
| 1016 |
|
|
output_file.write(" mul_state <= wait_go;\n")
|
| 1017 |
|
|
output_file.write(" multiplier_a_stb <= 0;\n")
|
| 1018 |
|
|
output_file.write(" multiplier_b_stb <= 0;\n")
|
| 1019 |
|
|
output_file.write(" multiplier_z_ack <= 0;\n")
|
| 1020 |
|
|
output_file.write(" end\n")
|
| 1021 |
|
|
output_file.write(" end\n\n")
|
| 1022 |
|
|
|
| 1023 |
|
|
def connect_adder(output_file):
|
| 1024 |
|
|
output_file.write(" \n adder adder_1(\n")
|
| 1025 |
|
|
output_file.write(" .clk(clk),\n")
|
| 1026 |
|
|
output_file.write(" .rst(rst),\n")
|
| 1027 |
|
|
output_file.write(" .input_a(adder_a),\n")
|
| 1028 |
|
|
output_file.write(" .input_a_stb(adder_a_stb),\n")
|
| 1029 |
|
|
output_file.write(" .input_a_ack(adder_a_ack),\n")
|
| 1030 |
|
|
output_file.write(" .input_b(adder_b),\n")
|
| 1031 |
|
|
output_file.write(" .input_b_stb(adder_b_stb),\n")
|
| 1032 |
|
|
output_file.write(" .input_b_ack(adder_b_ack),\n")
|
| 1033 |
|
|
output_file.write(" .output_z(adder_z),\n")
|
| 1034 |
|
|
output_file.write(" .output_z_stb(adder_z_stb),\n")
|
| 1035 |
|
|
output_file.write(" .output_z_ack(adder_z_ack)\n")
|
| 1036 |
|
|
output_file.write(" );\n\n")
|
| 1037 |
|
|
output_file.write(" \n always @(posedge clk)\n")
|
| 1038 |
|
|
output_file.write(" begin\n\n")
|
| 1039 |
|
|
output_file.write(" adder_done <= 0;\n")
|
| 1040 |
|
|
output_file.write(" case(add_state)\n\n")
|
| 1041 |
|
|
output_file.write(" wait_go:\n")
|
| 1042 |
|
|
output_file.write(" begin\n")
|
| 1043 |
|
|
output_file.write(" if (adder_go) begin\n")
|
| 1044 |
|
|
output_file.write(" add_state <= write_a;\n")
|
| 1045 |
|
|
output_file.write(" end\n")
|
| 1046 |
|
|
output_file.write(" end\n\n")
|
| 1047 |
|
|
output_file.write(" write_a:\n")
|
| 1048 |
|
|
output_file.write(" begin\n")
|
| 1049 |
|
|
output_file.write(" adder_a_stb <= 1;\n")
|
| 1050 |
|
|
output_file.write(" if (adder_a_stb && adder_a_ack) begin\n")
|
| 1051 |
|
|
output_file.write(" adder_a_stb <= 0;\n")
|
| 1052 |
|
|
output_file.write(" add_state <= write_b;\n")
|
| 1053 |
|
|
output_file.write(" end\n")
|
| 1054 |
|
|
output_file.write(" end\n\n")
|
| 1055 |
|
|
output_file.write(" write_b:\n")
|
| 1056 |
|
|
output_file.write(" begin\n")
|
| 1057 |
|
|
output_file.write(" adder_b_stb <= 1;\n")
|
| 1058 |
|
|
output_file.write(" if (adder_b_stb && adder_b_ack) begin\n")
|
| 1059 |
|
|
output_file.write(" adder_b_stb <= 0;\n")
|
| 1060 |
|
|
output_file.write(" add_state <= read_z;\n")
|
| 1061 |
|
|
output_file.write(" end\n")
|
| 1062 |
|
|
output_file.write(" end\n\n")
|
| 1063 |
|
|
output_file.write(" read_z:\n")
|
| 1064 |
|
|
output_file.write(" begin\n")
|
| 1065 |
|
|
output_file.write(" adder_z_ack <= 1;\n")
|
| 1066 |
|
|
output_file.write(" if (adder_z_stb && adder_z_ack) begin\n")
|
| 1067 |
|
|
output_file.write(" adder_z_ack <= 0;\n")
|
| 1068 |
|
|
output_file.write(" add_state <= wait_next;\n")
|
| 1069 |
|
|
output_file.write(" adder_done <= 1;\n")
|
| 1070 |
|
|
output_file.write(" end\n")
|
| 1071 |
|
|
output_file.write(" end\n")
|
| 1072 |
|
|
output_file.write(" wait_next:\n")
|
| 1073 |
|
|
output_file.write(" begin\n")
|
| 1074 |
|
|
output_file.write(" if (!adder_go) begin\n")
|
| 1075 |
|
|
output_file.write(" add_state <= wait_go;\n")
|
| 1076 |
|
|
output_file.write(" end\n")
|
| 1077 |
|
|
output_file.write(" end\n")
|
| 1078 |
|
|
output_file.write(" endcase\n")
|
| 1079 |
|
|
output_file.write(" if (rst) begin\n")
|
| 1080 |
|
|
output_file.write(" add_state <= wait_go;\n")
|
| 1081 |
|
|
output_file.write(" adder_a_stb <= 0;\n")
|
| 1082 |
|
|
output_file.write(" adder_b_stb <= 0;\n")
|
| 1083 |
|
|
output_file.write(" adder_z_ack <= 0;\n")
|
| 1084 |
|
|
output_file.write(" end\n")
|
| 1085 |
|
|
output_file.write(" end\n\n")
|
| 1086 |
|
|
|
| 1087 |
|
|
def generate_float_to_int_signals(output_file):
|
| 1088 |
|
|
output_file.write(" reg [31:0] float_to;\n")
|
| 1089 |
|
|
output_file.write(" reg float_to_stb;\n")
|
| 1090 |
|
|
output_file.write(" wire float_to_ack;\n")
|
| 1091 |
|
|
output_file.write(" wire [31:0] to_int;\n")
|
| 1092 |
|
|
output_file.write(" wire to_int_stb;\n")
|
| 1093 |
|
|
output_file.write(" reg to_int_ack;\n")
|
| 1094 |
|
|
output_file.write(" reg [2:0] float_to_int_state;\n")
|
| 1095 |
|
|
output_file.write(" reg float_to_int_go;\n")
|
| 1096 |
|
|
output_file.write(" reg float_to_int_done;\n")
|
| 1097 |
|
|
|
| 1098 |
|
|
def generate_int_to_float_signals(output_file):
|
| 1099 |
|
|
output_file.write(" reg [31:0] int_to;\n")
|
| 1100 |
|
|
output_file.write(" reg int_to_stb;\n")
|
| 1101 |
|
|
output_file.write(" wire int_to_ack;\n")
|
| 1102 |
|
|
output_file.write(" wire [31:0] to_float;\n")
|
| 1103 |
|
|
output_file.write(" wire to_float_stb;\n")
|
| 1104 |
|
|
output_file.write(" reg to_float_ack;\n")
|
| 1105 |
|
|
output_file.write(" reg [2:0] int_to_float_state;\n")
|
| 1106 |
|
|
output_file.write(" reg int_to_float_go;\n")
|
| 1107 |
|
|
output_file.write(" reg int_to_float_done;\n")
|
| 1108 |
|
|
|
| 1109 |
|
|
def generate_divider_signals(output_file):
|
| 1110 |
|
|
output_file.write(" reg [31:0] divider_a;\n")
|
| 1111 |
|
|
output_file.write(" reg divider_a_stb;\n")
|
| 1112 |
|
|
output_file.write(" wire divider_a_ack;\n")
|
| 1113 |
|
|
output_file.write(" reg [31:0] divider_b;\n")
|
| 1114 |
|
|
output_file.write(" reg divider_b_stb;\n")
|
| 1115 |
|
|
output_file.write(" wire divider_b_ack;\n")
|
| 1116 |
|
|
output_file.write(" wire [31:0] divider_z;\n")
|
| 1117 |
|
|
output_file.write(" wire divider_z_stb;\n")
|
| 1118 |
|
|
output_file.write(" reg divider_z_ack;\n")
|
| 1119 |
|
|
output_file.write(" reg [2:0] div_state;\n")
|
| 1120 |
|
|
output_file.write(" reg divider_go;\n")
|
| 1121 |
|
|
output_file.write(" reg divider_done;\n")
|
| 1122 |
|
|
|
| 1123 |
|
|
def generate_multiplier_signals(output_file):
|
| 1124 |
|
|
output_file.write(" reg [31:0] multiplier_a;\n")
|
| 1125 |
|
|
output_file.write(" reg multiplier_a_stb;\n")
|
| 1126 |
|
|
output_file.write(" wire multiplier_a_ack;\n")
|
| 1127 |
|
|
output_file.write(" reg [31:0] multiplier_b;\n")
|
| 1128 |
|
|
output_file.write(" reg multiplier_b_stb;\n")
|
| 1129 |
|
|
output_file.write(" wire multiplier_b_ack;\n")
|
| 1130 |
|
|
output_file.write(" wire [31:0] multiplier_z;\n")
|
| 1131 |
|
|
output_file.write(" wire multiplier_z_stb;\n")
|
| 1132 |
|
|
output_file.write(" reg multiplier_z_ack;\n")
|
| 1133 |
|
|
output_file.write(" reg [2:0] mul_state;\n")
|
| 1134 |
|
|
output_file.write(" reg multiplier_go;\n")
|
| 1135 |
|
|
output_file.write(" reg multiplier_done;\n")
|
| 1136 |
|
|
|
| 1137 |
|
|
def generate_adder_signals(output_file):
|
| 1138 |
|
|
output_file.write(" reg [31:0] adder_a;\n")
|
| 1139 |
|
|
output_file.write(" reg adder_a_stb;\n")
|
| 1140 |
|
|
output_file.write(" wire adder_a_ack;\n")
|
| 1141 |
|
|
output_file.write(" reg [31:0] adder_b;\n")
|
| 1142 |
|
|
output_file.write(" reg adder_b_stb;\n")
|
| 1143 |
|
|
output_file.write(" wire adder_b_ack;\n")
|
| 1144 |
|
|
output_file.write(" wire [31:0] adder_z;\n")
|
| 1145 |
|
|
output_file.write(" wire adder_z_stb;\n")
|
| 1146 |
|
|
output_file.write(" reg adder_z_ack;\n")
|
| 1147 |
|
|
output_file.write(" reg [2:0] add_state;\n")
|
| 1148 |
|
|
output_file.write(" reg adder_go;\n")
|
| 1149 |
|
|
output_file.write(" reg adder_done;\n")
|
