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`timescale 1 ns / 1 ns
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module testbench();
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// DATE: Mon May 19 20:22:16 2003
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// TITLE:
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// MODULE: TDM_Switch
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// DESIGN: TDM_Switch
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// FILENAME: TDM_Switch
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// PROJECT: tdm_switch
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// VERSION: Version
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// Inputs
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reg CLKIN;
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reg reset;
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reg R_W;
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reg EN;
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reg ram_clk;
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reg [8:0] ADDR;
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reg [8:0] DIN;
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wire [7:0] tdm_in;
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// Outputs
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wire [7:0] tdm_out;
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wire CLKOUT;
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wire FS_SIG;
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wire [8:0] DOUT;
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// Bidirs
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reg [7:0] frame_reg;
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reg [7:0] slot_load_reg;
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wire slot_load;
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wire [4:0] time_slot;
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reg [7:0] bit_counter;
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reg [4:0] timeslot_counter;
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reg [7:0] stream_0_mem_in [31:0];
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reg [7:0] stream_1_mem_in [31:0];
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reg [7:0] stream_2_mem_in [31:0];
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reg [7:0] stream_3_mem_in [31:0];
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reg [7:0] stream_4_mem_in [31:0];
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reg [7:0] stream_5_mem_in [31:0];
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reg [7:0] stream_6_mem_in [31:0];
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reg [7:0] stream_7_mem_in [31:0];
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reg [15:0] MEMORY [0:263];
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reg [7:0] stream_0_shift_reg_in;
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reg [7:0] stream_1_shift_reg_in;
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reg [7:0] stream_2_shift_reg_in;
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reg [7:0] stream_3_shift_reg_in;
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reg [7:0] stream_4_shift_reg_in;
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reg [7:0] stream_5_shift_reg_in;
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reg [7:0] stream_6_shift_reg_in;
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reg [7:0] stream_7_shift_reg_in;
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reg [7:0] stream_0_shift_reg_out;
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reg [7:0] stream_1_shift_reg_out;
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reg [7:0] stream_2_shift_reg_out;
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reg [7:0] stream_3_shift_reg_out;
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reg [7:0] stream_4_shift_reg_out;
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reg [7:0] stream_5_shift_reg_out;
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reg [7:0] stream_6_shift_reg_out;
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reg [7:0] stream_7_shift_reg_out;
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reg [4:0] display_en;
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wire in_stream_0, out_stream_0;
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wire in_stream_1, out_stream_1;
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wire in_stream_2, out_stream_2;
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wire in_stream_3, out_stream_3;
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wire in_stream_4, out_stream_4;
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wire in_stream_5, out_stream_5;
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wire in_stream_6, out_stream_6;
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wire in_stream_7, out_stream_7;
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wire [15:0] DATA_IN;
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// Instantiate the UUT
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tdm_switch_top UUT (
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.clk_in(CLKIN),
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.clk_out(CLKOUT),
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.frame_sync(FS_SIG),
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.rx_stream(tdm_in),
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.tx_stream(tdm_out),
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.reset(reset),
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.mpi_clk(ram_clk),
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.mpi_cs(EN),
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.mpi_rw(R_W),
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.mpi_addr(ADDR[8:0]),
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.mpi_data_in(DIN),
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.mpi_data_out(DOUT)
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);
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// Initialize Inputs
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// `ifdef auto_init
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initial begin
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CLKIN = 0;
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reset = 0;
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R_W = 0;
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EN = 0;
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ram_clk = 0;
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ADDR = 0;
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DIN = 0;
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display_en = 0;
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#2000 reset = 1;
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end
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// `endif
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//=====================================================================
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initial
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begin
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$readmemh ("stream_0.dat", stream_0_mem_in);
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$readmemh ("stream_1.dat", stream_1_mem_in);
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$readmemh ("stream_2.dat", stream_2_mem_in);
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$readmemh ("stream_3.dat", stream_3_mem_in);
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$readmemh ("stream_4.dat", stream_4_mem_in);
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$readmemh ("stream_5.dat", stream_5_mem_in);
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$readmemh ("stream_6.dat", stream_6_mem_in);
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$readmemh ("stream_7.dat", stream_7_mem_in);
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$readmemh ("map.dat", MEMORY);
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end
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//=====================================================================
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always #122 CLKIN = ~CLKIN;
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always #100 ram_clk = ~ram_clk;
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assign DATA_IN = MEMORY [ADDR];
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always @ (DATA_IN)
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DIN = DATA_IN [8:0];
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always @ (negedge ram_clk or negedge reset)
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if (!reset)
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ADDR = 0;
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else
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if (ADDR == 9'h107)
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ADDR = ADDR;
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else
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ADDR = ADDR + 1;
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always @ (ADDR)
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EN = (ADDR < 9'h108);
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initial #1000000 $stop;
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always @ (posedge CLKOUT)
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if (FS_SIG)
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frame_reg <= 0;
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else
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frame_reg <= frame_reg + 1;
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//=====================================================================
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always @ (posedge CLKOUT)
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if (FS_SIG)
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bit_counter <= 0;
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else
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bit_counter <= bit_counter + 1;
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always @ (bit_counter)
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timeslot_counter <= (bit_counter + 1) >> 3;
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always @ (negedge CLKOUT)
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case (frame_reg)
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8'hFF : slot_load_reg <= 8'h80;
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default : slot_load_reg[7:0] <= {slot_load_reg[0], slot_load_reg[7:1]};
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endcase
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assign slot_load = slot_load_reg[7];
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always @ (posedge CLKOUT)
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if (slot_load)
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begin
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stream_0_shift_reg_in <= stream_0_mem_in [timeslot_counter];
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stream_1_shift_reg_in <= stream_1_mem_in [timeslot_counter];
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stream_2_shift_reg_in <= stream_2_mem_in [timeslot_counter];
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stream_3_shift_reg_in <= stream_3_mem_in [timeslot_counter];
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stream_4_shift_reg_in <= stream_4_mem_in [timeslot_counter];
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stream_5_shift_reg_in <= stream_5_mem_in [timeslot_counter];
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stream_6_shift_reg_in <= stream_6_mem_in [timeslot_counter];
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stream_7_shift_reg_in <= stream_7_mem_in [timeslot_counter];
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end
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else
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begin
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stream_0_shift_reg_in <= stream_0_shift_reg_in >> 1;
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stream_1_shift_reg_in <= stream_1_shift_reg_in >> 1;
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stream_2_shift_reg_in <= stream_2_shift_reg_in >> 1;
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stream_3_shift_reg_in <= stream_3_shift_reg_in >> 1;
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stream_4_shift_reg_in <= stream_4_shift_reg_in >> 1;
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stream_5_shift_reg_in <= stream_5_shift_reg_in >> 1;
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stream_6_shift_reg_in <= stream_6_shift_reg_in >> 1;
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stream_7_shift_reg_in <= stream_7_shift_reg_in >> 1;
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end
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assign in_stream_0 = stream_0_shift_reg_in[0];
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assign in_stream_1 = stream_1_shift_reg_in[0];
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assign in_stream_2 = stream_2_shift_reg_in[0];
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assign in_stream_3 = stream_3_shift_reg_in[0];
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assign in_stream_4 = stream_4_shift_reg_in[0];
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assign in_stream_5 = stream_5_shift_reg_in[0];
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assign in_stream_6 = stream_6_shift_reg_in[0];
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assign in_stream_7 = stream_7_shift_reg_in[0];
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assign out_stream_0 = tdm_out[0];
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assign out_stream_1 = tdm_out[1];
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assign out_stream_2 = tdm_out[2];
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assign out_stream_3 = tdm_out[3];
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assign out_stream_4 = tdm_out[4];
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assign out_stream_5 = tdm_out[5];
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assign out_stream_6 = tdm_out[6];
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assign out_stream_7 = tdm_out[7];
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assign tdm_in[0] = in_stream_0;
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assign tdm_in[1] = in_stream_1;
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assign tdm_in[2] = in_stream_2;
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assign tdm_in[3] = in_stream_3;
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assign tdm_in[4] = in_stream_4;
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assign tdm_in[5] = in_stream_5;
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assign tdm_in[6] = in_stream_6;
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assign tdm_in[7] = in_stream_7;
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always @ (negedge CLKOUT)
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begin
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stream_0_shift_reg_out <= {out_stream_0, stream_0_shift_reg_out[7:1]};
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stream_1_shift_reg_out <= {out_stream_1, stream_1_shift_reg_out[7:1]};
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stream_2_shift_reg_out <= {out_stream_2, stream_2_shift_reg_out[7:1]};
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stream_3_shift_reg_out <= {out_stream_3, stream_3_shift_reg_out[7:1]};
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stream_4_shift_reg_out <= {out_stream_4, stream_4_shift_reg_out[7:1]};
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stream_5_shift_reg_out <= {out_stream_5, stream_5_shift_reg_out[7:1]};
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stream_6_shift_reg_out <= {out_stream_6, stream_6_shift_reg_out[7:1]};
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stream_7_shift_reg_out <= {out_stream_7, stream_7_shift_reg_out[7:1]};
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end
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assign time_slot = timeslot_counter-1;
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always @ (negedge FS_SIG)
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display_en = display_en + 1;
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/*
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always @ (posedge CLKOUT)
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if (FS_SIG)
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display_en = display_en + 1;
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else
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display_en = display_en;
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*/
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integer SimFile;
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initial SimFile = $fopen("sim_result.dat");
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initial
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begin
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$display ("||=======================================================================================================||");
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$display ("||***************************** SWITCHING **************** RESULTAT *************************************||");
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$display ("||=======================================================================================================||");
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$display ("|| Time Slot # || STREAM_0 | STREAM_1 | STREAM_2 | STREAM_3 | STREAM_4 | STREAM_5 | STREAM_6 | STREAM_7 ||");
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$display ("||==============||==========|==========|==========|==========|==========|==========|==========|==========||");
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$fdisplay (SimFile, "||=======================================================================================================||");
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$fdisplay (SimFile, "||***************************** SWITCHING **************** RESULTAT *************************************||");
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$fdisplay (SimFile, "||=======================================================================================================||");
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$fdisplay (SimFile, "|| Time Slot # || STREAM_0 | STREAM_1 | STREAM_2 | STREAM_3 | STREAM_4 | STREAM_5 | STREAM_6 | STREAM_7 ||");
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$fdisplay (SimFile, "||==============||==========|==========|==========|==========|==========|==========|==========|==========||");
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end
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always @ (posedge CLKOUT)
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if (display_en > 4)
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if (slot_load)
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begin
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$display ("|| Time Slot %d || %h | %h | %h | %h | %h | %h | %h | %h || ", time_slot,
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stream_0_shift_reg_out,
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stream_1_shift_reg_out,
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stream_2_shift_reg_out,
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stream_3_shift_reg_out,
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stream_4_shift_reg_out,
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stream_5_shift_reg_out,
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stream_6_shift_reg_out,
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stream_7_shift_reg_out);
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$display ("||=======================================================================================================||");
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$fdisplay (SimFile, "|| Time Slot %d || %h | %h | %h | %h | %h | %h | %h | %h || ", time_slot,
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stream_0_shift_reg_out,
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stream_1_shift_reg_out,
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stream_2_shift_reg_out,
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stream_3_shift_reg_out,
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stream_4_shift_reg_out,
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stream_5_shift_reg_out,
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stream_6_shift_reg_out,
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stream_7_shift_reg_out);
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$fdisplay (SimFile, "||=======================================================================================================||");
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end
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endmodule
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