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[/] [tg68/] [trunk/] [VHDL/] [TG68.vhd] - Blame information for rev 10

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------------------------------------------------------------------------------
------------------------------------------------------------------------------
--                                                                          --
-- This is the TOP-Level for TG68_fast to generate 68K Bus signals          --
--                                                                          --
-- Copyright (c) 2007-2008 Tobias Gubener <tobiflex@opencores.org>          -- 
--                                                                          --
-- This source file is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU Lesser General Public License as published --
-- by the Free Software Foundation, either version 3 of the License, or     --
-- (at your option) any later version.                                      --
--                                                                          --
-- This source file is distributed in the hope that it will be useful,      --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of           --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            --
-- GNU General Public License for more details.                             --
--                                                                          --
-- You should have received a copy of the GNU General Public License        --
-- along with this program.  If not, see <http://www.gnu.org/licenses/>.    --
--                                                                          --
------------------------------------------------------------------------------
------------------------------------------------------------------------------
--
-- Revision 1.02 2008/01/23
-- bugfix Timing
--
-- Revision 1.01 2007/11/28
-- add MOVEP
-- Bugfix Interrupt in MOVEQ
--
-- Revision 1.0 2007/11/05
-- Clean up code and first release
--
-- known bugs/todo:
-- Add CHK INSTRUCTION
-- full decode ILLEGAL INSTRUCTIONS
-- Add FDC Output
-- add odd Address test
-- add TRACE
-- Movem with regmask==x0000
 
 
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity TG68 is
   port(
                clk           : in std_logic;
                reset         : in std_logic;
        clkena_in     : in std_logic:='1';
        data_in       : in std_logic_vector(15 downto 0);
        IPL           : in std_logic_vector(2 downto 0):="111";
        dtack         : in std_logic;
        addr          : out std_logic_vector(31 downto 0);
        data_out      : out std_logic_vector(15 downto 0);
        as            : out std_logic;
        uds           : out std_logic;
        lds           : out std_logic;
        rw            : out std_logic;
        drive_data    : out std_logic                           --enable for data_out driver
        );
end TG68;
 
ARCHITECTURE logic OF TG68 IS
 
        COMPONENT TG68_fast
    PORT (
        clk           : in std_logic;
        reset         : in std_logic;
        clkena_in     : in std_logic;
        data_in       : in std_logic_vector(15 downto 0);
                IPL                       : in std_logic_vector(2 downto 0);
        test_IPL      : in std_logic;
        address       : out std_logic_vector(31 downto 0);
        data_write    : out std_logic_vector(15 downto 0);
        state_out     : out std_logic_vector(1 downto 0);
        decodeOPC     : buffer std_logic;
                wr                        : out std_logic;
                UDS, LDS          : out std_logic
        );
        END COMPONENT;
 
 
   SIGNAL as_s        : std_logic;
   SIGNAL as_e        : std_logic;
   SIGNAL uds_s       : std_logic;
   SIGNAL uds_e       : std_logic;
   SIGNAL lds_s       : std_logic;
   SIGNAL lds_e       : std_logic;
   SIGNAL rw_s        : std_logic;
   SIGNAL rw_e        : std_logic;
   SIGNAL waitm       : std_logic;
   SIGNAL clkena_e    : std_logic;
   SIGNAL S_state     : std_logic_vector(1 downto 0);
   SIGNAL decode          : std_logic;
   SIGNAL wr          : std_logic;
   SIGNAL uds_in          : std_logic;
   SIGNAL lds_in          : std_logic;
   SIGNAL state       : std_logic_vector(1 downto 0);
   SIGNAL clkena          : std_logic;
   SIGNAL n_clk           : std_logic;
   SIGNAL cpuIPL      : std_logic_vector(2 downto 0);
 
 
BEGIN
 
        n_clk <= NOT clk;
 
TG68_fast_inst: TG68_fast
        PORT MAP (
                clk => n_clk,                   -- : in std_logic;
        reset => reset,                 -- : in std_logic;
        clkena_in => clkena,    -- : in std_logic;
        data_in => data_in,     -- : in std_logic_vector(15 downto 0);
                IPL => cpuIPL,                  -- : in std_logic_vector(2 downto 0);
        test_IPL => '0',                 -- : in std_logic;
        address => addr,                -- : out std_logic_vector(31 downto 0);
        data_write => data_out, -- : out std_logic_vector(15 downto 0);
        state_out => state,     -- : out std_logic_vector(1 downto 0);
        decodeOPC => decode,    -- : buffer std_logic;
                wr => wr,                               -- : out std_logic;
                UDS => uds_in,                  -- : out std_logic;
                LDS => lds_in                   -- : out std_logic;
        );
 
        PROCESS (clk)
        BEGIN
                IF clkena_in='1' AND (clkena_e='1' OR state="01") THEN
                        clkena <= '1';
                ELSE
                        clkena <= '0';
                END IF;
        END PROCESS;
 
PROCESS (clk, reset, state, as_s, as_e, rw_s, rw_e, uds_s, uds_e, lds_s, lds_e)
        BEGIN
                IF state="01" THEN
                        as <= '1';
                        rw <= '1';
                        uds <= '1';
                        lds <= '1';
                ELSE
                        as <= as_s AND as_e;
                        rw <= rw_s AND rw_e;
                        uds <= uds_s AND uds_e;
                        lds <= lds_s AND lds_e;
                END IF;
                IF reset='0' THEN
                        S_state <= "11";
                        as_s <= '1';
                        rw_s <= '1';
                        uds_s <= '1';
                        lds_s <= '1';
                ELSIF rising_edge(clk) THEN
                IF clkena_in='1' THEN
                                as_s <= '1';
                                rw_s <= '1';
                                uds_s <= '1';
                                lds_s <= '1';
                                IF state/="01" OR decode='1' THEN
                                        CASE S_state IS
                                                WHEN "00" => as_s <= '0';
                                                                         rw_s <= wr;
                                                                         IF wr='1' THEN
                                                                                 uds_s <= uds_in;
                                                                                 lds_s <= lds_in;
                                                                         END IF;
                                                                         S_state <= "01";
                                                WHEN "01" => as_s <= '0';
                                                                         rw_s <= wr;
                                                                         uds_s <= uds_in;
                                                                         lds_s <= lds_in;
                                                                         S_state <= "10";
                                                WHEN "10" =>
                                                                         rw_s <= wr;
                                                                         IF waitm='0' THEN
                                                                                S_state <= "11";
                                                                         END IF;
                                                WHEN "11" =>
                                                                         S_state <= "00";
                                                WHEN OTHERS => null;
                                        END CASE;
                                END IF;
                        END IF;
                END IF;
                IF reset='0' THEN
                        as_e <= '1';
                        rw_e <= '1';
                        uds_e <= '1';
                        lds_e <= '1';
                        clkena_e <= '0';
                        cpuIPL <= "111";
                        drive_data <= '0';
                ELSIF falling_edge(clk) THEN
                IF clkena_in='1' THEN
                                as_e <= '1';
                                rw_e <= '1';
                                uds_e <= '1';
                                lds_e <= '1';
                                clkena_e <= '0';
                                drive_data <= '0';
                                CASE S_state IS
                                        WHEN "00" => null;
                                        WHEN "01" => drive_data <= NOT wr;
                                        WHEN "10" => as_e <= '0';
                                                                 uds_e <= uds_in;
                                                                 lds_e <= lds_in;
                                                                 cpuIPL <= IPL;
                                                                 drive_data <= NOT wr;
                                                                 IF state="01" THEN
                                                                         clkena_e <= '1';
                                                                         waitm <= '0';
                                                                 ELSE
                                                                         clkena_e <= NOT dtack;
                                                                         waitm <= dtack;
                                                                 END IF;
                                        WHEN OTHERS => null;
                                END CASE;
                        END IF;
                END IF;
        END PROCESS;
END;

Line No.	Rev	Author	Line
1	2	tobiflex	`------------------------------------------------------------------------------`
2			`------------------------------------------------------------------------------`
3			`-- --`
4			`-- This is the TOP-Level for TG68_fast to generate 68K Bus signals --`
5			`-- --`
6	8	tobiflex	`-- Copyright (c) 2007-2008 Tobias Gubener <tobiflex@opencores.org> --`
7	2	tobiflex	`-- --`
8			`-- This source file is free software: you can redistribute it and/or modify --`
9			`-- it under the terms of the GNU Lesser General Public License as published --`
10			`-- by the Free Software Foundation, either version 3 of the License, or --`
11			`-- (at your option) any later version. --`
12			`-- --`
13			`-- This source file is distributed in the hope that it will be useful, --`
14			`-- but WITHOUT ANY WARRANTY; without even the implied warranty of --`
15			`-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --`
16			`-- GNU General Public License for more details. --`
17			`-- --`
18			`-- You should have received a copy of the GNU General Public License --`
19			`-- along with this program. If not, see <http://www.gnu.org/licenses/>. --`
20			`-- --`
21			`------------------------------------------------------------------------------`
22			`------------------------------------------------------------------------------`
23			`--`
24	8	tobiflex	`-- Revision 1.02 2008/01/23`
25			`-- bugfix Timing`
26			`--`
27	4	tobiflex	`-- Revision 1.01 2007/11/28`
28			`-- add MOVEP`
29			`-- Bugfix Interrupt in MOVEQ`
30			`--`
31	2	tobiflex	`-- Revision 1.0 2007/11/05`
32			`-- Clean up code and first release`
33			`--`
34			`-- known bugs/todo:`
35			`-- Add CHK INSTRUCTION`
36			`-- full decode ILLEGAL INSTRUCTIONS`
37			`-- Add FDC Output`
38			`-- add odd Address test`
39			`-- add TRACE`
40			`-- Movem with regmask==x0000`
41
42
43
44			`library ieee;`
45			`use ieee.std_logic_1164.all;`
46			`use ieee.std_logic_unsigned.all;`
47
48			`entity TG68 is`
49			`port(`
50			`clk : in std_logic;`
51			`reset : in std_logic;`
52			`clkena_in : in std_logic:='1';`
53			`data_in : in std_logic_vector(15 downto 0);`
54			`IPL : in std_logic_vector(2 downto 0):="111";`
55			`dtack : in std_logic;`
56			`addr : out std_logic_vector(31 downto 0);`
57			`data_out : out std_logic_vector(15 downto 0);`
58			`as : out std_logic;`
59			`uds : out std_logic;`
60			`lds : out std_logic;`
61	8	tobiflex	`rw : out std_logic;`
62			`drive_data : out std_logic --enable for data_out driver`
63	2	tobiflex	`);`
64			`end TG68;`
65
66			`ARCHITECTURE logic OF TG68 IS`
67
68			`COMPONENT TG68_fast`
69			`PORT (`
70			`clk : in std_logic;`
71			`reset : in std_logic;`
72			`clkena_in : in std_logic;`
73			`data_in : in std_logic_vector(15 downto 0);`
74			`IPL : in std_logic_vector(2 downto 0);`
75			`test_IPL : in std_logic;`
76			`address : out std_logic_vector(31 downto 0);`
77			`data_write : out std_logic_vector(15 downto 0);`
78			`state_out : out std_logic_vector(1 downto 0);`
79			`decodeOPC : buffer std_logic;`
80			`wr : out std_logic;`
81			`UDS, LDS : out std_logic`
82			`);`
83			`END COMPONENT;`
84
85
86			`SIGNAL as_s : std_logic;`
87			`SIGNAL as_e : std_logic;`
88			`SIGNAL uds_s : std_logic;`
89			`SIGNAL uds_e : std_logic;`
90			`SIGNAL lds_s : std_logic;`
91			`SIGNAL lds_e : std_logic;`
92			`SIGNAL rw_s : std_logic;`
93			`SIGNAL rw_e : std_logic;`
94			`SIGNAL waitm : std_logic;`
95			`SIGNAL clkena_e : std_logic;`
96			`SIGNAL S_state : std_logic_vector(1 downto 0);`
97			`SIGNAL decode : std_logic;`
98			`SIGNAL wr : std_logic;`
99			`SIGNAL uds_in : std_logic;`
100			`SIGNAL lds_in : std_logic;`
101			`SIGNAL state : std_logic_vector(1 downto 0);`
102			`SIGNAL clkena : std_logic;`
103	8	tobiflex	`SIGNAL n_clk : std_logic;`
104			`SIGNAL cpuIPL : std_logic_vector(2 downto 0);`
105	2	tobiflex
106
107			`BEGIN`
108
109	8	tobiflex	`n_clk <= NOT clk;`
110
111	2	tobiflex	`TG68_fast_inst: TG68_fast`
112			`PORT MAP (`
113	8	tobiflex	`clk => n_clk, -- : in std_logic;`
114	2	tobiflex	`reset => reset, -- : in std_logic;`
115			`clkena_in => clkena, -- : in std_logic;`
116			`data_in => data_in, -- : in std_logic_vector(15 downto 0);`
117	8	tobiflex	`IPL => cpuIPL, -- : in std_logic_vector(2 downto 0);`
118	2	tobiflex	`test_IPL => '0', -- : in std_logic;`
119			`address => addr, -- : out std_logic_vector(31 downto 0);`
120			`data_write => data_out, -- : out std_logic_vector(15 downto 0);`
121			`state_out => state, -- : out std_logic_vector(1 downto 0);`
122			`decodeOPC => decode, -- : buffer std_logic;`
123			`wr => wr, -- : out std_logic;`
124			`UDS => uds_in, -- : out std_logic;`
125			`LDS => lds_in -- : out std_logic;`
126			`);`
127
128			`PROCESS (clk)`
129			`BEGIN`
130	8	tobiflex	`IF clkena_in='1' AND (clkena_e='1' OR state="01") THEN`
131			`clkena <= '1';`
132			`ELSE`
133			`clkena <= '0';`
134	2	tobiflex	`END IF;`
135			`END PROCESS;`
136
137			`PROCESS (clk, reset, state, as_s, as_e, rw_s, rw_e, uds_s, uds_e, lds_s, lds_e)`
138			`BEGIN`
139			`IF state="01" THEN`
140			`as <= '1';`
141			`rw <= '1';`
142			`uds <= '1';`
143			`lds <= '1';`
144			`ELSE`
145			`as <= as_s AND as_e;`
146			`rw <= rw_s AND rw_e;`
147			`uds <= uds_s AND uds_e;`
148			`lds <= lds_s AND lds_e;`
149			`END IF;`
150			`IF reset='0' THEN`
151			`S_state <= "11";`
152			`as_s <= '1';`
153			`rw_s <= '1';`
154			`uds_s <= '1';`
155			`lds_s <= '1';`
156			`ELSIF rising_edge(clk) THEN`
157			`IF clkena_in='1' THEN`
158			`as_s <= '1';`
159			`rw_s <= '1';`
160			`uds_s <= '1';`
161			`lds_s <= '1';`
162	8	tobiflex	`IF state/="01" OR decode='1' THEN`
163			`CASE S_state IS`
164			`WHEN "00" => as_s <= '0';`
165			`rw_s <= wr;`
166			`IF wr='1' THEN`
167			`uds_s <= uds_in;`
168			`lds_s <= lds_in;`
169			`END IF;`
170			`S_state <= "01";`
171			`WHEN "01" => as_s <= '0';`
172			`rw_s <= wr;`
173	2	tobiflex	`uds_s <= uds_in;`
174			`lds_s <= lds_in;`
175	8	tobiflex	`S_state <= "10";`
176			`WHEN "10" =>`
177			`rw_s <= wr;`
178			`IF waitm='0' THEN`
179			`S_state <= "11";`
180			`END IF;`
181			`WHEN "11" =>`
182			`S_state <= "00";`
183			`WHEN OTHERS => null;`
184			`END CASE;`
185			`END IF;`
186	2	tobiflex	`END IF;`
187			`END IF;`
188			`IF reset='0' THEN`
189			`as_e <= '1';`
190			`rw_e <= '1';`
191			`uds_e <= '1';`
192			`lds_e <= '1';`
193			`clkena_e <= '0';`
194	8	tobiflex	`cpuIPL <= "111";`
195			`drive_data <= '0';`
196	2	tobiflex	`ELSIF falling_edge(clk) THEN`
197			`IF clkena_in='1' THEN`
198			`as_e <= '1';`
199			`rw_e <= '1';`
200			`uds_e <= '1';`
201			`lds_e <= '1';`
202			`clkena_e <= '0';`
203	8	tobiflex	`drive_data <= '0';`
204	2	tobiflex	`CASE S_state IS`
205	8	tobiflex	`WHEN "00" => null;`
206			`WHEN "01" => drive_data <= NOT wr;`
207	2	tobiflex	`WHEN "10" => as_e <= '0';`
208			`uds_e <= uds_in;`
209			`lds_e <= lds_in;`
210	8	tobiflex	`cpuIPL <= IPL;`
211			`drive_data <= NOT wr;`
212	2	tobiflex	`IF state="01" THEN`
213			`clkena_e <= '1';`
214			`waitm <= '0';`
215			`ELSE`
216			`clkena_e <= NOT dtack;`
217			`waitm <= dtack;`
218			`END IF;`
219	8	tobiflex	`WHEN OTHERS => null;`
220	2	tobiflex	`END CASE;`
221			`END IF;`
222			`END IF;`
223			`END PROCESS;`
224			`END;`

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[/] [tg68/] [trunk/] [VHDL/] [TG68.vhd] - Blame information for rev 10