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`include "aDefinitions.v"
 
/**********************************************************************************
Theia, Ray Cast Programable graphic Processing Unit.
Copyright (C) 2012  Diego Valverde (diego.valverde.g@gmail.com)
 
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License
as published by the Free Software Foundation; either version 2
of the License, or (at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
 
***********************************************************************************/
 
module Unit_Execution
(
input wire                               Clock,
input wire                               Reset,
input wire                               iEnable,
input wire [`INSTRUCTION_ADDR_WIDTH-1:0] iInstructionMem_WriteAddress,
input wire                               iInstructionMem_WriteEnable,
input wire [`INSTRUCTION_WIDTH-1:0]      iInstructionMem_WriteData,
//OMEM
output wire [`DATA_ROW_WIDTH-1:0]        oOMEMWriteAddress,
output wire [`DATA_ROW_WIDTH-1:0]        oOMEMWriteData,
output wire                              oOMEMWriteEnable,
//TMEM
output wire [`DATA_ROW_WIDTH-1:0]      oTMEMReadAddress,
input wire [`DATA_ROW_WIDTH-1:0]       iTMEMReadData,
input wire                             iTMEMDataAvailable,
output wire                            oTMEMDataRequest
);
 
wire [`INSTRUCTION_ADDR_WIDTH -1:0]                  wII_2_IM_IP0;
wire [`INSTRUCTION_ADDR_WIDTH -1:0]                  wII_2_IM_IP1;
wire [`INSTRUCTION_WIDTH-1:0]                        wIM_2_II_Instruction0;
wire [`INSTRUCTION_WIDTH-1:0]                        wIM_2_II_Instruction1;
wire [`DATA_ADDRESS_WIDTH-1:0]                       wII_2_RF_Addr0;
wire [`DATA_ADDRESS_WIDTH-1:0]                       wII_2_RF_Addr1;
wire [`DATA_ROW_WIDTH-1:0]                           wRF_2_II_Data0;
wire [`DATA_ROW_WIDTH-1:0]                           wRF_2_II_Data1;
wire [`NUMBER_OF_RSVR_STATIONS-1:0]                  wRS_2_II_Busy;
wire [`ISSUE_PACKET_SIZE-1:0]                        wIssueBus;
wire [`MOD_ISSUE_PACKET_SIZE-1:0]                    wModIssue;
wire [`NUMBER_OF_RSVR_STATIONS-1:0]                  wStationCommitRequest;
wire [`NUMBER_OF_RSVR_STATIONS-1:0]                  wStationCommitGrant;
wire [`COMMIT_PACKET_SIZE-1:0]                       wCommitBus;
wire [`MOD_COMMIT_PACKET_SIZE-1:0]                   wModCommitBus;
wire [`COMMIT_PACKET_SIZE-1:0]                       wCommitData_Adder0;
wire [`COMMIT_PACKET_SIZE-1:0]                       wCommitData_Adder1;
wire [`COMMIT_PACKET_SIZE-1:0]                       wCommitData_Div;
wire [`COMMIT_PACKET_SIZE-1:0]                       wCommitData_Mul;
wire [`COMMIT_PACKET_SIZE-1:0]                       wCommitData_Sqrt;
wire [`COMMIT_PACKET_SIZE-1:0]                       wCommitData_Logic;
wire [`COMMIT_PACKET_SIZE-1:0]                       wCommitData_IO;
wire                                                 wZeroFlag;
wire                                                 wSignFlag;
wire [`DATA_ADDRESS_WIDTH-1:0]                       wFrameOffset,wIndexRegister;
wire [`WIDTH-1:0]                                    wThreadControl;
 
// The Register File
RegisterFile # ( `DATA_ROW_WIDTH,`DATA_ADDRESS_WIDTH ) RF
(
 .Clock(                  Clock                            ),
 .Reset(                  Reset                            ),
 .iWriteEnable(           wCommitBus[`COMMIT_WE_RNG]       ),
 .iReadAddress0(          wII_2_RF_Addr0                   ),
 .iReadAddress1(          wII_2_RF_Addr1                   ),
 .iWriteAddress(          wCommitBus[`COMMIT_DST_RNG]      ),
 .oFrameOffset(           wFrameOffset                     ),
 .oIndexRegister(         wIndexRegister                   ),
 .oThreadControlRegister( wThreadControl                   ),
 .iData(                  wCommitBus[`COMMIT_DATA_RNG]     ),
 .oData0(                 wRF_2_II_Data0                   ),
 .oData1(                 wRF_2_II_Data1                   )
);
 
 
 
 
//Code bank 0
RAM_DUAL_READ_PORT  # (`INSTRUCTION_WIDTH, `INSTRUCTION_ADDR_WIDTH) IM
(
 .Clock(            Clock                              ),
 .iWriteEnable(      iInstructionMem_WriteEnable       ),
 .iReadAddress0(    wII0_IP0                           ),
 .iReadAddress1(    wII1_IP0                           ),
 .iWriteAddress(    iInstructionMem_WriteAddress       ),
 .iDataIn(          iInstructionMem_WriteData          ),
 .oDataOut0(        wInstrThread0                      ),
 .oDataOut1(        wInstrThread1                      )
);
 
 
//**********************************************
parameter MaxThreads = 3;
wire [MaxThreads-1:0] wDelay;
 
 
UPCOUNTER_POSEDGE # (MaxThreads) UP111
(
.Clock( Clock), .Reset( Reset),
.Initial(0),
.Enable(1'b1),
.Q(wDelay)
);
 
wire [`INSTRUCTION_ADDR_WIDTH -1:0]    wII0_IP0,wII0_IP1;
wire [`INSTRUCTION_ADDR_WIDTH -1:0]    wII1_IP0,wII1_IP1;
wire [`DATA_ADDRESS_WIDTH-1:0]                   wII0_RF_Addr0,wII0_RF_Addr1;
wire [`DATA_ADDRESS_WIDTH-1:0]                   wII1_RF_Addr0,wII1_RF_Addr1;
wire [`ISSUE_PACKET_SIZE-1:0]          wII0_IBus,wII1_IBus;
 
 
assign wII_2_RF_Addr0 = (wCurrentActiveThread[0]) ? wII0_RF_Addr0 : wII1_RF_Addr0;
 
assign wII_2_RF_Addr1 = (wCurrentActiveThread[0]) ? wII0_RF_Addr1 : wII1_RF_Addr1;
 
assign wIssueBus = (wCurrentActiveThread[0]) ? wII0_IBus: wII1_IBus;
 
 
wire [`MAX_THREADS-1:0] wCurrentActiveThread,wCurrentActiveThread_Pre,wCurrentActiveThread_Pre2;
 
CIRCULAR_SHIFTLEFT_POSEDGE_EX # ( `MAX_THREADS ) THREAD_SELECT
(
  .Clock( Clock ),
  .Reset( Reset ),
  .Initial(`MAX_THREADS'b1),
  .Enable( wDelay[0] /*& wDelay[1]*/ & wThreadControl[`SPR_TCONTROL0_MT_ENABLED]),
  .O( wCurrentActiveThread_Pre )
  );
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( `MAX_THREADS ) FFD12
(       Clock, Reset, 1'b1 , wCurrentActiveThread_Pre , wCurrentActiveThread_Pre2  );
 
assign wCurrentActiveThread = (wThreadControl[`SPR_TCONTROL0_MT_ENABLED]) ? wCurrentActiveThread_Pre2 : `MAX_THREADS'b1;
 
 
//**********************************************
wire [`INSTRUCTION_WIDTH-1:0] wInstrThread0;
//When the thread is inactive I want to keep this input just the way it was,
//sort of "time freezing"...
 
 
 
InstructionIssue II0
(
   .Clock(                Clock                   ),
        .Reset(                Reset                   ),
        .iEnable(             wCurrentActiveThread[0] &  iEnable),
        .iFrameOffset(         wFrameOffset            ),
        /* New Apr 06*/.iCodeOffset(   `INSTRUCTION_ADDR_WIDTH'b0     ),
        .iMtEnabled(wThreadControl[`SPR_TCONTROL0_MT_ENABLED]),
        .iIndexRegister(       wIndexRegister          ),
        .iInstruction0(        wInstrThread0           ),
//      .iInstruction1(        wIM_2_II_Instruction1   ),
        .iSourceData0(         wRF_2_II_Data0          ),
        .iSourceData1(         wRF_2_II_Data1          ),
        .iRStationBusy(        wRS_2_II_Busy           ),
        .iResultBcast(         wCommitBus              ),
        .iSignFlag(            wSignFlag               ),
        .iZeroFlag(            wZeroFlag               ),
        .iIgnoreResultBcast(   wResultBCastDst[7] &  wThreadControl[`SPR_TCONTROL0_MT_ENABLED] ),
        .oSourceAddress0(      wII0_RF_Addr0           ),//wII_2_RF_Addr0        ),
        .oSourceAddress1(      wII0_RF_Addr1           ),//wII_2_RF_Addr1        ),
        .oIssueBcast(          wII0_IBus               ),//wIssueBus             ), 
        .oIP0(                 wII0_IP0                )//wII_2_IM_IP0          ),
        //.oIP1(                 wII0_IP1                )//wII_2_IM_IP1          )
 
);
 
 
 
wire [`INSTRUCTION_WIDTH-1:0] wInstrThread1;
//When the thread is inactive I want to keep this input just the way it was,
//sort of "time freezing"...
 
//Add the offset to the thread instructions... 1 16 bit adder wasted :(
//assign wInstrThread1 = wInstrThread1_Pre;
 
wire [`DATA_ADDRESS_WIDTH-1:0] wResultBCastDst;
assign wResultBCastDst = wCommitBus[`COMMIT_DST_RNG];
 
 
InstructionIssue II1
(
   .Clock(                Clock                                                       ),
        .Reset(                Reset  ||  ~wThreadControl[`SPR_TCONTROL0_MT_ENABLED]       ),
        .iEnable(              wCurrentActiveThread[1]    & iEnable                        ),
        .iFrameOffset(         wFrameOffset                                                ),
         .iCodeOffset(         wThreadControl[`SPR_TCONTROL0_T0_INST_OFFSET_RNG]           ),
        .iMtEnabled(           wThreadControl[`SPR_TCONTROL0_MT_ENABLED]                   ),
        .iIndexRegister(       wIndexRegister        ),
        .iInstruction0(        wInstrThread1         ),
        .iSourceData0(         wRF_2_II_Data0        ),
        .iSourceData1(         wRF_2_II_Data1        ),
        .iRStationBusy(        wRS_2_II_Busy         ),
        .iResultBcast(         wCommitBus            ),
        .iSignFlag(            wSignFlag             ),
        .iZeroFlag(            wZeroFlag             ),
 
        .iIgnoreResultBcast(   ~wResultBCastDst[7]   ),
        .oSourceAddress0(      wII1_RF_Addr0 ),
        .oSourceAddress1(      wII1_RF_Addr1 ),
        .oIssueBcast(          wII1_IBus ),
        .oIP0(                 wII1_IP0 )
        //.oIP1(                 wII1_IP1 )
 
);
 
 
 
OperandModifiers SMU
(
        .Clock(                Clock                 ),
        .Reset(                Reset                 ),
        .iIssueBus(            wIssueBus             ),
        .iCommitBus(           wCommitBus            ),
        .oModIssue(            wModIssue             ),
        .oCommitBus(           wModCommitBus         )
 
);
 
assign wSignFlag = wCommitBus[`COMMIT_SIGN_X] & wCommitBus[`COMMIT_SIGN_Y] & wCommitBus[`COMMIT_SIGN_Z];
assign wZeroFlag = (wCommitBus[`COMMIT_DATA_RNG] == `DATA_ROW_WIDTH'b0) ? 1'b1 : 1'b0;
 
 
ADDER_STATION ADD_STA0
(
   .Clock(               Clock                       ),
        .Reset(               Reset                       ),
        .iId(                 `RS_ADD0                    ),
   .iIssueBus(           wModIssue                   ),
   .iCommitBus(          wModCommitBus               ),
        .oCommitData(         wCommitData_Adder0          ),
        .oCommitResquest(     wStationCommitRequest[0]    ),
        .iCommitGranted(      wStationCommitGrant[0]      ),
        .oBusy(               wRS_2_II_Busy[ 0 ]          )
 
);
 
ADDER_STATION ADD_STA1
(
   .Clock(               Clock                        ),
        .Reset(               Reset                        ),
        .iId(                 `RS_ADD1                     ),
   .iIssueBus(           wModIssue                    ),
   .iCommitBus(          wModCommitBus                ),
        .oCommitData(         wCommitData_Adder1           ),
        .oCommitResquest(     wStationCommitRequest[1]     ),
        .iCommitGranted(      wStationCommitGrant[1]       ),
        .oBusy(               wRS_2_II_Busy[ 1 ]           )
 
);
 
 
DIVISION_STATION DIV_STA
(
   .Clock(               Clock                       ),
        .Reset(               Reset                       ),
        .iId(                 `RS_DIV                     ),
   .iIssueBus(           wModIssue                   ),
   .iCommitBus(          wModCommitBus               ),
        .oCommitData(         wCommitData_Div             ),
        .oCommitResquest(     wStationCommitRequest[2]    ),
        .iCommitGranted(      wStationCommitGrant[2]      ),
        .oBusy(               wRS_2_II_Busy[2]            )
 
);
 
 
MUL_STATION MUL_STA
(
   .Clock(               Clock                       ),
        .Reset(               Reset                       ),
        .iId(                 `RS_MUL                     ),
   .iIssueBus(           wModIssue                   ),
   .iCommitBus(          wModCommitBus               ),
        .oCommitData(         wCommitData_Mul             ),
        .oCommitResquest(     wStationCommitRequest[3]    ),
        .iCommitGranted(      wStationCommitGrant[3]      ),
        .oBusy(               wRS_2_II_Busy[3]            )
 
);
 
 
SQRT_STATION SQRT_STA
(
   .Clock(               Clock                    ),
        .Reset(               Reset                    ),
        .iId(                 `RS_SQRT                 ),
   .iIssueBus(           wModIssue                ),
   .iCommitBus(          wModCommitBus            ),
        .oCommitData(         wCommitData_Sqrt         ),
        .oCommitResquest(     wStationCommitRequest[4] ),
        .iCommitGranted(      wStationCommitGrant[4]   ),
        .oBusy(               wRS_2_II_Busy[4]         )
 
);
 
 
 
LOGIC_STATION LOGIC_STA
(
   .Clock(               Clock                    ),
        .Reset(               Reset                    ),
        .iId(                 `RS_LOGIC                ),
   .iIssueBus(           wModIssue                ),
   .iCommitBus(          wModCommitBus            ),
        .oCommitData(         wCommitData_Logic        ),
        .oCommitResquest(     wStationCommitRequest[5] ),
        .iCommitGranted(      wStationCommitGrant[5]   ),
        .oBusy(               wRS_2_II_Busy[5]         )
 
);
 
IO_STATION IO_STA
(
   .Clock(               Clock                    ),
        .Reset(               Reset                    ),
        .iId(                 `RS_IO                  ),
   .iIssueBus(           wModIssue                ),
   .iCommitBus(          wModCommitBus            ),
        .oCommitData(         wCommitData_IO           ),
        .oCommitResquest(     wStationCommitRequest[6] ),
        .iCommitGranted(      wStationCommitGrant[6]   ),
        .oBusy(               wRS_2_II_Busy[6]         ),
        //OMEM
        .oOMEMWriteAddress(   oOMEMWriteAddress        ),
   .oOMEMWriteData(      oOMEMWriteData           ),
   .oOMEMWriteEnable(    oOMEMWriteEnable         ),
        //TMEM
        .oTMEMReadAddress(    oTMEMReadAddress         ),
   .iTMEMReadData(       iTMEMReadData            ),
   .iTMEMDataAvailable(  iTMEMDataAvailable       ),
   .oTMEMDataRequest(    oTMEMDataRequest         )
 
);
 
ROUND_ROBIN_7_ENTRIES ARB
//ROUND_ROBIN_6_ENTRIES ARB
(
.Clock( Clock ),
.Reset( Reset ),
.iRequest0( wStationCommitRequest[0] ),
.iRequest1( wStationCommitRequest[1] ),
.iRequest2( wStationCommitRequest[2] ),
.iRequest3( wStationCommitRequest[3] ),
.iRequest4( wStationCommitRequest[4] ),
.iRequest5( wStationCommitRequest[5] ),
.iRequest6( wStationCommitRequest[6] ),
.oGrant0(    wStationCommitGrant[0]   ),
.oGrant1(    wStationCommitGrant[1]   ),
.oGrant2(    wStationCommitGrant[2]   ),
.oGrant3(    wStationCommitGrant[3]   ),
.oGrant4(    wStationCommitGrant[4]   ),
.oGrant5(    wStationCommitGrant[5]   ),
.oGrant6(    wStationCommitGrant[6]   )
 
);
 
wire [5:0] wBusSelector_Tmp;
wire[2:0] wBusSelector;
DECODER_ONEHOT_2_BINARY DECODER
(
.iIn( wStationCommitGrant ),
.oOut(  wBusSelector_Tmp    )
);
assign wBusSelector = wBusSelector_Tmp[3:0];
 
MUXFULLPARALELL_3SEL_GENERIC # (`COMMIT_PACKET_SIZE ) MUX               //TODO I need one more entry for the IO
 (
 .Sel(wBusSelector),
 .I1(`COMMIT_PACKET_SIZE'b0),
 .I2(wCommitData_Adder0),
 .I3(wCommitData_Adder1),
 .I4(wCommitData_Div),
 .I5(wCommitData_Mul),
 .I6(wCommitData_Sqrt),
 .I7(wCommitData_Logic),
 .I8(wCommitData_IO        ),
 .O1(wCommitBus)
 );
 
 
endmodule

Line No.	Rev	Author	Line
1	213	diegovalve
2			`include "aDefinitions.v"
3
4	230	diegovalve	`/**********************************************************************************`
5			`Theia, Ray Cast Programable graphic Processing Unit.`
6			`Copyright (C) 2012 Diego Valverde (diego.valverde.g@gmail.com)`
7
8			`This program is free software; you can redistribute it and/or`
9			`modify it under the terms of the GNU General Public License`
10			`as published by the Free Software Foundation; either version 2`
11			`of the License, or (at your option) any later version.`
12
13			`This program is distributed in the hope that it will be useful,`
14			`but WITHOUT ANY WARRANTY; without even the implied warranty of`
15			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
16			`GNU General Public License for more details.`
17
18			`You should have received a copy of the GNU General Public License`
19			`along with this program; if not, write to the Free Software`
20			`Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.`
21
22	213	diegovalve	`***********************************************************************************/`
23
24			`module Unit_Execution`
25			`(`
26			`input wire Clock,`
27			`input wire Reset,`
28			`input wire iEnable,`
29			input wire [`INSTRUCTION_ADDR_WIDTH-1:0] iInstructionMem_WriteAddress,
30			`input wire iInstructionMem_WriteEnable,`
31			input wire [`INSTRUCTION_WIDTH-1:0] iInstructionMem_WriteData,
32	230	diegovalve	`//OMEM`
33			output wire [`DATA_ROW_WIDTH-1:0] oOMEMWriteAddress,
34			output wire [`DATA_ROW_WIDTH-1:0] oOMEMWriteData,
35			`output wire oOMEMWriteEnable,`
36			`//TMEM`
37			output wire [`DATA_ROW_WIDTH-1:0] oTMEMReadAddress,
38			input wire [`DATA_ROW_WIDTH-1:0] iTMEMReadData,
39			`input wire iTMEMDataAvailable,`
40			`output wire oTMEMDataRequest`
41	213	diegovalve	`);`
42
43			wire [`INSTRUCTION_ADDR_WIDTH -1:0] wII_2_IM_IP0;
44			wire [`INSTRUCTION_ADDR_WIDTH -1:0] wII_2_IM_IP1;
45			wire [`INSTRUCTION_WIDTH-1:0] wIM_2_II_Instruction0;
46			wire [`INSTRUCTION_WIDTH-1:0] wIM_2_II_Instruction1;
47			wire [`DATA_ADDRESS_WIDTH-1:0] wII_2_RF_Addr0;
48			wire [`DATA_ADDRESS_WIDTH-1:0] wII_2_RF_Addr1;
49			wire [`DATA_ROW_WIDTH-1:0] wRF_2_II_Data0;
50			wire [`DATA_ROW_WIDTH-1:0] wRF_2_II_Data1;
51			wire [`NUMBER_OF_RSVR_STATIONS-1:0] wRS_2_II_Busy;
52	230	diegovalve	wire [`ISSUE_PACKET_SIZE-1:0] wIssueBus;
53			wire [`MOD_ISSUE_PACKET_SIZE-1:0] wModIssue;
54	213	diegovalve	wire [`NUMBER_OF_RSVR_STATIONS-1:0] wStationCommitRequest;
55			wire [`NUMBER_OF_RSVR_STATIONS-1:0] wStationCommitGrant;
56			wire [`COMMIT_PACKET_SIZE-1:0] wCommitBus;
57			wire [`MOD_COMMIT_PACKET_SIZE-1:0] wModCommitBus;
58			wire [`COMMIT_PACKET_SIZE-1:0] wCommitData_Adder0;
59			wire [`COMMIT_PACKET_SIZE-1:0] wCommitData_Adder1;
60			wire [`COMMIT_PACKET_SIZE-1:0] wCommitData_Div;
61			wire [`COMMIT_PACKET_SIZE-1:0] wCommitData_Mul;
62			wire [`COMMIT_PACKET_SIZE-1:0] wCommitData_Sqrt;
63			wire [`COMMIT_PACKET_SIZE-1:0] wCommitData_Logic;
64			wire [`COMMIT_PACKET_SIZE-1:0] wCommitData_IO;
65			`wire wZeroFlag;`
66			`wire wSignFlag;`
67			wire [`DATA_ADDRESS_WIDTH-1:0] wFrameOffset,wIndexRegister;
68			wire [`WIDTH-1:0] wThreadControl;
69
70			`// The Register File`
71	230	diegovalve	RegisterFile # ( `DATA_ROW_WIDTH,`DATA_ADDRESS_WIDTH ) RF
72			`(`
73	213	diegovalve	`.Clock( Clock ),`
74	230	diegovalve	`.Reset( Reset ),`
75			.iWriteEnable( wCommitBus[`COMMIT_WE_RNG] ),
76			`.iReadAddress0( wII_2_RF_Addr0 ),`
77			`.iReadAddress1( wII_2_RF_Addr1 ),`
78	213	diegovalve	.iWriteAddress( wCommitBus[`COMMIT_DST_RNG] ),
79			`.oFrameOffset( wFrameOffset ),`
80			`.oIndexRegister( wIndexRegister ),`
81			`.oThreadControlRegister( wThreadControl ),`
82	230	diegovalve	.iData( wCommitBus[`COMMIT_DATA_RNG] ),
83			`.oData0( wRF_2_II_Data0 ),`
84			`.oData1( wRF_2_II_Data1 )`
85	213	diegovalve	`);`
86
87
88
89
90	230	diegovalve	`//Code bank 0`
91			RAM_DUAL_READ_PORT # (`INSTRUCTION_WIDTH, `INSTRUCTION_ADDR_WIDTH) IM
92			`(`
93			`.Clock( Clock ),`
94			`.iWriteEnable( iInstructionMem_WriteEnable ),`
95			`.iReadAddress0( wII0_IP0 ),`
96			`.iReadAddress1( wII1_IP0 ),`
97			`.iWriteAddress( iInstructionMem_WriteAddress ),`
98			`.iDataIn( iInstructionMem_WriteData ),`
99			`.oDataOut0( wInstrThread0 ),`
100			`.oDataOut1( wInstrThread1 )`
101	213	diegovalve	`);`
102
103
104			`//**********************************************`
105			`parameter MaxThreads = 3;`
106			`wire [MaxThreads-1:0] wDelay;`
107
108
109	230	diegovalve	`UPCOUNTER_POSEDGE # (MaxThreads) UP111`
110			`(`
111			`.Clock( Clock), .Reset( Reset),`
112	213	diegovalve	`.Initial(0),`
113			`.Enable(1'b1),`
114	230	diegovalve	`.Q(wDelay)`
115	213	diegovalve	`);`
116
117			wire [`INSTRUCTION_ADDR_WIDTH -1:0] wII0_IP0,wII0_IP1;
118			wire [`INSTRUCTION_ADDR_WIDTH -1:0] wII1_IP0,wII1_IP1;
119			wire [`DATA_ADDRESS_WIDTH-1:0] wII0_RF_Addr0,wII0_RF_Addr1;
120			wire [`DATA_ADDRESS_WIDTH-1:0] wII1_RF_Addr0,wII1_RF_Addr1;
121			wire [`ISSUE_PACKET_SIZE-1:0] wII0_IBus,wII1_IBus;
122
123
124			`assign wII_2_RF_Addr0 = (wCurrentActiveThread[0]) ? wII0_RF_Addr0 : wII1_RF_Addr0;`
125
126			`assign wII_2_RF_Addr1 = (wCurrentActiveThread[0]) ? wII0_RF_Addr1 : wII1_RF_Addr1;`
127
128			`assign wIssueBus = (wCurrentActiveThread[0]) ? wII0_IBus: wII1_IBus;`
129
130
131			wire [`MAX_THREADS-1:0] wCurrentActiveThread,wCurrentActiveThread_Pre,wCurrentActiveThread_Pre2;
132
133	230	diegovalve	CIRCULAR_SHIFTLEFT_POSEDGE_EX # ( `MAX_THREADS ) THREAD_SELECT
134	213	diegovalve	`(`
135	230	diegovalve	`.Clock( Clock ),`
136			`.Reset( Reset ),`
137			.Initial(`MAX_THREADS'b1),
138	213	diegovalve	.Enable( wDelay[0] /& wDelay[1]/ & wThreadControl[`SPR_TCONTROL0_MT_ENABLED]),
139			`.O( wCurrentActiveThread_Pre )`
140			`);`
141
142	230	diegovalve	FFD_POSEDGE_SYNCRONOUS_RESET # ( `MAX_THREADS ) FFD12
143	213	diegovalve	`( Clock, Reset, 1'b1 , wCurrentActiveThread_Pre , wCurrentActiveThread_Pre2 );`
144
145			assign wCurrentActiveThread = (wThreadControl[`SPR_TCONTROL0_MT_ENABLED]) ? wCurrentActiveThread_Pre2 : `MAX_THREADS'b1;
146
147
148			`//**********************************************`
149			wire [`INSTRUCTION_WIDTH-1:0] wInstrThread0;
150			`//When the thread is inactive I want to keep this input just the way it was,`
151			`//sort of "time freezing"...`
152
153
154
155			`InstructionIssue II0`
156			`(`
157	230	diegovalve	`.Clock( Clock ),`
158			`.Reset( Reset ),`
159	213	diegovalve	`.iEnable( wCurrentActiveThread[0] & iEnable),`
160			`.iFrameOffset( wFrameOffset ),`
161			/* New Apr 06*/.iCodeOffset( `INSTRUCTION_ADDR_WIDTH'b0 ),
162			.iMtEnabled(wThreadControl[`SPR_TCONTROL0_MT_ENABLED]),
163	230	diegovalve	`.iIndexRegister( wIndexRegister ),`
164	213	diegovalve	`.iInstruction0( wInstrThread0 ),`
165			`// .iInstruction1( wIM_2_II_Instruction1 ),`
166			`.iSourceData0( wRF_2_II_Data0 ),`
167			`.iSourceData1( wRF_2_II_Data1 ),`
168			`.iRStationBusy( wRS_2_II_Busy ),`
169	230	diegovalve	`.iResultBcast( wCommitBus ),`
170	213	diegovalve	`.iSignFlag( wSignFlag ),`
171			`.iZeroFlag( wZeroFlag ),`
172			.iIgnoreResultBcast( wResultBCastDst[7] & wThreadControl[`SPR_TCONTROL0_MT_ENABLED] ),
173	230	diegovalve	`.oSourceAddress0( wII0_RF_Addr0 ),//wII_2_RF_Addr0 ),`
174	213	diegovalve	`.oSourceAddress1( wII0_RF_Addr1 ),//wII_2_RF_Addr1 ),`
175			`.oIssueBcast( wII0_IBus ),//wIssueBus ),`
176			`.oIP0( wII0_IP0 )//wII_2_IM_IP0 ),`
177	230	diegovalve	`//.oIP1( wII0_IP1 )//wII_2_IM_IP1 )`
178	213	diegovalve
179			`);`
180
181
182
183			wire [`INSTRUCTION_WIDTH-1:0] wInstrThread1;
184			`//When the thread is inactive I want to keep this input just the way it was,`
185			`//sort of "time freezing"...`
186
187			`//Add the offset to the thread instructions... 1 16 bit adder wasted :(`
188			`//assign wInstrThread1 = wInstrThread1_Pre;`
189
190			wire [`DATA_ADDRESS_WIDTH-1:0] wResultBCastDst;
191			assign wResultBCastDst = wCommitBus[`COMMIT_DST_RNG];
192
193
194			`InstructionIssue II1`
195			`(`
196			`.Clock( Clock ),`
197			.Reset( Reset \|\| ~wThreadControl[`SPR_TCONTROL0_MT_ENABLED] ),
198			`.iEnable( wCurrentActiveThread[1] & iEnable ),`
199			`.iFrameOffset( wFrameOffset ),`
200			.iCodeOffset( wThreadControl[`SPR_TCONTROL0_T0_INST_OFFSET_RNG] ),
201			.iMtEnabled( wThreadControl[`SPR_TCONTROL0_MT_ENABLED] ),
202	230	diegovalve	`.iIndexRegister( wIndexRegister ),`
203	213	diegovalve	`.iInstruction0( wInstrThread1 ),`
204			`.iSourceData0( wRF_2_II_Data0 ),`
205			`.iSourceData1( wRF_2_II_Data1 ),`
206			`.iRStationBusy( wRS_2_II_Busy ),`
207	230	diegovalve	`.iResultBcast( wCommitBus ),`
208	213	diegovalve	`.iSignFlag( wSignFlag ),`
209			`.iZeroFlag( wZeroFlag ),`
210
211			`.iIgnoreResultBcast( ~wResultBCastDst[7] ),`
212	230	diegovalve	`.oSourceAddress0( wII1_RF_Addr0 ),`
213	213	diegovalve	`.oSourceAddress1( wII1_RF_Addr1 ),`
214			`.oIssueBcast( wII1_IBus ),`
215			`.oIP0( wII1_IP0 )`
216	230	diegovalve	`//.oIP1( wII1_IP1 )`
217	213	diegovalve
218			`);`
219
220
221
222			`OperandModifiers SMU`
223			`(`
224	230	diegovalve	`.Clock( Clock ),`
225	213	diegovalve	`.Reset( Reset ),`
226			`.iIssueBus( wIssueBus ),`
227			`.iCommitBus( wCommitBus ),`
228			`.oModIssue( wModIssue ),`
229			`.oCommitBus( wModCommitBus )`
230
231			`);`
232
233			assign wSignFlag = wCommitBus[`COMMIT_SIGN_X] & wCommitBus[`COMMIT_SIGN_Y] & wCommitBus[`COMMIT_SIGN_Z];
234			assign wZeroFlag = (wCommitBus[`COMMIT_DATA_RNG] == `DATA_ROW_WIDTH'b0) ? 1'b1 : 1'b0;
235
236
237			`ADDER_STATION ADD_STA0`
238			`(`
239	230	diegovalve	`.Clock( Clock ),`
240	213	diegovalve	`.Reset( Reset ),`
241			.iId( `RS_ADD0 ),
242			`.iIssueBus( wModIssue ),`
243			`.iCommitBus( wModCommitBus ),`
244			`.oCommitData( wCommitData_Adder0 ),`
245			`.oCommitResquest( wStationCommitRequest[0] ),`
246			`.iCommitGranted( wStationCommitGrant[0] ),`
247			`.oBusy( wRS_2_II_Busy[ 0 ] )`
248
249			`);`
250
251			`ADDER_STATION ADD_STA1`
252			`(`
253	230	diegovalve	`.Clock( Clock ),`
254	213	diegovalve	`.Reset( Reset ),`
255			.iId( `RS_ADD1 ),
256			`.iIssueBus( wModIssue ),`
257			`.iCommitBus( wModCommitBus ),`
258			`.oCommitData( wCommitData_Adder1 ),`
259			`.oCommitResquest( wStationCommitRequest[1] ),`
260			`.iCommitGranted( wStationCommitGrant[1] ),`
261			`.oBusy( wRS_2_II_Busy[ 1 ] )`
262
263			`);`
264
265
266			`DIVISION_STATION DIV_STA`
267			`(`
268	230	diegovalve	`.Clock( Clock ),`
269	213	diegovalve	`.Reset( Reset ),`
270			.iId( `RS_DIV ),
271			`.iIssueBus( wModIssue ),`
272			`.iCommitBus( wModCommitBus ),`
273			`.oCommitData( wCommitData_Div ),`
274			`.oCommitResquest( wStationCommitRequest[2] ),`
275			`.iCommitGranted( wStationCommitGrant[2] ),`
276			`.oBusy( wRS_2_II_Busy[2] )`
277
278			`);`
279
280
281			`MUL_STATION MUL_STA`
282			`(`
283	230	diegovalve	`.Clock( Clock ),`
284	213	diegovalve	`.Reset( Reset ),`
285			.iId( `RS_MUL ),
286			`.iIssueBus( wModIssue ),`
287			`.iCommitBus( wModCommitBus ),`
288			`.oCommitData( wCommitData_Mul ),`
289			`.oCommitResquest( wStationCommitRequest[3] ),`
290			`.iCommitGranted( wStationCommitGrant[3] ),`
291			`.oBusy( wRS_2_II_Busy[3] )`
292
293			`);`
294
295
296			`SQRT_STATION SQRT_STA`
297			`(`
298	230	diegovalve	`.Clock( Clock ),`
299	213	diegovalve	`.Reset( Reset ),`
300			.iId( `RS_SQRT ),
301			`.iIssueBus( wModIssue ),`
302			`.iCommitBus( wModCommitBus ),`
303			`.oCommitData( wCommitData_Sqrt ),`
304			`.oCommitResquest( wStationCommitRequest[4] ),`
305			`.iCommitGranted( wStationCommitGrant[4] ),`
306			`.oBusy( wRS_2_II_Busy[4] )`
307
308			`);`
309
310
311
312			`LOGIC_STATION LOGIC_STA`
313			`(`
314	230	diegovalve	`.Clock( Clock ),`
315	213	diegovalve	`.Reset( Reset ),`
316			.iId( `RS_LOGIC ),
317			`.iIssueBus( wModIssue ),`
318			`.iCommitBus( wModCommitBus ),`
319			`.oCommitData( wCommitData_Logic ),`
320			`.oCommitResquest( wStationCommitRequest[5] ),`
321			`.iCommitGranted( wStationCommitGrant[5] ),`
322			`.oBusy( wRS_2_II_Busy[5] )`
323
324			`);`
325
326			`IO_STATION IO_STA`
327			`(`
328	230	diegovalve	`.Clock( Clock ),`
329	213	diegovalve	`.Reset( Reset ),`
330			.iId( `RS_IO ),
331			`.iIssueBus( wModIssue ),`
332			`.iCommitBus( wModCommitBus ),`
333			`.oCommitData( wCommitData_IO ),`
334			`.oCommitResquest( wStationCommitRequest[6] ),`
335			`.iCommitGranted( wStationCommitGrant[6] ),`
336			`.oBusy( wRS_2_II_Busy[6] ),`
337	230	diegovalve	`//OMEM`
338			`.oOMEMWriteAddress( oOMEMWriteAddress ),`
339			`.oOMEMWriteData( oOMEMWriteData ),`
340			`.oOMEMWriteEnable( oOMEMWriteEnable ),`
341			`//TMEM`
342			`.oTMEMReadAddress( oTMEMReadAddress ),`
343			`.iTMEMReadData( iTMEMReadData ),`
344			`.iTMEMDataAvailable( iTMEMDataAvailable ),`
345			`.oTMEMDataRequest( oTMEMDataRequest )`
346	213	diegovalve
347			`);`
348
349			`ROUND_ROBIN_7_ENTRIES ARB`
350			`//ROUND_ROBIN_6_ENTRIES ARB`
351			`(`
352			`.Clock( Clock ),`
353			`.Reset( Reset ),`
354			`.iRequest0( wStationCommitRequest[0] ),`
355			`.iRequest1( wStationCommitRequest[1] ),`
356			`.iRequest2( wStationCommitRequest[2] ),`
357			`.iRequest3( wStationCommitRequest[3] ),`
358			`.iRequest4( wStationCommitRequest[4] ),`
359			`.iRequest5( wStationCommitRequest[5] ),`
360			`.iRequest6( wStationCommitRequest[6] ),`
361			`.oGrant0( wStationCommitGrant[0] ),`
362			`.oGrant1( wStationCommitGrant[1] ),`
363			`.oGrant2( wStationCommitGrant[2] ),`
364			`.oGrant3( wStationCommitGrant[3] ),`
365			`.oGrant4( wStationCommitGrant[4] ),`
366			`.oGrant5( wStationCommitGrant[5] ),`
367			`.oGrant6( wStationCommitGrant[6] )`
368
369			`);`
370
371	230	diegovalve	`wire [5:0] wBusSelector_Tmp;`
372			`wire[2:0] wBusSelector;`
373	213	diegovalve	`DECODER_ONEHOT_2_BINARY DECODER`
374			`(`
375			`.iIn( wStationCommitGrant ),`
376	230	diegovalve	`.oOut( wBusSelector_Tmp )`
377	213	diegovalve	`);`
378	230	diegovalve	`assign wBusSelector = wBusSelector_Tmp[3:0];`
379	213	diegovalve
380	230	diegovalve	MUXFULLPARALELL_3SEL_GENERIC # (`COMMIT_PACKET_SIZE ) MUX //TODO I need one more entry for the IO
381			`(`
382			`.Sel(wBusSelector),`
383	213	diegovalve	.I1(`COMMIT_PACKET_SIZE'b0),
384			`.I2(wCommitData_Adder0),`
385			`.I3(wCommitData_Adder1),`
386			`.I4(wCommitData_Div),`
387			`.I5(wCommitData_Mul),`
388			`.I6(wCommitData_Sqrt),`
389	230	diegovalve	`.I7(wCommitData_Logic),`
390			`.I8(wCommitData_IO ),`
391			`.O1(wCommitBus)`
392	213	diegovalve	`);`
393
394
395			`endmodule`

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