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[/] [tiny_tate_bilinear_pairing/] [trunk/] [group_size_is_151_bits/] [rtl/] [pairing.v] - Blame information for rev 15

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Line No. Rev Author Line
1 5 homer.hsin
/*
2 15 homer.hsin
 * Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
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 *
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 * Licensed under the Apache License, Version 2.0 (the "License");
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 * you may not use this file except in compliance with the License.
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 * You may obtain a copy of the License at
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 *
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 * http://www.apache.org/licenses/LICENSE-2.0
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 *
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 * Unless required by applicable law or agreed to in writing, software
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 * distributed under the License is distributed on an "AS IS" BASIS,
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 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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 * See the License for the specific language governing permissions and
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 * limitations under the License.
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 */
16 5 homer.hsin
 
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module pairing(clk, reset, sel, addr, w, update, ready, i, o, done);
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   input clk;
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   input reset; // for the arithmethic core
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   input sel;
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   input [5:0] addr;
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   input w;
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   input update; // update reg_in & reg_out
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   input ready;  // shift reg_in & reg_out
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   input i;
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   output o;
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   output done;
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   reg [197:0] reg_in, reg_out;
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   wire [197:0] out;
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   assign o = reg_out[0];
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   tiny
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      tiny0 (clk, reset, sel, addr, w, reg_in, out, done);
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   always @ (posedge clk) // write LSB firstly
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      if (update) reg_in <= 0;
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      else if (ready) reg_in <= {i,reg_in[197:1]};
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   always @ (posedge clk) // read LSB firstly
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      if (update) reg_out <= out;
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      else if (ready) reg_out <= reg_out>>1;
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endmodule

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