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[/] [tiny_tate_bilinear_pairing/] [trunk/] [group_size_is_151_bits/] [testbench/] [test_const.v] - Blame information for rev 15

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1 15 homer.hsin
/*
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 * Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
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 *
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 * Licensed under the Apache License, Version 2.0 (the "License");
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 * you may not use this file except in compliance with the License.
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 * You may obtain a copy of the License at
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 *
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 * http://www.apache.org/licenses/LICENSE-2.0
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 *
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 * Unless required by applicable law or agreed to in writing, software
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 * distributed under the License is distributed on an "AS IS" BASIS,
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 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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 * See the License for the specific language governing permissions and
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 * limitations under the License.
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 */
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`timescale 1ns / 1ps
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`define P 20 // clock period
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module test_const;
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        // Inputs
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    reg clk;
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        reg [5:0] addr;
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        // Outputs
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        wire [197:0] out;
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        wire effective;
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    reg [197:0] w_out;
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    reg w_effective;
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        // Instantiate the Unit Under Test (UUT)
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        const uut (
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        .clk(clk),
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                .addr(addr),
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                .out(out),
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                .effective(effective)
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        );
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        initial begin
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                // Initialize Inputs
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                addr = 0; clk = 0;
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                // Wait 100 ns for global reset to finish
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                #100;
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                // Add stimulus here
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        @ (negedge clk);
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        addr = 1; w_out = 0; w_effective = 1;
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        #(`P); check;
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        addr = 2; w_out = 1;
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        #(`P); check;
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        addr = 4; w_out = {6'b000101, 192'd0};
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        #(`P); check;
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        addr = 8; w_out = {6'b001001, 192'd0};
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        #(`P); check;
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        addr = 16; w_out = {6'b010101, 192'd0};
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        #(`P); check;
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        addr = 0; w_out = 0; w_effective = 0;
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        #(`P); check;
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        $display("Good");
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        $finish;
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        end
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    initial #100 forever #(`P/2) clk = ~clk;
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    task check;
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      begin
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        if (out !== w_out || effective !== w_effective)
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            $display("E %d %h %h", addr, out, w_out);
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      end
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    endtask
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endmodule
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