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[/] [tosnet/] [trunk/] [gateware/] [MicroBlaze_Peripheral_rev3_2/] [pcores/] [tosnet_v3_20_a/] [data/] [tosnet_v2_1_0.mpd] - Blame information for rev 5

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Line No. Rev Author Line
1 5 sonicwave 
###################################################################
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##
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## Name     : tosnet
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## Desc     : Microprocessor Peripheral Description
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##          : Automatically generated by PsfUtility
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##
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###################################################################
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BEGIN tosnet
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## Peripheral Options
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OPTION IPTYPE = PERIPHERAL
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OPTION IMP_NETLIST = TRUE
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OPTION HDL = VHDL
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OPTION IP_GROUP = MICROBLAZE:PPC:USER
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OPTION STYLE = MIX
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OPTION RUN_NGCBUILD = TRUE
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## Bus Interfaces
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BUS_INTERFACE BUS = SPLB, BUS_STD = PLBV46, BUS_TYPE = SLAVE
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## Generics for VHDL or Parameters for Verilog
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PARAMETER C_REG_ENABLE = 0b00000000, DT = std_logic_vector(7 downto 0)
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PARAMETER C_NODE_ID = 0, DT = INTEGER
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PARAMETER C_MAX_SKIPPED_READS = 0, DT = INTEGER
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PARAMETER C_MAX_SKIPPED_WRITES = 0, DT = INTEGER
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PARAMETER C_WATCHDOG_THRESHOLD = 16384, DT = INTEGER
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PARAMETER C_DISABLE_MASTER = 0, DT = std_logic
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PARAMETER C_DISABLE_SLAVE = 0, DT = std_logic
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PARAMETER C_DISABLE_ASYNC = 0, DT = std_logic
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PARAMETER C_BASEADDR = 0xffffffff, DT = std_logic_vector, PAIR = C_HIGHADDR, ADDRESS = BASE, BUS = SPLB
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PARAMETER C_HIGHADDR = 0x00000000, DT = std_logic_vector, PAIR = C_BASEADDR, ADDRESS = HIGH, BUS = SPLB
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PARAMETER C_SPLB_AWIDTH = 32, DT = INTEGER, BUS = SPLB
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PARAMETER C_SPLB_DWIDTH = 128, DT = INTEGER, BUS = SPLB
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PARAMETER C_SPLB_NUM_MASTERS = 8, DT = INTEGER, BUS = SPLB
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PARAMETER C_SPLB_MID_WIDTH = 3, DT = INTEGER, BUS = SPLB
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PARAMETER C_SPLB_NATIVE_DWIDTH = 32, DT = INTEGER, BUS = SPLB
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PARAMETER C_SPLB_P2P = 0, DT = INTEGER, BUS = SPLB
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PARAMETER C_SPLB_SUPPORT_BURSTS = 0, DT = INTEGER, BUS = SPLB
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PARAMETER C_SPLB_SMALLEST_MASTER = 32, DT = INTEGER, BUS = SPLB
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PARAMETER C_SPLB_CLK_PERIOD_PS = 10000, DT = INTEGER, BUS = SPLB
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PARAMETER C_INCLUDE_DPHASE_TIMER = 0, DT = INTEGER
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PARAMETER C_FAMILY = virtex5, DT = STRING
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PARAMETER C_MEM0_BASEADDR = 0xffffffff, DT = std_logic_vector, PAIR = C_MEM0_HIGHADDR, ADDRESS = BASE, BUS = SPLB, ADDR_TYPE = MEMORY
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PARAMETER C_MEM0_HIGHADDR = 0x00000000, DT = std_logic_vector, PAIR = C_MEM0_BASEADDR, ADDRESS = HIGH, BUS = SPLB, ADDR_TYPE = MEMORY
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## Ports
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PORT sig_in = "", DIR = I
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PORT sig_out = "", DIR = O
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PORT clk_50M = "", DIR = I
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PORT sync_strobe = "", DIR = O, SIGIS = INTERRUPT, SENSITIVITY = EDGE_RISING
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PORT system_halt = "", DIR = O, SIGIS = INTERRUPT, SENSITIVITY = LEVEL_HIGH
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PORT SPLB_Clk = "", DIR = I, SIGIS = CLK, BUS = SPLB
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PORT SPLB_Rst = SPLB_Rst, DIR = I, SIGIS = RST, BUS = SPLB
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PORT PLB_ABus = PLB_ABus, DIR = I, VEC = [0:31], BUS = SPLB
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PORT PLB_UABus = PLB_UABus, DIR = I, VEC = [0:31], BUS = SPLB
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PORT PLB_PAValid = PLB_PAValid, DIR = I, BUS = SPLB
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PORT PLB_SAValid = PLB_SAValid, DIR = I, BUS = SPLB
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PORT PLB_rdPrim = PLB_rdPrim, DIR = I, BUS = SPLB
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PORT PLB_wrPrim = PLB_wrPrim, DIR = I, BUS = SPLB
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PORT PLB_masterID = PLB_masterID, DIR = I, VEC = [0:(C_SPLB_MID_WIDTH-1)], BUS = SPLB
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PORT PLB_abort = PLB_abort, DIR = I, BUS = SPLB
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PORT PLB_busLock = PLB_busLock, DIR = I, BUS = SPLB
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PORT PLB_RNW = PLB_RNW, DIR = I, BUS = SPLB
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PORT PLB_BE = PLB_BE, DIR = I, VEC = [0:((C_SPLB_DWIDTH/8)-1)], BUS = SPLB
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PORT PLB_MSize = PLB_MSize, DIR = I, VEC = [0:1], BUS = SPLB
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PORT PLB_size = PLB_size, DIR = I, VEC = [0:3], BUS = SPLB
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PORT PLB_type = PLB_type, DIR = I, VEC = [0:2], BUS = SPLB
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PORT PLB_lockErr = PLB_lockErr, DIR = I, BUS = SPLB
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PORT PLB_wrDBus = PLB_wrDBus, DIR = I, VEC = [0:(C_SPLB_DWIDTH-1)], BUS = SPLB
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PORT PLB_wrBurst = PLB_wrBurst, DIR = I, BUS = SPLB
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PORT PLB_rdBurst = PLB_rdBurst, DIR = I, BUS = SPLB
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PORT PLB_wrPendReq = PLB_wrPendReq, DIR = I, BUS = SPLB
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PORT PLB_rdPendReq = PLB_rdPendReq, DIR = I, BUS = SPLB
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PORT PLB_wrPendPri = PLB_wrPendPri, DIR = I, VEC = [0:1], BUS = SPLB
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PORT PLB_rdPendPri = PLB_rdPendPri, DIR = I, VEC = [0:1], BUS = SPLB
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PORT PLB_reqPri = PLB_reqPri, DIR = I, VEC = [0:1], BUS = SPLB
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PORT PLB_TAttribute = PLB_TAttribute, DIR = I, VEC = [0:15], BUS = SPLB
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PORT Sl_addrAck = Sl_addrAck, DIR = O, BUS = SPLB
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PORT Sl_SSize = Sl_SSize, DIR = O, VEC = [0:1], BUS = SPLB
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PORT Sl_wait = Sl_wait, DIR = O, BUS = SPLB
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PORT Sl_rearbitrate = Sl_rearbitrate, DIR = O, BUS = SPLB
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PORT Sl_wrDAck = Sl_wrDAck, DIR = O, BUS = SPLB
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PORT Sl_wrComp = Sl_wrComp, DIR = O, BUS = SPLB
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PORT Sl_wrBTerm = Sl_wrBTerm, DIR = O, BUS = SPLB
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PORT Sl_rdDBus = Sl_rdDBus, DIR = O, VEC = [0:(C_SPLB_DWIDTH-1)], BUS = SPLB
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PORT Sl_rdWdAddr = Sl_rdWdAddr, DIR = O, VEC = [0:3], BUS = SPLB
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PORT Sl_rdDAck = Sl_rdDAck, DIR = O, BUS = SPLB
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PORT Sl_rdComp = Sl_rdComp, DIR = O, BUS = SPLB
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PORT Sl_rdBTerm = Sl_rdBTerm, DIR = O, BUS = SPLB
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PORT Sl_MBusy = Sl_MBusy, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
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PORT Sl_MWrErr = Sl_MWrErr, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
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PORT Sl_MRdErr = Sl_MRdErr, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
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PORT Sl_MIRQ = Sl_MIRQ, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
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END

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