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[/] [tosnet/] [trunk/] [gateware/] [TosNet_rev3_2/] [tdl_app_sync.vhd] - Blame information for rev 2

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1 2 sonicwave
----------------------------------------------------------------------------------
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-- Company:             University of Southern Denmark
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-- Engineer:            Simon Falsig
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-- 
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-- Create Date:         7/3/2010 
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-- Design Name          TosNet
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-- Module Name:         app_sync - Behavioral 
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-- File Name:           app_sync.vhd
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-- Project Name:        TosNet
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-- Target Devices:      Spartan3/6
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-- Tool versions:       Xilinx ISE 12.2
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-- Description:         The synchronization module handles the synchronization strobes
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--                                      that are emitted at the end of each cycle. The strobe is
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--                                      delayed for a fixed interval, depending on the node address
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--                                      (which specifies the position of the node in the network
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--                                      relative to the master), which causes the strobe to be emitted
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--                                      at the same time in all nodes.
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--
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-- Revision: 
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-- Revision 3.2 -       Initial release
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--
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-- Copyright 2010
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--
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-- This module is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU Lesser General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This module is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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-- GNU Lesser General Public License for more details.
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--
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-- You should have received a copy of the GNU Lesser General Public License
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-- along with this module.  If not, see <http://www.gnu.org/licenses/>.
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity tdl_app_sync is
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        Port (  app_enable                              : in    STD_LOGIC;
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                        app_data_in                             : in    STD_LOGIC_VECTOR(7 downto 0);
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                        app_data_in_strobe              : in    STD_LOGIC;
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                        app_data_in_enable              : in    STD_LOGIC;
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                        app_data_out                    : out   STD_LOGIC_VECTOR(7 downto 0);
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                        app_data_out_strobe             : out   STD_LOGIC;
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                        app_data_out_enable             : out   STD_LOGIC;
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                        app_buffer_full                 : in    STD_LOGIC;
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                        app_packet_error                : in    STD_LOGIC;
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                        app_force_packet_error  : out   STD_LOGIC;
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                        app_cmd_valid                   : in    STD_LOGIC;
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                        app_sync_strobe                 : out   STD_LOGIC;
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                        app_is_master                   : in    STD_LOGIC;
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                        app_dsc_done                    : out   STD_LOGIC;
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                        app_node_id                             : in    STD_LOGIC_VECTOR(3 downto 0);
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                        app_node_count                  : in    STD_LOGIC_VECTOR(3 downto 0);
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                        app_node_address                : in    STD_LOGIC_VECTOR(3 downto 0);
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                        app_clk                                 : in    STD_LOGIC;
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                        app_reset                               : in    STD_LOGIC);
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end tdl_app_sync;
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architecture Behavioral of tdl_app_sync is
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        type STATES is (OFF, CALC_SYNC_DELAY, SYNC_READY, SYNC_ONLINE, SYNC_RUNNING, SYNC_SET);
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        signal state                                    : STATES := OFF;
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        signal next_state                               : STATES := OFF;
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        signal last_data_in_enable              : STD_LOGIC;
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        signal counter                                  : STD_LOGIC_VECTOR(4 downto 0) := "00000";
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        signal delay_counter                    : STD_LOGIC_VECTOR(11 downto 0) := "000000000000";
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        signal delay_current_node               : STD_LOGIC_VECTOR(11 downto 0) := "000000000000";
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        constant delay_pr_node                  : STD_LOGIC_VECTOR(11 downto 0) := "000100101100";
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begin
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        process(app_clk)
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        begin
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                if(app_clk = '1' and app_clk'EVENT) then
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                        if(app_reset = '1') then
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                                state <= OFF;
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                        else
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                                state <= next_state;
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                        end if;
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                        if(state = next_state) then
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                                counter <= counter + 1;
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                        else
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                                counter <= "00000";
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                        end if;
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                        case state is
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                                when OFF =>
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                                        delay_counter <= "000000000000";
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                                        delay_current_node <= "000000000000";
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                                        app_dsc_done <= '0';
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                                        last_data_in_enable <= '0';
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                                        app_sync_strobe <= '0';
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                                when CALC_SYNC_DELAY =>
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                                        if(app_is_master = '1') then
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                                                delay_current_node <= "000000000000";
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                                        elsif(counter = 0) then
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                                                delay_current_node <= delay_pr_node;
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                                        else
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                                                delay_current_node <= delay_current_node + delay_pr_node;
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                                        end if;
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                                when SYNC_READY =>
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                                        if(app_is_master = '1') then
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                                                app_sync_strobe <= '1';                 --If this is the master node, send out a single sync pulse to get the application started...
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                                        end if;
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                                when SYNC_ONLINE =>
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                                        app_dsc_done <= '1';
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                                        app_sync_strobe <= '0';
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                                        delay_counter <= "000000000000";
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                                when SYNC_RUNNING =>
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                                        delay_counter <= delay_counter + 1;
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                                when SYNC_SET =>
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                                        app_sync_strobe <= '1';
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                        end case;
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                        last_data_in_enable <= app_data_in_enable;
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                end if;
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        end process;
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        process(state, app_enable, counter, app_node_count, app_node_address, delay_counter, delay_current_node, app_data_in_enable, last_data_in_enable)
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        begin
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                case state is
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                        when OFF =>
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                                if(app_enable = '1') then
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                                        next_state <= CALC_SYNC_DELAY;
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                                else
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                                        next_state <= OFF;
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                                end if;
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                        when CALC_SYNC_DELAY =>
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                                if(counter = app_node_count - app_node_address - 1) then
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                                        next_state <= SYNC_READY;
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                                else
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                                        next_state <= CALC_SYNC_DELAY;
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                                end if;
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                        when SYNC_READY =>                                                                      --Make sure that the current transmission is done before going online (if not the enable signal from the received sync_set will trigger the sync mechanism... which is kinda not what we want)
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                                if(app_data_in_enable = '0') then
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                                        next_state <= SYNC_ONLINE;
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                                else
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                                        next_state <= SYNC_READY;
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                                end if;
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                        when SYNC_ONLINE =>
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                                if(app_data_in_enable = '0' and last_data_in_enable = '1') then
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                                        next_state <= SYNC_RUNNING;
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                                else
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                                        next_state <= SYNC_ONLINE;
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                                end if;
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                        when SYNC_RUNNING =>
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                                if(app_data_in_enable = '1') then                       --If app_data_in_enable goes high before the sync_strobe something bad is happening - but let's just make sure we don't make it worse by sending a sync_strobe in the middle of a (probably erroneous) transmission...
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                                        next_state <= SYNC_ONLINE;
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                                elsif(delay_counter = delay_current_node) then
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                                        next_state <= SYNC_SET;
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                                else
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                                        next_state <= SYNC_RUNNING;
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                                end if;
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                        when SYNC_SET =>
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                                next_state <= SYNC_ONLINE;
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                end case;
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        end process;
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end Behavioral;
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