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[/] [trigonometric_functions_in_double_fpu/] [trunk/] [verilog/] [divider.v] - Blame information for rev 17

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1 17 draunzer
/////////////////////////////////////////////////////////////////////
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////                                                             ////
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////                                                          ////
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////  Trigonometric functions using double precision Floating Point Unit        ////
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////                                                             ////
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////  Author: Muni Aditya                                        ////
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////          muni_aditya@yahoo.com                                ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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//// Copyright (C) 2013 Muni Aditya                           ////
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////                  muni_aditya@yahoo.com                        ////
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////                                                             ////
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//// This source file may be used and distributed without        ////
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//// restriction provided that this copyright statement is not   ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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////                                                             ////
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////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
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//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
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//// POSSIBILITY OF SUCH DAMAGE.                                 ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
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`timescale 1ns / 100ps
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`define INPUT_WIDTH 32
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module dividor (clk, inp, rst, out);
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  input clk;
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  input [`INPUT_WIDTH-1:0] inp;
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  input rst;
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//////////////inputs/////////////////
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  output  reg [`INPUT_WIDTH-1:0] out;
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//////////////output/////////////////  
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 wire [`INPUT_WIDTH-1:0]DIVISOR = `INPUT_WIDTH'd360 ;
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  always @ (posedge clk)
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// modulo division 
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   if(rst)
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     out <= 8'd0 ;
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   else
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    out <= inp % DIVISOR ;
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 endmodule
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