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[/] [uart16550/] [tags/] [initial/] [verilog/] [FIFO_inc.v] - Blame information for rev 106

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/// File:  FIFO_inc.v
/// Author: Jacob Gorban, Flextronics Semiconductor
///
/// This file is FIFO logic. It should be included in your FIFO.
/// A module envelope should be created in the parent file.
/// The reason for creating this in a included module is being able to create custom FIFOs,
/// like modules with different ports or additional logic on the FIFO except the standard, easily
 
// FIFO parameters
parameter fifo_width = `FIFO_WIDTH;
parameter fifo_depth = `FIFO_DEPTH;
parameter fifo_pointer_w = `FIFO_POINTER_W;
parameter fifo_counter_w = `FIFO_COUNTER_W;
 
input                           clk;
input                           wb_rst_i;
input                           push;
input                           pop;
input   [fifo_width-1:0] data_in;
output  [fifo_width-1:0] data_out;
output                          overrun;
output                          underrun;
output  [fifo_counter_w-1:0]     count;
 
wire    [fifo_width-1:0] data_out;
 
// FIFO itself
reg     [fifo_width-1:0] fifo[fifo_depth-1:0];
 
// FIFO pointers
reg     [fifo_pointer_w-1:0]     top;
reg     [fifo_pointer_w-1:0]     bottom;
 
reg     [fifo_counter_w-1:0]     count;
reg                             overrun;
reg                             underrun;
 
wire [fifo_pointer_w-1:0] top_plus_1 = top + 1;
 
//always @(posedge clk or posedge wb_rst_i) // synchronous FIFO
always @(posedge push or posedge pop or posedge wb_rst_i)  // asynchronous FIFO
begin
        if (wb_rst_i==1)
        begin
                top             <= #1 0;
                bottom          <= #1 0;
                underrun        <= #1 0;
                overrun         <= #1 0;
                count           <= #1 0;
        end
        else
        begin
                case ({push, pop})
//              2'b00 : begin  // this will never happen, really
//                              underrun <= #1 0;
//                              overrun  <= #1 0;
//                      end
                2'b10 : if (count==fifo_depth)  // overrun condition
                        begin
                                overrun   <= #1 1;
                                underrun  <= #1 0;
                        end
                        else
                        begin
                                top       <= #1 top_plus_1;
                                fifo[top_plus_1] <= #1 data_in;
                                underrun  <= #1 0;
                                overrun   <= #1 0;
                                count     <= #1 count + 1;
                        end
                2'b01 : if (~|count)
                        begin
                                underrun <= #1 1;  // underrun condition
                                overrun  <= #1 0;
                        end
                        else
                        begin
                                bottom   <= #1 bottom + 1;
                                underrun <= #1 0;
                                overrun  <= #1 0;
                                count    <= #1 count -1;
                        end
                2'b11 : begin
                                bottom   <= #1 bottom + 1;
                                top       <= #1 top_plus_1;
                                fifo[top_plus_1] <= #1 data_in;
                                underrun <= #1 0;
                                overrun  <= #1 0;
                        end
                endcase
        end
end   // always
 
always @(posedge clk)
begin
        if (overrun)
                overrun <= #1 0;
        if (underrun)
                underrun <= #1 0;
end
 
 
// please note though that data_out is only valid one clock after pop signal
assign data_out = fifo[bottom];

Line No.	Rev	Author	Line
1	2	gorban	`/// File: FIFO_inc.v`
2			`/// Author: Jacob Gorban, Flextronics Semiconductor`
3			`///`
4			`/// This file is FIFO logic. It should be included in your FIFO.`
5			`/// A module envelope should be created in the parent file.`
6			`/// The reason for creating this in a included module is being able to create custom FIFOs,`
7			`/// like modules with different ports or additional logic on the FIFO except the standard, easily`
8
9			`// FIFO parameters`
10			parameter fifo_width = `FIFO_WIDTH;
11			parameter fifo_depth = `FIFO_DEPTH;
12			parameter fifo_pointer_w = `FIFO_POINTER_W;
13			parameter fifo_counter_w = `FIFO_COUNTER_W;
14
15			`input clk;`
16			`input wb_rst_i;`
17			`input push;`
18			`input pop;`
19			`input [fifo_width-1:0] data_in;`
20			`output [fifo_width-1:0] data_out;`
21			`output overrun;`
22			`output underrun;`
23			`output [fifo_counter_w-1:0] count;`
24
25			`wire [fifo_width-1:0] data_out;`
26
27			`// FIFO itself`
28			`reg [fifo_width-1:0] fifo[fifo_depth-1:0];`
29
30			`// FIFO pointers`
31			`reg [fifo_pointer_w-1:0] top;`
32			`reg [fifo_pointer_w-1:0] bottom;`
33
34			`reg [fifo_counter_w-1:0] count;`
35			`reg overrun;`
36			`reg underrun;`
37
38			`wire [fifo_pointer_w-1:0] top_plus_1 = top + 1;`
39
40			`//always @(posedge clk or posedge wb_rst_i) // synchronous FIFO`
41			`always @(posedge push or posedge pop or posedge wb_rst_i) // asynchronous FIFO`
42			`begin`
43			`if (wb_rst_i==1)`
44			`begin`
45			`top <= #1 0;`
46			`bottom <= #1 0;`
47			`underrun <= #1 0;`
48			`overrun <= #1 0;`
49			`count <= #1 0;`
50			`end`
51			`else`
52			`begin`
53			`case ({push, pop})`
54			`// 2'b00 : begin // this will never happen, really`
55			`// underrun <= #1 0;`
56			`// overrun <= #1 0;`
57			`// end`
58			`2'b10 : if (count==fifo_depth) // overrun condition`
59			`begin`
60			`overrun <= #1 1;`
61			`underrun <= #1 0;`
62			`end`
63			`else`
64			`begin`
65			`top <= #1 top_plus_1;`
66			`fifo[top_plus_1] <= #1 data_in;`
67			`underrun <= #1 0;`
68			`overrun <= #1 0;`
69			`count <= #1 count + 1;`
70			`end`
71			`2'b01 : if (~\|count)`
72			`begin`
73			`underrun <= #1 1; // underrun condition`
74			`overrun <= #1 0;`
75			`end`
76			`else`
77			`begin`
78			`bottom <= #1 bottom + 1;`
79			`underrun <= #1 0;`
80			`overrun <= #1 0;`
81			`count <= #1 count -1;`
82			`end`
83			`2'b11 : begin`
84			`bottom <= #1 bottom + 1;`
85			`top <= #1 top_plus_1;`
86			`fifo[top_plus_1] <= #1 data_in;`
87			`underrun <= #1 0;`
88			`overrun <= #1 0;`
89			`end`
90			`endcase`
91			`end`
92			`end // always`
93
94			`always @(posedge clk)`
95			`begin`
96			`if (overrun)`
97			`overrun <= #1 0;`
98			`if (underrun)`
99			`underrun <= #1 0;`
100			`end`
101
102
103			`// please note though that data_out is only valid one clock after pop signal`
104			`assign data_out = fifo[bottom];`

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[/] [uart16550/] [tags/] [initial/] [verilog/] [FIFO_inc.v] - Blame information for rev 106