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[/] [uart16550/] [tags/] [initial/] [verilog/] [UART_FIFO.v] - Blame information for rev 106

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1 2 gorban
//  UART core transmitter FIFO
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//
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// Author: Jacob Gorban   (jacob.gorban@flextronicssemi.com)
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// Company: Flextronics Semiconductor
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//
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// Filename: UART_FIFO.v
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//
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// The actual FIFO logic is in the FIFO_inc.v file
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//
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// Releases:
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//              1.1     First release
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//
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`include "timescale.v"
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`include "UART_defines.v"
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module UART_TX_FIFO (clk,
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        wb_rst_i, data_in, data_out,
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// Control signals
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        push, // push strobe, active high
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        pop,   // pop strobe, active high
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// status signals
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        underrun,
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        overrun,
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        count
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        );
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`include "FIFO_inc.v"
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endmodule

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