URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

[/] [uart16550/] [tags/] [initial/] [verilog/] [UART_regs.v] - Blame information for rev 106

Details | Compare with Previous | View Log


//  UART core registers
//
// Includes transmission and reception tasks
//
// Author: Jacob Gorban   (jacob.gorban@flextronicssemi.com)
// Company: Flextronics Semiconductor
//
// Filename: UART_regs.v
//
// Releases:
//              1.1     First release
//
`include "timescale.v"
`include "UART_defines.v"
 
`define DL1 7:0
`define DL2 15:8
`define DL3 23:16
`define DL4 31:24
 
module UART_regs (clk,
        wb_rst_i, wb_addr_i, wb_dat_i, wb_dat_o, wb_we_i,
 
// registers
        ier, iir, fcr, mcr, lcr, lsr, msr, dl,
// additional signals
        modem_inputs,
        stx_o, srx_i,
        enable,
        rts_o, dtr_o
        );
 
input           clk;
input           wb_rst_i;
input   [`ADDR_WIDTH-1:0]        wb_addr_i;
input   [7:0]    wb_dat_i;
output  [7:0]    wb_dat_o;
input           wb_we_i;
 
output  [3:0]    ier;
output  [7:0]    iir;
output  [3:0]    fcr;  /// bits 7,6,2,1 of fcr. Other bits are ignored
output  [4:0]    mcr;
output  [7:0]    lcr;
output  [7:0]    lsr;
output  [7:0]    msr;
output  [31:0]   dl;  // 32-bit divisor latch
output          stx_o;
input           srx_i;
 
input   [3:0]    modem_inputs;
output          enable;
output          rts_o;
output          dtr_o;
 
wire    [3:0]    modem_inputs;
reg             enable;
reg             stx_o;
wire            srx_i;
 
reg     [7:0]    wb_dat_o;
 
wire    [`ADDR_WIDTH-1:0]        wb_addr_i;
wire    [7:0]    wb_dat_i;
 
 
reg     [3:0]    ier;
reg     [7:0]    iir;
reg     [3:0]    fcr;  /// bits 7,6,2,1 of fcr. Other bits are ignored
reg     [4:0]    mcr;
reg     [7:0]    lcr;
reg     [7:0]    lsr;
reg     [7:0]    msr;
reg     [31:0]   dl;  // 32-bit divisor latch
 
reg     [31:0]   dlc;  // 32-bit divisor latch counter
 
// Transmitter FIFO signals
wire    [`FIFO_WIDTH-1:0]        tf_data_in;
wire    [`FIFO_WIDTH-1:0]        tf_data_out;
reg                             tf_push;
reg                             tf_pop;
wire                            tf_underrun;
wire                            tf_overrun;
wire    [`FIFO_COUNTER_W-1:0]    tf_count;
 
// Receiver FIFO signals
reg     [`FIFO_REC_WIDTH-1:0]    rf_data_in;
wire    [`FIFO_REC_WIDTH-1:0]    rf_data_out;
reg                             rf_push;
reg                             rf_pop;
wire                            rf_underrun;
wire                            rf_overrun;
wire    [`FIFO_COUNTER_W-1:0]    rf_count;
wire                            rf_error_bit; // an error (parity or framing) is inside the fifo
 
reg     [3:0]                    trigger_level; // trigger level of the receiver FIFO
 
wire            dlab;                      // divisor latch access bit
wire            cts_i, dsr_i, ri_i, dcd_i; // modem status bits
wire            loopback;                  // loopback bit (MCR bit 4)
wire            cts, dsr, ri, dcd;         // effective signals (considering loopback)
wire            rts_o, dtr_o;              // modem control outputs
 
//
// ASSINGS
//
assign {cts_i, dsr_i, ri_i, dcd_i} = modem_inputs;
assign {cts, dsr, ri, dcd} = loopback ? {mcr[`MC_RTS],mcr[`MC_DTR],mcr[`MC_OUT1],mcr[`MC_OUT2]}
                 : ~{cts_i,dsr_i,ri_i,dcd_i};
 
assign dlab = lcr[`LC_DL];
assign tf_data_in = wb_dat_i;
assign loopback = mcr[4];
 
// assign modem outputs
assign  rts_o = mcr[`MC_RTS];
assign  dtr_o = mcr[`MC_DTR];
 
 
//
// FIFO INSTANCES
//
 
UART_TX_FIFO fifo_tx(clk, wb_rst_i, tf_data_in, tf_data_out,
        tf_push, tf_pop, tf_underrun, tf_overrun, tf_count);
 
UART_RX_FIFO fifo_rx(clk, wb_rst_i, rf_data_in, rf_data_out,
        rf_push, rf_pop, rf_underrun, rf_overrun, rf_count, rf_error_bit);
// Receiver FIFO parameters redefine
defparam fifo_rx.fifo_width = `FIFO_REC_WIDTH;
 
always @(posedge clk)   // synchrounous reading
//always @(wb_we_i or wb_addr_i or dlab or dl or rf_data_out or ier or iir or lcr or lsr or msr)
    if (~wb_we_i)   //if (we're not writing)
        case (wb_addr_i)
        `REG_RB : begin // Receiver FIFO or DL byte 1
                        rf_pop <= #1 1;
                        wb_dat_o <= #1 dlab ? dl[`DL1] : rf_data_out;
                  end
 
        `REG_IE : wb_dat_o <= #1 dlab ? dl[`DL2] : ier;
        `REG_II : wb_dat_o <= #1 iir;
        `REG_LC : wb_dat_o <= #1 lcr;
        `REG_LS : if (dlab)
                        wb_dat_o <= #1 dl[`DL4];
                  else
                  begin
                        wb_dat_o <= #1 lsr;
                        // clear read bits
                        lsr <= #1 lsr & 8'b00000001;
                  end
        `REG_MS : wb_dat_o <= #1 msr;
        `REG_DL3: wb_dat_o <= #1 dlab ? dl[`DL3] : 8'b0;
 
        default:  wb_dat_o <= #1 8'b0; // ??
        endcase
    else
        wb_dat_o <= #1 8'b0;
 
 
//
//   WRITES AND RESETS   //
//
// Line Control Register
always @(posedge clk)
        if (wb_rst_i)
                lcr <= #1 8'b00000011; // 8n1 setting
        else
        if (wb_we_i && wb_addr_i==`REG_LC)
                lcr <= #1 wb_dat_i;
 
// Interrupt Enable Register or DL2
always @(posedge clk or posedge wb_rst_i)
        if (wb_rst_i)
                ier <= #1 4'b0000; // no interrupts after reset
        else
        if (wb_we_i && wb_addr_i==`REG_IE)
                if (dlab)
                begin
                        dl[`DL2] <= #1 wb_dat_i;
                        dlc <= #1 dl;  // reset the counter to dl value
                end
                else
                        ier <= #1 wb_dat_i[3:0]; // ier uses only 4 lsb
 
 
// FIFO Control Register
always @(posedge clk or posedge wb_rst_i)
        if (wb_rst_i)
                fcr <= #1 4'b1100; // no interrupts after reset
        else
        if (wb_we_i && wb_addr_i==`REG_FC)
                fcr <= #1 {wb_dat_i[7:6],wb_dat_i[2:1]};
 
// Modem Control Register or DL3
always @(posedge clk or posedge wb_rst_i)
        if (wb_rst_i)
                mcr <= #1 5'b00000; // no interrupts after reset
        else
        if (wb_we_i && wb_addr_i==`REG_MC)
                if (dlab)
                begin
                        dl[`DL3] <= #1 wb_dat_i;
                        dlc <= #1 dl;
                end
                else
                        mcr <= #1 wb_dat_i[4:0];
 
// TX_FIFO or DL1
always @(posedge clk or posedge wb_rst_i)
        if (!wb_rst_i && wb_we_i && wb_addr_i==`REG_TR)
                if (dlab)
                begin
                        dl[`DL1] <= #1 wb_dat_i;
                        dlc <= #1 dl;
                end
                else
                        tf_push  <= #1 1;
 
// Receiver FIFO trigger level selection logic (asynchronous mux)
always @(fcr[`FC_TL])
        case (fcr[`FC_TL])
                2'b00 : trigger_level <= #1 1;
                2'b01 : trigger_level <= #1 4;
                2'b10 : trigger_level <= #1 8;
                2'b11 : trigger_level <= #1 14;
        endcase
 
// FIFO push and pop signals reset
always @(posedge clk or posedge wb_rst_i)
        if (wb_rst_i)
                tf_push <= #1 0;
        else
        if (tf_push == 1)
                tf_push <= #1 0;
 
always @(posedge clk or posedge wb_rst_i)
        if (wb_rst_i)
                tf_pop <= #1 0;
        else
        if (tf_pop == 1)
                tf_pop <= #1 0;
 
always @(posedge clk or posedge wb_rst_i)
        if (wb_rst_i)
                rf_push <= #1 0;
        else
        if (rf_push == 1)
                rf_push <= #1 0;
 
always @(posedge clk or posedge wb_rst_i)
        if (wb_rst_i)
                rf_pop <= #1 0;
        else
        if (rf_pop == 1)
                rf_pop <= #1 0;
 
 
// DL4 write
always @(posedge clk)
        if (!wb_rst_i && wb_we_i && wb_addr_i==`REG_DL4)
        begin
                dl[`DL4] <= #1 wb_dat_i;
                dlc <= #1 dl;
        end
 
//
//  STATUS REGISTERS  //
//
 
// Modem Status Register
always @(posedge clk)
begin
        msr[`MS_DDCD:`MS_DCTS] <= #1 {dcd, ri, dsr, cts} ^ msr[`MS_DDCD:`MS_DCTS];
        msr[`MS_CDCD:`MS_CCTS] <= #1 {dcd, ri, dsr, cts};
end
 
// Divisor Latches reset
always @(posedge wb_rst_i)
        dl <= #1 32'b0;
 
// Line Status Register is after the transmitter
 
// Enable signal generation logic
always @(posedge clk)
begin
        if (|dl) // if dl<>0
                if (enable)
                        dlc <= #1 dl;
                else
                        dlc <= #1 dlc - 1;  // decrease count
end
 
always @(dlc)
        if (~|dlc)  // dlc==0 ?
                enable = 1;
        else
                enable = 0;
 
//
//      INTERRUPT LOGIC
//
reg     rls_int;  // receiver line status interrupt
reg     rda_int;  // receiver data available interrupt
reg     ti_int;   // timeout indicator interrupt
reg     thre_int; // transmitter holding register empty interrupt
reg     ms_int;   // modem status interrupt
 
reg     [5:0]    counter_t;      // counts the timeout condition clocks
 
always @(posedge clk or posedge wb_rst_i)
begin
        if (wb_rst_i)
        begin
                rls_int  <= #1 0;
                rda_int  <= #1 0;
                ti_int   <= #1 0;
                thre_int <= #1 0;
                ms_int   <= #1 0;
        end
        else
        begin
                rls_int  <= #1 lsr[`LS_OE] | lsr[`LS_PE] | lsr['LS_FE] | lsr[`LS_BE];
                rda_int  <= #1 (rf_count >= trigger_level);
                thre_int <= #1 lsr[`LS_TFE];
                ms_int   <= #1 | msr[7:4]; // modem interrupt is pending when one of the modem inputs is asserted
                ti_int   <= #1 (counter_t == 0);
        end
end
 
always @(posedge clk or posedge wb_rst_i)
begin
        if (rls_int && ier[`IE_RLS])  // interrupt occured and is enabled  (not masked)
        begin
                iir[`II_II] <= #1 `II_RLS;      // set identification register to correct value
                iir                             // and set the IIR bit 0 (interrupt pending)
        end
end
 
 
 
//
// TRANSMITTER LOGIC
//
 
`define S_IDLE        0
`define S_SEND_START  1
`define S_SEND_BYTE   2
`define S_SEND_PARITY 3
`define S_SEND_STOP   4
`define S_POP_BYTE    5
 
reg     [2:0]    state;
reg     [3:0]    counter16;
reg     [2:0]    bit_counter;   // counts the bits to be sent
reg     [6:0]    shift_out;      // output shift register
reg             bit_out;
reg             parity_xor;  // parity of the word
 
always @(posedge clk or posedge wb_rst_i)
begin
  if (wb_rst_i)
  begin
        state     <= #1 `S_IDLE;
        stx_o     <= #1 0;
        counter16 <= #1 0;
  end
  else
  if (enable)
  begin
        case (state)
        `S_IDLE  :      if (~|tf_count) // if tf_count==0
                        begin
                                state <= #1 `S_IDLE;
                                stx_o <= #1 0;
                        end
                        else
                        begin
                                tf_pop <= #1 1;
                                stx_o  <= #1 0;
                                state  <= #1 `S_POP_BYTE;
                        end
        `S_POP_BYTE :   begin
                                tf_pop <= #1 0;
                                case (lcr[/*`LC_BITS*/1:0])  // number of bits in a word
                                2'b00 : begin
                                        bit_counter <= #1 3'b100;
                                        parity_xor  <= #1 ^tf_data_out[4:0];
                                     end
                                2'b01 : begin
                                        bit_counter <= #1 3'b101;
                                        parity_xor  <= #1 ^tf_data_out[5:0];
                                     end
                                2'b10 : begin
                                        bit_counter <= #1 3'b110;
                                        parity_xor  <= #1 ^tf_data_out[6:0];
                                     end
                                2'b11 : begin
                                        bit_counter <= #1 3'b111;
                                        parity_xor <= #1 ^tf_data_out[7:0];
                                     end
                                endcase
                                {shift_out[6:0], bit_out} <= #1 tf_data_out;
                                state <= #1 `S_SEND_START;
                        end
        `S_SEND_START : begin
                                if (~|counter16)
                                        counter16 <= #1 4'b1111;
                                else
                                if (counter16 == 1)
                                begin
                                        counter16 <= #1 0;
                                        state <= #1 `S_SEND_BYTE;
                                end
                                else
                                        counter16 <= #1 counter16 - 1;
                                stx_o <= #1 1;
                        end
        `S_SEND_BYTE :  begin
                                if (~|counter16)
                                        counter16 <= #1 4'b1111;
                                else
                                if (counter16 == 1)
                                begin
                                        if (|bit_counter) // if bit_counter>0
                                        begin
                                                bit_counter <= #1 bit_counter - 1;
                                                {shift_out[5:0],bit_out  } <= #1 {shift_out[6:1], shift_out[0]};
                                                state <= #1 `S_SEND_BYTE;
                                        end
                                        else   // end of byte
                                        if (~lcr[`LC_PE])
                                        begin
                                                state <= #1 `S_SEND_STOP;
                                        end
                                        else
                                        begin
                                                case ({lcr[`LC_EP],lcr[`LC_SP]})
                                                2'b00:  bit_out <= #1 ~parity_xor;
                                                2'b01:  bit_out <= #1 1;
                                                2'b10:  bit_out <= #1 parity_xor;
                                                2'b11:  bit_out <= #1 0;
                                                endcase
                                                state <= #1 `S_SEND_PARITY;
                                        end
                                        counter16 <= #1 0;
                                end
                                else
                                        counter16 <= #1 counter16 - 1;
                                stx_o <= #1 bit_out; // set output pin
                        end
        `S_SEND_PARITY :        begin
                                if (~|counter16)
                                        counter16 <= #1 4'b1111;
                                else
                                if (counter16 == 1)
                                begin
                                        counter16 <= #1 0;
                                        state <= #1 `S_SEND_STOP;
                                end
                                else
                                        counter16 <= #1 counter16 - 1;
                                stx_o <= #1 bit_out;
                        end
        `S_SEND_STOP :  begin
                                if (~|counter16)
                                        counter16 <= #1 4'b1111;
                                else
                                if (counter16 == 1)
                                begin
                                        counter16 <= #1 0;
                                        state <= #1 `S_IDLE;
                                end
                                else
                                        counter16 <= #1 counter16 - 1;
                                stx_o <= #1 0;
                        end
 
                default : // should never get here
                        state <= #1 `S_IDLE;
        endcase
  end // end if enable
end // transmitter logic
 
 
///
///  RECEIVER LOGIC
///
 
`define SR_IDLE         0
`define SR_REC_START    1
`define SR_REC_BIT      2
`define SR_REC_PARITY   3
`define SR_REC_STOP     4
`define SR_CHECK_PARITY 5
`define SR_REC_PREPARE  6
`define SR_END_BIT      7
`define SR_CALC_PARITY  8
`define SR_WAIT1        9
`define SR_PUSH         10
`define SR_LAST         11
 
reg     [3:0]    rstate;
reg     [3:0]    rcounter16;
reg     [2:0]    rbit_counter;
reg     [7:0]    rshift;                 // receiver shift register
reg             rparity;                // received parity
reg             rparity_error;
reg             rframing_error;         // framing error flag
reg             rbit_in;
reg             rparity_xor;
 
wire            rcounter16_eq_7 = (rcounter16 == 7);
wire            rcounter16_eq_0 = (rcounter16 == 0);
wire    [3:0]    rcounter16_minus_1 = rcounter16 - 1;
 
always @(posedge clk or posedge wb_rst_i)
begin
  if (wb_rst_i)
  begin
        rstate          <= #1 `SR_IDLE;
        rbit_in         <= #1 0;
        rcounter16      <= #1 0;
        rbit_counter    <= #1 0;
        rparity_xor     <= #1 0;
        rframing_error  <= #1 0;
        rparity_error   <= #1 0;
        rshift          <= #1 0;
  end
  else
  if (enable)
  begin
        case (rstate)
        `SR_IDLE :      if (srx_i==1)   // detected a pulse (start bit?)
                        begin
                                rstate <= #1 `SR_REC_START;
                                rcounter16 <= #1 4'b1110;
                        end
                        else
                                rstate <= #1 `SR_IDLE;
        `SR_REC_START : begin
                                if (rcounter16_eq_7)    // check the pulse
                                        if (srx_i==0)   // no start bit
                                                rstate <= #1 `SR_IDLE;
                                        else            // start bit detected
                                                rstate <= #1 `SR_REC_PREPARE;
                                rcounter16 <= #1 rcounter16_minus_1;
                        end
        `SR_REC_PREPARE:begin
                                case (lcr[/*`LC_BITS*/1:0])  // number of bits in a word
                                2'b00 : rbit_counter <= #1 3'b100;
                                2'b01 : rbit_counter <= #1 3'b101;
                                2'b10 : rbit_counter <= #1 3'b110;
                                2'b11 : rbit_counter <= #1 3'b111;
                                endcase
                                if (rcounter16_eq_0)
                                begin
                                        rstate          <= #1 `SR_REC_BIT;
                                        rcounter16      <= #1 4'b1110;
                                        rshift          <= #1 0;
                                end
                                else
                                        rstate <= #1 `SR_REC_PREPARE;
                                rcounter16 <= #1 rcounter16_minus_1;
                        end
        `SR_REC_BIT :   begin
                                if (rcounter16_eq_0)
                                        rstate <= #1 `SR_END_BIT;
                                if (rcounter16_eq_7) // read the bit
                                        case (lcr[/*`LC_BITS*/1:0])  // number of bits in a word
                                        2'b00 : rshift[4:0]  <= #1 {srx_i, rshift[4:1]};
                                        2'b01 : rshift[5:0]  <= #1 {srx_i, rshift[5:1]};
                                        2'b10 : rshift[6:0]  <= #1 {srx_i, rshift[6:1]};
                                        2'b11 : rshift[7:0]  <= #1 {srx_i, rshift[7:1]};
                                        endcase
                                rcounter16 <= #1 rcounter16_minus_1;
                        end
        `SR_END_BIT :   begin
                                if (rbit_counter==0) // no more bits in word
                                        if (lcr[`LC_PE]) // choose state based on parity
                                                rstate <= #1 `SR_REC_PARITY;
                                        else
                                        begin
                                                rstate <= #1 `SR_REC_STOP;
                                                rparity_error <= #1 0;  // no parity - no error :)
                                        end
                                else            // else we have more bits to read
                                begin
                                        rstate <= #1 `SR_REC_BIT;
                                        rbit_counter <= #1 rbit_counter - 1;
                                end
                                rcounter16 <= #1 4'b1110;
                        end
        `SR_REC_PARITY: begin
                                if (rcounter16_eq_7)    // read the parity
                                begin
                                        rparity <= #1 srx_i;
                                        rstate <= #1 `SR_CALC_PARITY;
                                end
                                rcounter16 <= #1 rcounter16_minus_1;
                        end
        `SR_CALC_PARITY : begin    // rcounter equals 6
                                rcounter16  <= #1 rcounter16_minus_1;
                                rparity_xor <= #1 ^{rshift,rparity}; // calculate parity on all incoming data
                                rstate      <= #1 `SR_CHECK_PARITY;
                          end
        `SR_CHECK_PARITY: begin   // rcounter equals 5
                                case ({lcr[`LC_EP],lcr[`LC_SP]})
                                2'b00: rparity_error <= #1 ~rparity_xor;  // no error if parity 1
                                2'b01: rparity_error <= #1 ~rparity;      // parity should sticked to 1
                                2'b10: rparity_error <= #1 rparity_xor;   // error if parity is odd
                                2'b11: rparity_error <= #1 rparity;       // parity should be sticked to 0
                                endcase
                                rcounter16 <= #1 rcounter16_minus_1;
                                rstate <= #1 `SR_WAIT1;
                          end
        `SR_WAIT1 :     if (rcounter16_eq_0)
                        begin
                                rstate <= #1 `SR_REC_STOP;
                                rcounter16 <= #1 4'b1110;
                        end
                        else
                        begin
                                rcounter16 <= #1 rcounter16_minus_1;
//                              rstate <= #1 `SR_WAIT1;
                        end
        `SR_REC_STOP :  begin
                                if (rcounter16_eq_7)    // read the parity
                                begin
                                        rframing_error <= #1 srx_i; // no framing error if input is 0 (stop bit)
                                        rf_data_in <= #1 {rshift, rparity_error, rframing_error};
                                        rstate <= #1 `SR_PUSH;
                                end
                                rcounter16 <= #1 rcounter16_minus_1;
                        end
        `SR_PUSH :      begin
///////////////////////////////////////
                                $display($time, ": received: %b", rf_data_in);
                                rf_push    <= #1 1;
                                rstate     <= #1 `SR_LAST;
                        end
        `SR_LAST :      begin
                                if (rcounter16_eq_0)
                                        rstate <= #1 `SR_IDLE;
                                rcounter16 <= #1 rcounter16_minus_1;
                                rf_push <= #1 0;
                        end
        default : rstate <= #1 `SR_IDLE;
        endcase
  end  // if (enable)
end // always of receiver
 
//
// Break condition detection.
// Works in conjuction with the receiver state machine
reg     [3:0]    counter_b;      // counts the 0 signals
 
always @(posedge clk or posedge wb_rst_i)
begin
        if (wb_rst_i)
                counter_b <= #1 4'd11;
        else
        if (enable)  // only work on enable times
                if (srx_i)
                begin
                        counter_b <= #1 4'd11; // maximum character time length - 1
                        lsr[`LS_BI] <= #1 0;   // break off
                end
                else
                if (counter_b == 0)            // break reached
                        lsr[`LS_BI] <= #1 1;   // break detected flag set
                else
                        counter_b <= #1 counter_b - 1;  // decrement break counter
end // always of break condition detection
 
///
/// Timeout condition detection
 
always @(posedge clk or posedge wb_rst_i)
begin
        if (wb_rst_i)
                counter_t <= #1 6'd44;
        else
        if (enable)
                if(rf_push | rf_pop | rda_int) // counter is reset when RX FIFO is accessed or above trigger level
                        counter_t <= #1 6'd44;
                else
                if (counter_t != 0)  // we don't want to underflow
                        counter_t <= #1 counter_t - 1;
end
 
// Line Status Register
always @(posedge clk or wb_rst_i)
begin
        if (wb_rst_i)
                lsr <= #1 8'b01100000;
        else
        begin
                lsr[0] <= #1 (rf_count!=0);  // data in receiver fifo available
                lsr[1] <= #1 rf_overrun;     // Receiver overrun error
                lsr[2] <= #1 rf_data_out[1]; // parity error bit
                //lsr[4] (break interrupt is done in break detection, after the receiver FSM)
                lsr[3] <= #1 rf_data_out[0]; // framing error bit
                lsr[5] <= #1 (tf_count==0);  // transmitter fifo is empty
                lsr[6] <= #1 (tf_count==0 && state == `S_IDLE); // transmitter empty
                lsr[7] <= #1 rf_error_bit;
        end
end
 
endmodule

Browse

Tools

Subversion Repositories uart16550

[/] [uart16550/] [tags/] [initial/] [verilog/] [UART_regs.v] - Blame information for rev 106

Line No.	Rev	Author	Line
1	2	gorban	`// UART core registers`
2			`//`
3			`// Includes transmission and reception tasks`
4			`//`
5			`// Author: Jacob Gorban (jacob.gorban@flextronicssemi.com)`
6			`// Company: Flextronics Semiconductor`
7			`//`
8			`// Filename: UART_regs.v`
9			`//`
10			`// Releases:`
11			`// 1.1 First release`
12			`//`
13			`include "timescale.v"
14			`include "UART_defines.v"
15
16			`define DL1 7:0
17			`define DL2 15:8
18			`define DL3 23:16
19			`define DL4 31:24
20
21			`module UART_regs (clk,`
22			`wb_rst_i, wb_addr_i, wb_dat_i, wb_dat_o, wb_we_i,`
23
24			`// registers`
25			`ier, iir, fcr, mcr, lcr, lsr, msr, dl,`
26			`// additional signals`
27			`modem_inputs,`
28			`stx_o, srx_i,`
29			`enable,`
30			`rts_o, dtr_o`
31			`);`
32
33			`input clk;`
34			`input wb_rst_i;`
35			input [`ADDR_WIDTH-1:0] wb_addr_i;
36			`input [7:0] wb_dat_i;`
37			`output [7:0] wb_dat_o;`
38			`input wb_we_i;`
39
40			`output [3:0] ier;`
41			`output [7:0] iir;`
42			`output [3:0] fcr; /// bits 7,6,2,1 of fcr. Other bits are ignored`
43			`output [4:0] mcr;`
44			`output [7:0] lcr;`
45			`output [7:0] lsr;`
46			`output [7:0] msr;`
47			`output [31:0] dl; // 32-bit divisor latch`
48			`output stx_o;`
49			`input srx_i;`
50
51			`input [3:0] modem_inputs;`
52			`output enable;`
53			`output rts_o;`
54			`output dtr_o;`
55
56			`wire [3:0] modem_inputs;`
57			`reg enable;`
58			`reg stx_o;`
59			`wire srx_i;`
60
61			`reg [7:0] wb_dat_o;`
62
63			wire [`ADDR_WIDTH-1:0] wb_addr_i;
64			`wire [7:0] wb_dat_i;`
65
66
67			`reg [3:0] ier;`
68			`reg [7:0] iir;`
69			`reg [3:0] fcr; /// bits 7,6,2,1 of fcr. Other bits are ignored`
70			`reg [4:0] mcr;`
71			`reg [7:0] lcr;`
72			`reg [7:0] lsr;`
73			`reg [7:0] msr;`
74			`reg [31:0] dl; // 32-bit divisor latch`
75
76			`reg [31:0] dlc; // 32-bit divisor latch counter`
77
78			`// Transmitter FIFO signals`
79			wire [`FIFO_WIDTH-1:0] tf_data_in;
80			wire [`FIFO_WIDTH-1:0] tf_data_out;
81			`reg tf_push;`
82			`reg tf_pop;`
83			`wire tf_underrun;`
84			`wire tf_overrun;`
85			wire [`FIFO_COUNTER_W-1:0] tf_count;
86
87			`// Receiver FIFO signals`
88			reg [`FIFO_REC_WIDTH-1:0] rf_data_in;
89			wire [`FIFO_REC_WIDTH-1:0] rf_data_out;
90			`reg rf_push;`
91			`reg rf_pop;`
92			`wire rf_underrun;`
93			`wire rf_overrun;`
94			wire [`FIFO_COUNTER_W-1:0] rf_count;
95			`wire rf_error_bit; // an error (parity or framing) is inside the fifo`
96
97			`reg [3:0] trigger_level; // trigger level of the receiver FIFO`
98
99			`wire dlab; // divisor latch access bit`
100			`wire cts_i, dsr_i, ri_i, dcd_i; // modem status bits`
101			`wire loopback; // loopback bit (MCR bit 4)`
102			`wire cts, dsr, ri, dcd; // effective signals (considering loopback)`
103			`wire rts_o, dtr_o; // modem control outputs`
104
105			`//`
106			`// ASSINGS`
107			`//`
108			`assign {cts_i, dsr_i, ri_i, dcd_i} = modem_inputs;`
109			assign {cts, dsr, ri, dcd} = loopback ? {mcr[`MC_RTS],mcr[`MC_DTR],mcr[`MC_OUT1],mcr[`MC_OUT2]}
110			`: ~{cts_i,dsr_i,ri_i,dcd_i};`
111
112			assign dlab = lcr[`LC_DL];
113			`assign tf_data_in = wb_dat_i;`
114			`assign loopback = mcr[4];`
115
116			`// assign modem outputs`
117			assign rts_o = mcr[`MC_RTS];
118			assign dtr_o = mcr[`MC_DTR];
119
120
121			`//`
122			`// FIFO INSTANCES`
123			`//`
124
125			`UART_TX_FIFO fifo_tx(clk, wb_rst_i, tf_data_in, tf_data_out,`
126			`tf_push, tf_pop, tf_underrun, tf_overrun, tf_count);`
127
128			`UART_RX_FIFO fifo_rx(clk, wb_rst_i, rf_data_in, rf_data_out,`
129			`rf_push, rf_pop, rf_underrun, rf_overrun, rf_count, rf_error_bit);`
130			`// Receiver FIFO parameters redefine`
131			defparam fifo_rx.fifo_width = `FIFO_REC_WIDTH;
132
133			`always @(posedge clk) // synchrounous reading`
134			`//always @(wb_we_i or wb_addr_i or dlab or dl or rf_data_out or ier or iir or lcr or lsr or msr)`
135			`if (~wb_we_i) //if (we're not writing)`
136			`case (wb_addr_i)`
137			`REG_RB : begin // Receiver FIFO or DL byte 1
138			`rf_pop <= #1 1;`
139			wb_dat_o <= #1 dlab ? dl[`DL1] : rf_data_out;
140			`end`
141
142			`REG_IE : wb_dat_o <= #1 dlab ? dl[`DL2] : ier;
143			`REG_II : wb_dat_o <= #1 iir;
144			`REG_LC : wb_dat_o <= #1 lcr;
145			`REG_LS : if (dlab)
146			wb_dat_o <= #1 dl[`DL4];
147			`else`
148			`begin`
149			`wb_dat_o <= #1 lsr;`
150			`// clear read bits`
151			`lsr <= #1 lsr & 8'b00000001;`
152			`end`
153			`REG_MS : wb_dat_o <= #1 msr;
154			`REG_DL3: wb_dat_o <= #1 dlab ? dl[`DL3] : 8'b0;
155
156			`default: wb_dat_o <= #1 8'b0; // ??`
157			`endcase`
158			`else`
159			`wb_dat_o <= #1 8'b0;`
160
161
162			`//`
163			`// WRITES AND RESETS //`
164			`//`
165			`// Line Control Register`
166			`always @(posedge clk)`
167			`if (wb_rst_i)`
168			`lcr <= #1 8'b00000011; // 8n1 setting`
169			`else`
170			if (wb_we_i && wb_addr_i==`REG_LC)
171			`lcr <= #1 wb_dat_i;`
172
173			`// Interrupt Enable Register or DL2`
174			`always @(posedge clk or posedge wb_rst_i)`
175			`if (wb_rst_i)`
176			`ier <= #1 4'b0000; // no interrupts after reset`
177			`else`
178			if (wb_we_i && wb_addr_i==`REG_IE)
179			`if (dlab)`
180			`begin`
181			dl[`DL2] <= #1 wb_dat_i;
182			`dlc <= #1 dl; // reset the counter to dl value`
183			`end`
184			`else`
185			`ier <= #1 wb_dat_i[3:0]; // ier uses only 4 lsb`
186
187
188			`// FIFO Control Register`
189			`always @(posedge clk or posedge wb_rst_i)`
190			`if (wb_rst_i)`
191			`fcr <= #1 4'b1100; // no interrupts after reset`
192			`else`
193			if (wb_we_i && wb_addr_i==`REG_FC)
194			`fcr <= #1 {wb_dat_i[7:6],wb_dat_i[2:1]};`
195
196			`// Modem Control Register or DL3`
197			`always @(posedge clk or posedge wb_rst_i)`
198			`if (wb_rst_i)`
199			`mcr <= #1 5'b00000; // no interrupts after reset`
200			`else`
201			if (wb_we_i && wb_addr_i==`REG_MC)
202			`if (dlab)`
203			`begin`
204			dl[`DL3] <= #1 wb_dat_i;
205			`dlc <= #1 dl;`
206			`end`
207			`else`
208			`mcr <= #1 wb_dat_i[4:0];`
209
210			`// TX_FIFO or DL1`
211			`always @(posedge clk or posedge wb_rst_i)`
212			if (!wb_rst_i && wb_we_i && wb_addr_i==`REG_TR)
213			`if (dlab)`
214			`begin`
215			dl[`DL1] <= #1 wb_dat_i;
216			`dlc <= #1 dl;`
217			`end`
218			`else`
219			`tf_push <= #1 1;`
220
221			`// Receiver FIFO trigger level selection logic (asynchronous mux)`
222			always @(fcr[`FC_TL])
223			case (fcr[`FC_TL])
224			`2'b00 : trigger_level <= #1 1;`
225			`2'b01 : trigger_level <= #1 4;`
226			`2'b10 : trigger_level <= #1 8;`
227			`2'b11 : trigger_level <= #1 14;`
228			`endcase`
229
230			`// FIFO push and pop signals reset`
231			`always @(posedge clk or posedge wb_rst_i)`
232			`if (wb_rst_i)`
233			`tf_push <= #1 0;`
234			`else`
235			`if (tf_push == 1)`
236			`tf_push <= #1 0;`
237
238			`always @(posedge clk or posedge wb_rst_i)`
239			`if (wb_rst_i)`
240			`tf_pop <= #1 0;`
241			`else`
242			`if (tf_pop == 1)`
243			`tf_pop <= #1 0;`
244
245			`always @(posedge clk or posedge wb_rst_i)`
246			`if (wb_rst_i)`
247			`rf_push <= #1 0;`
248			`else`
249			`if (rf_push == 1)`
250			`rf_push <= #1 0;`
251
252			`always @(posedge clk or posedge wb_rst_i)`
253			`if (wb_rst_i)`
254			`rf_pop <= #1 0;`
255			`else`
256			`if (rf_pop == 1)`
257			`rf_pop <= #1 0;`
258
259
260			`// DL4 write`
261			`always @(posedge clk)`
262			if (!wb_rst_i && wb_we_i && wb_addr_i==`REG_DL4)
263			`begin`
264			dl[`DL4] <= #1 wb_dat_i;
265			`dlc <= #1 dl;`
266			`end`
267
268			`//`
269			`// STATUS REGISTERS //`
270			`//`
271
272			`// Modem Status Register`
273			`always @(posedge clk)`
274			`begin`
275			msr[`MS_DDCD:`MS_DCTS] <= #1 {dcd, ri, dsr, cts} ^ msr[`MS_DDCD:`MS_DCTS];
276			msr[`MS_CDCD:`MS_CCTS] <= #1 {dcd, ri, dsr, cts};
277			`end`
278
279			`// Divisor Latches reset`
280			`always @(posedge wb_rst_i)`
281			`dl <= #1 32'b0;`
282
283			`// Line Status Register is after the transmitter`
284
285			`// Enable signal generation logic`
286			`always @(posedge clk)`
287			`begin`
288			`if (\|dl) // if dl<>0`
289			`if (enable)`
290			`dlc <= #1 dl;`
291			`else`
292			`dlc <= #1 dlc - 1; // decrease count`
293			`end`
294
295			`always @(dlc)`
296			`if (~\|dlc) // dlc==0 ?`
297			`enable = 1;`
298			`else`
299			`enable = 0;`
300
301			`//`
302			`// INTERRUPT LOGIC`
303			`//`
304			`reg rls_int; // receiver line status interrupt`
305			`reg rda_int; // receiver data available interrupt`
306			`reg ti_int; // timeout indicator interrupt`
307			`reg thre_int; // transmitter holding register empty interrupt`
308			`reg ms_int; // modem status interrupt`
309
310			`reg [5:0] counter_t; // counts the timeout condition clocks`
311
312			`always @(posedge clk or posedge wb_rst_i)`
313			`begin`
314			`if (wb_rst_i)`
315			`begin`
316			`rls_int <= #1 0;`
317			`rda_int <= #1 0;`
318			`ti_int <= #1 0;`
319			`thre_int <= #1 0;`
320			`ms_int <= #1 0;`
321			`end`
322			`else`
323			`begin`
324			rls_int <= #1 lsr[`LS_OE] \| lsr[`LS_PE] \| lsr['LS_FE] \| lsr[`LS_BE];
325			`rda_int <= #1 (rf_count >= trigger_level);`
326			thre_int <= #1 lsr[`LS_TFE];
327			`ms_int <= #1 \| msr[7:4]; // modem interrupt is pending when one of the modem inputs is asserted`
328			`ti_int <= #1 (counter_t == 0);`
329			`end`
330			`end`
331
332			`always @(posedge clk or posedge wb_rst_i)`
333			`begin`
334			if (rls_int && ier[`IE_RLS]) // interrupt occured and is enabled (not masked)
335			`begin`
336			iir[`II_II] <= #1 `II_RLS; // set identification register to correct value
337			`iir // and set the IIR bit 0 (interrupt pending)`
338			`end`
339			`end`
340
341
342
343			`//`
344			`// TRANSMITTER LOGIC`
345			`//`
346
347			`define S_IDLE 0
348			`define S_SEND_START 1
349			`define S_SEND_BYTE 2
350			`define S_SEND_PARITY 3
351			`define S_SEND_STOP 4
352			`define S_POP_BYTE 5
353
354			`reg [2:0] state;`
355			`reg [3:0] counter16;`
356			`reg [2:0] bit_counter; // counts the bits to be sent`
357			`reg [6:0] shift_out; // output shift register`
358			`reg bit_out;`
359			`reg parity_xor; // parity of the word`
360
361			`always @(posedge clk or posedge wb_rst_i)`
362			`begin`
363			`if (wb_rst_i)`
364			`begin`
365			state <= #1 `S_IDLE;
366			`stx_o <= #1 0;`
367			`counter16 <= #1 0;`
368			`end`
369			`else`
370			`if (enable)`
371			`begin`
372			`case (state)`
373			`S_IDLE : if (~\|tf_count) // if tf_count==0
374			`begin`
375			state <= #1 `S_IDLE;
376			`stx_o <= #1 0;`
377			`end`
378			`else`
379			`begin`
380			`tf_pop <= #1 1;`
381			`stx_o <= #1 0;`
382			state <= #1 `S_POP_BYTE;
383			`end`
384			`S_POP_BYTE : begin
385			`tf_pop <= #1 0;`
386			case (lcr[/`LC_BITS/1:0]) // number of bits in a word
387			`2'b00 : begin`
388			`bit_counter <= #1 3'b100;`
389			`parity_xor <= #1 ^tf_data_out[4:0];`
390			`end`
391			`2'b01 : begin`
392			`bit_counter <= #1 3'b101;`
393			`parity_xor <= #1 ^tf_data_out[5:0];`
394			`end`
395			`2'b10 : begin`
396			`bit_counter <= #1 3'b110;`
397			`parity_xor <= #1 ^tf_data_out[6:0];`
398			`end`
399			`2'b11 : begin`
400			`bit_counter <= #1 3'b111;`
401			`parity_xor <= #1 ^tf_data_out[7:0];`
402			`end`
403			`endcase`
404			`{shift_out[6:0], bit_out} <= #1 tf_data_out;`
405			state <= #1 `S_SEND_START;
406			`end`
407			`S_SEND_START : begin
408			`if (~\|counter16)`
409			`counter16 <= #1 4'b1111;`
410			`else`
411			`if (counter16 == 1)`
412			`begin`
413			`counter16 <= #1 0;`
414			state <= #1 `S_SEND_BYTE;
415			`end`
416			`else`
417			`counter16 <= #1 counter16 - 1;`
418			`stx_o <= #1 1;`
419			`end`
420			`S_SEND_BYTE : begin
421			`if (~\|counter16)`
422			`counter16 <= #1 4'b1111;`
423			`else`
424			`if (counter16 == 1)`
425			`begin`
426			`if (\|bit_counter) // if bit_counter>0`
427			`begin`
428			`bit_counter <= #1 bit_counter - 1;`
429			`{shift_out[5:0],bit_out } <= #1 {shift_out[6:1], shift_out[0]};`
430			state <= #1 `S_SEND_BYTE;
431			`end`
432			`else // end of byte`
433			if (~lcr[`LC_PE])
434			`begin`
435			state <= #1 `S_SEND_STOP;
436			`end`
437			`else`
438			`begin`
439			case ({lcr[`LC_EP],lcr[`LC_SP]})
440			`2'b00: bit_out <= #1 ~parity_xor;`
441			`2'b01: bit_out <= #1 1;`
442			`2'b10: bit_out <= #1 parity_xor;`
443			`2'b11: bit_out <= #1 0;`
444			`endcase`
445			state <= #1 `S_SEND_PARITY;
446			`end`
447			`counter16 <= #1 0;`
448			`end`
449			`else`
450			`counter16 <= #1 counter16 - 1;`
451			`stx_o <= #1 bit_out; // set output pin`
452			`end`
453			`S_SEND_PARITY : begin
454			`if (~\|counter16)`
455			`counter16 <= #1 4'b1111;`
456			`else`
457			`if (counter16 == 1)`
458			`begin`
459			`counter16 <= #1 0;`
460			state <= #1 `S_SEND_STOP;
461			`end`
462			`else`
463			`counter16 <= #1 counter16 - 1;`
464			`stx_o <= #1 bit_out;`
465			`end`
466			`S_SEND_STOP : begin
467			`if (~\|counter16)`
468			`counter16 <= #1 4'b1111;`
469			`else`
470			`if (counter16 == 1)`
471			`begin`
472			`counter16 <= #1 0;`
473			state <= #1 `S_IDLE;
474			`end`
475			`else`
476			`counter16 <= #1 counter16 - 1;`
477			`stx_o <= #1 0;`
478			`end`
479
480			`default : // should never get here`
481			state <= #1 `S_IDLE;
482			`endcase`
483			`end // end if enable`
484			`end // transmitter logic`
485
486
487			`///`
488			`/// RECEIVER LOGIC`
489			`///`
490
491			`define SR_IDLE 0
492			`define SR_REC_START 1
493			`define SR_REC_BIT 2
494			`define SR_REC_PARITY 3
495			`define SR_REC_STOP 4
496			`define SR_CHECK_PARITY 5
497			`define SR_REC_PREPARE 6
498			`define SR_END_BIT 7
499			`define SR_CALC_PARITY 8
500			`define SR_WAIT1 9
501			`define SR_PUSH 10
502			`define SR_LAST 11
503
504			`reg [3:0] rstate;`
505			`reg [3:0] rcounter16;`
506			`reg [2:0] rbit_counter;`
507			`reg [7:0] rshift; // receiver shift register`
508			`reg rparity; // received parity`
509			`reg rparity_error;`
510			`reg rframing_error; // framing error flag`
511			`reg rbit_in;`
512			`reg rparity_xor;`
513
514			`wire rcounter16_eq_7 = (rcounter16 == 7);`
515			`wire rcounter16_eq_0 = (rcounter16 == 0);`
516			`wire [3:0] rcounter16_minus_1 = rcounter16 - 1;`
517
518			`always @(posedge clk or posedge wb_rst_i)`
519			`begin`
520			`if (wb_rst_i)`
521			`begin`
522			rstate <= #1 `SR_IDLE;
523			`rbit_in <= #1 0;`
524			`rcounter16 <= #1 0;`
525			`rbit_counter <= #1 0;`
526			`rparity_xor <= #1 0;`
527			`rframing_error <= #1 0;`
528			`rparity_error <= #1 0;`
529			`rshift <= #1 0;`
530			`end`
531			`else`
532			`if (enable)`
533			`begin`
534			`case (rstate)`
535			`SR_IDLE : if (srx_i==1) // detected a pulse (start bit?)
536			`begin`
537			rstate <= #1 `SR_REC_START;
538			`rcounter16 <= #1 4'b1110;`
539			`end`
540			`else`
541			rstate <= #1 `SR_IDLE;
542			`SR_REC_START : begin
543			`if (rcounter16_eq_7) // check the pulse`
544			`if (srx_i==0) // no start bit`
545			rstate <= #1 `SR_IDLE;
546			`else // start bit detected`
547			rstate <= #1 `SR_REC_PREPARE;
548			`rcounter16 <= #1 rcounter16_minus_1;`
549			`end`
550			`SR_REC_PREPARE:begin
551			case (lcr[/`LC_BITS/1:0]) // number of bits in a word
552			`2'b00 : rbit_counter <= #1 3'b100;`
553			`2'b01 : rbit_counter <= #1 3'b101;`
554			`2'b10 : rbit_counter <= #1 3'b110;`
555			`2'b11 : rbit_counter <= #1 3'b111;`
556			`endcase`
557			`if (rcounter16_eq_0)`
558			`begin`
559			rstate <= #1 `SR_REC_BIT;
560			`rcounter16 <= #1 4'b1110;`
561			`rshift <= #1 0;`
562			`end`
563			`else`
564			rstate <= #1 `SR_REC_PREPARE;
565			`rcounter16 <= #1 rcounter16_minus_1;`
566			`end`
567			`SR_REC_BIT : begin
568			`if (rcounter16_eq_0)`
569			rstate <= #1 `SR_END_BIT;
570			`if (rcounter16_eq_7) // read the bit`
571			case (lcr[/`LC_BITS/1:0]) // number of bits in a word
572			`2'b00 : rshift[4:0] <= #1 {srx_i, rshift[4:1]};`
573			`2'b01 : rshift[5:0] <= #1 {srx_i, rshift[5:1]};`
574			`2'b10 : rshift[6:0] <= #1 {srx_i, rshift[6:1]};`
575			`2'b11 : rshift[7:0] <= #1 {srx_i, rshift[7:1]};`
576			`endcase`
577			`rcounter16 <= #1 rcounter16_minus_1;`
578			`end`
579			`SR_END_BIT : begin
580			`if (rbit_counter==0) // no more bits in word`
581			if (lcr[`LC_PE]) // choose state based on parity
582			rstate <= #1 `SR_REC_PARITY;
583			`else`
584			`begin`
585			rstate <= #1 `SR_REC_STOP;
586			`rparity_error <= #1 0; // no parity - no error :)`
587			`end`
588			`else // else we have more bits to read`
589			`begin`
590			rstate <= #1 `SR_REC_BIT;
591			`rbit_counter <= #1 rbit_counter - 1;`
592			`end`
593			`rcounter16 <= #1 4'b1110;`
594			`end`
595			`SR_REC_PARITY: begin
596			`if (rcounter16_eq_7) // read the parity`
597			`begin`
598			`rparity <= #1 srx_i;`
599			rstate <= #1 `SR_CALC_PARITY;
600			`end`
601			`rcounter16 <= #1 rcounter16_minus_1;`
602			`end`
603			`SR_CALC_PARITY : begin // rcounter equals 6
604			`rcounter16 <= #1 rcounter16_minus_1;`
605			`rparity_xor <= #1 ^{rshift,rparity}; // calculate parity on all incoming data`
606			rstate <= #1 `SR_CHECK_PARITY;
607			`end`
608			`SR_CHECK_PARITY: begin // rcounter equals 5
609			case ({lcr[`LC_EP],lcr[`LC_SP]})
610			`2'b00: rparity_error <= #1 ~rparity_xor; // no error if parity 1`
611			`2'b01: rparity_error <= #1 ~rparity; // parity should sticked to 1`
612			`2'b10: rparity_error <= #1 rparity_xor; // error if parity is odd`
613			`2'b11: rparity_error <= #1 rparity; // parity should be sticked to 0`
614			`endcase`
615			`rcounter16 <= #1 rcounter16_minus_1;`
616			rstate <= #1 `SR_WAIT1;
617			`end`
618			`SR_WAIT1 : if (rcounter16_eq_0)
619			`begin`
620			rstate <= #1 `SR_REC_STOP;
621			`rcounter16 <= #1 4'b1110;`
622			`end`
623			`else`
624			`begin`
625			`rcounter16 <= #1 rcounter16_minus_1;`
626			// rstate <= #1 `SR_WAIT1;
627			`end`
628			`SR_REC_STOP : begin
629			`if (rcounter16_eq_7) // read the parity`
630			`begin`
631			`rframing_error <= #1 srx_i; // no framing error if input is 0 (stop bit)`
632			`rf_data_in <= #1 {rshift, rparity_error, rframing_error};`
633			rstate <= #1 `SR_PUSH;
634			`end`
635			`rcounter16 <= #1 rcounter16_minus_1;`
636			`end`
637			`SR_PUSH : begin
638			`///////////////////////////////////////`
639			`$display($time, ": received: %b", rf_data_in);`
640			`rf_push <= #1 1;`
641			rstate <= #1 `SR_LAST;
642			`end`
643			`SR_LAST : begin
644			`if (rcounter16_eq_0)`
645			rstate <= #1 `SR_IDLE;
646			`rcounter16 <= #1 rcounter16_minus_1;`
647			`rf_push <= #1 0;`
648			`end`
649			default : rstate <= #1 `SR_IDLE;
650			`endcase`
651			`end // if (enable)`
652			`end // always of receiver`
653
654			`//`
655			`// Break condition detection.`
656			`// Works in conjuction with the receiver state machine`
657			`reg [3:0] counter_b; // counts the 0 signals`
658
659			`always @(posedge clk or posedge wb_rst_i)`
660			`begin`
661			`if (wb_rst_i)`
662			`counter_b <= #1 4'd11;`
663			`else`
664			`if (enable) // only work on enable times`
665			`if (srx_i)`
666			`begin`
667			`counter_b <= #1 4'd11; // maximum character time length - 1`
668			lsr[`LS_BI] <= #1 0; // break off
669			`end`
670			`else`
671			`if (counter_b == 0) // break reached`
672			lsr[`LS_BI] <= #1 1; // break detected flag set
673			`else`
674			`counter_b <= #1 counter_b - 1; // decrement break counter`
675			`end // always of break condition detection`
676
677			`///`
678			`/// Timeout condition detection`
679
680			`always @(posedge clk or posedge wb_rst_i)`
681			`begin`
682			`if (wb_rst_i)`
683			`counter_t <= #1 6'd44;`
684			`else`
685			`if (enable)`
686			`if(rf_push \| rf_pop \| rda_int) // counter is reset when RX FIFO is accessed or above trigger level`
687			`counter_t <= #1 6'd44;`
688			`else`
689			`if (counter_t != 0) // we don't want to underflow`
690			`counter_t <= #1 counter_t - 1;`
691			`end`
692
693			`// Line Status Register`
694			`always @(posedge clk or wb_rst_i)`
695			`begin`
696			`if (wb_rst_i)`
697			`lsr <= #1 8'b01100000;`
698			`else`
699			`begin`
700			`lsr[0] <= #1 (rf_count!=0); // data in receiver fifo available`
701			`lsr[1] <= #1 rf_overrun; // Receiver overrun error`
702			`lsr[2] <= #1 rf_data_out[1]; // parity error bit`
703			`//lsr[4] (break interrupt is done in break detection, after the receiver FSM)`
704			`lsr[3] <= #1 rf_data_out[0]; // framing error bit`
705			`lsr[5] <= #1 (tf_count==0); // transmitter fifo is empty`
706			lsr[6] <= #1 (tf_count==0 && state == `S_IDLE); // transmitter empty
707			`lsr[7] <= #1 rf_error_bit;`
708			`end`
709			`end`
710
711			`endmodule`