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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  uart_regs.v                                                 ////
////                                                              ////
////                                                              ////
////  This file is part of the "UART 16550 compatible" project    ////
////  http://www.opencores.org/cores/uart16550/                   ////
////                                                              ////
////  Documentation related to this project:                      ////
////  - http://www.opencores.org/cores/uart16550/                 ////
////                                                              ////
////  Projects compatibility:                                     ////
////  - WISHBONE                                                  ////
////  RS232 Protocol                                              ////
////  16550D uart (mostly supported)                              ////
////                                                              ////
////  Overview (main Features):                                   ////
////  Registers of the uart 16550 core                            ////
////                                                              ////
////  Known problems (limits):                                    ////
////  Inserts 1 wait state in all WISHBONE transfers              ////
////                                                              ////
////  To Do:                                                      ////
////  Nothing or verification.                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - gorban@opencores.org                                  ////
////      - Jacob Gorban                                          ////
////      - Igor Mohor (igorm@opencores.org)                      ////
////                                                              ////
////  Created:        2001/05/12                                  ////
////  Last Updated:   (See log for the revision history           ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000, 2001 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.29  2001/12/12 09:05:46  mohor
// LSR status bit 0 was not cleared correctly in case of reseting the FCR (rx fifo).
//
// Revision 1.28  2001/12/10 19:52:41  gorban
// Scratch register added
//
// Revision 1.27  2001/12/06 14:51:04  gorban
// Bug in LSR[0] is fixed.
// All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.
//
// Revision 1.26  2001/12/03 21:44:29  gorban
// Updated specification documentation.
// Added full 32-bit data bus interface, now as default.
// Address is 5-bit wide in 32-bit data bus mode.
// Added wb_sel_i input to the core. It's used in the 32-bit mode.
// Added debug interface with two 32-bit read-only registers in 32-bit mode.
// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
// My small test bench is modified to work with 32-bit mode.
//
// Revision 1.25  2001/11/28 19:36:39  gorban
// Fixed: timeout and break didn't pay attention to current data format when counting time
//
// Revision 1.24  2001/11/26 21:38:54  gorban
// Lots of fixes:
// Break condition wasn't handled correctly at all.
// LSR bits could lose their values.
// LSR value after reset was wrong.
// Timing of THRE interrupt signal corrected.
// LSR bit 0 timing corrected.
//
// Revision 1.23  2001/11/12 21:57:29  gorban
// fixed more typo bugs
//
// Revision 1.22  2001/11/12 15:02:28  mohor
// lsr1r error fixed.
//
// Revision 1.21  2001/11/12 14:57:27  mohor
// ti_int_pnd error fixed.
//
// Revision 1.20  2001/11/12 14:50:27  mohor
// ti_int_d error fixed.
//
// Revision 1.19  2001/11/10 12:43:21  gorban
// Synthesis bugs fixed. Some other minor changes
//
// Revision 1.18  2001/11/08 14:54:23  mohor
// Comments in Slovene language deleted, few small fixes for better work of
// old tools. IRQs need to be fix.
//
// Revision 1.17  2001/11/07 17:51:52  gorban
// Heavily rewritten interrupt and LSR subsystems.
// Many bugs hopefully squashed.
//
// Revision 1.16  2001/11/02 09:55:16  mohor
// no message
//
// Revision 1.15  2001/10/31 15:19:22  gorban
// Fixes to break and timeout conditions
//
// Revision 1.14  2001/10/29 17:00:46  gorban
// fixed parity sending and tx_fifo resets over- and underrun
//
// Revision 1.13  2001/10/20 09:58:40  gorban
// Small synopsis fixes
//
// Revision 1.12  2001/10/19 16:21:40  gorban
// Changes data_out to be synchronous again as it should have been.
//
// Revision 1.11  2001/10/18 20:35:45  gorban
// small fix
//
// Revision 1.10  2001/08/24 21:01:12  mohor
// Things connected to parity changed.
// Clock devider changed.
//
// Revision 1.9  2001/08/23 16:05:05  mohor
// Stop bit bug fixed.
// Parity bug fixed.
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
//
// Revision 1.10  2001/06/23 11:21:48  gorban
// DL made 16-bit long. Fixed transmission/reception bugs.
//
// Revision 1.9  2001/05/31 20:08:01  gorban
// FIFO changes and other corrections.
//
// Revision 1.8  2001/05/29 20:05:04  gorban
// Fixed some bugs and synthesis problems.
//
// Revision 1.7  2001/05/27 17:37:49  gorban
// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
//
// Revision 1.6  2001/05/21 19:12:02  gorban
// Corrected some Linter messages.
//
// Revision 1.5  2001/05/17 18:34:18  gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0  2001-05-17 21:27:11+02  jacob
// Initial revision
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
`include "uart_defines.v"
 
`define UART_DL1 7:0
`define UART_DL2 15:8
 
module uart_regs (clk,
        wb_rst_i, wb_addr_i, wb_dat_i, wb_dat_o, wb_we_i, wb_re_i,
 
// additional signals
        modem_inputs,
        stx_pad_o, srx_pad_i,
 
`ifdef DATA_BUS_WIDTH_8
`else
// debug interface signals      enabled
ier, iir, fcr, mcr, lcr, msr, lsr, rf_count, tf_count, tstate, rstate,
`endif
        rts_pad_o, dtr_pad_o, int_o
        );
 
input                                                                   clk;
input                                                                   wb_rst_i;
input [`UART_ADDR_WIDTH-1:0]             wb_addr_i;
input [7:0]                                                      wb_dat_i;
output [7:0]                                                     wb_dat_o;
input                                                                   wb_we_i;
input                                                                   wb_re_i;
 
output                                                                  stx_pad_o;
input                                                                   srx_pad_i;
 
input [3:0]                                                      modem_inputs;
output                                                                  rts_pad_o;
output                                                                  dtr_pad_o;
output                                                                  int_o;
 
`ifdef DATA_BUS_WIDTH_8
`else
// if 32-bit databus and debug interface are enabled
output [3:0]                                                     ier;
output [3:0]                                                     iir;
output [1:0]                                                     fcr;  /// bits 7 and 6 of fcr. Other bits are ignored
output [4:0]                                                     mcr;
output [7:0]                                                     lcr;
output [7:0]                                                     msr;
output [7:0]                                                     lsr;
output [`UART_FIFO_COUNTER_W-1:0]        rf_count;
output [`UART_FIFO_COUNTER_W-1:0]        tf_count;
output [2:0]                                                     tstate;
output [3:0]                                                     rstate;
 
`endif
 
wire [3:0]                                                               modem_inputs;
reg                                                                             enable;
wire                                                                            stx_pad_o;              // received from transmitter module
wire                                                                            srx_pad_i;
 
reg [7:0]                                                                wb_dat_o;
 
wire [`UART_ADDR_WIDTH-1:0]              wb_addr_i;
wire [7:0]                                                               wb_dat_i;
 
 
reg [3:0]                                                                ier;
reg [3:0]                                                                iir;
reg [1:0]                                                                fcr;  /// bits 7 and 6 of fcr. Other bits are ignored
reg [4:0]                                                                mcr;
reg [7:0]                                                                lcr;
reg [7:0]                                                                msr;
reg [15:0]                                                               dl;  // 32-bit divisor latch
reg [7:0]                                                                scratch; // UART scratch register
reg                                                                             start_dlc; // activate dlc on writing to UART_DL1
reg                                                                             lsr_mask_d; // delay for lsr_mask condition
reg                                                                             msi_reset; // reset MSR 4 lower bits indicator
//reg                                                                           threi_clear; // THRE interrupt clear flag
reg [15:0]                                                               dlc;  // 32-bit divisor latch counter
reg                                                                             int_o;
 
reg [3:0]                                                                trigger_level; // trigger level of the receiver FIFO
reg                                                                             rx_reset;
reg                                                                             tx_reset;
 
wire                                                                            dlab;                      // divisor latch access bit
wire                                                                            cts_pad_i, dsr_pad_i, ri_pad_i, dcd_pad_i; // modem status bits
wire                                                                            loopback;                  // loopback bit (MCR bit 4)
wire                                                                            cts, dsr, ri, dcd;         // effective signals (considering loopback)
wire                                                                            rts_pad_o, dtr_pad_o;              // modem control outputs
 
// LSR bits wires and regs
wire [7:0]                                                               lsr;
wire                                                                            lsr0, lsr1, lsr2, lsr3, lsr4, lsr5, lsr6, lsr7;
reg                                                                             lsr0r, lsr1r, lsr2r, lsr3r, lsr4r, lsr5r, lsr6r, lsr7r;
wire                                                                            lsr_mask; // lsr_mask
 
//
// ASSINGS
//
 
assign                                                                  lsr[7:0] = { lsr7r, lsr6r, lsr5r, lsr4r, lsr3r, lsr2r, lsr1r, lsr0r };
 
assign                                                                  {cts_pad_i, dsr_pad_i, ri_pad_i, dcd_pad_i} = modem_inputs;
assign                                                                  {cts, dsr, ri, dcd} = loopback ? {mcr[`UART_MC_RTS],mcr[`UART_MC_DTR],mcr[`UART_MC_OUT1],mcr[`UART_MC_OUT2]}
                                                                                        : ~{cts_pad_i,dsr_pad_i,ri_pad_i,dcd_pad_i};
 
assign                                                                  dlab = lcr[`UART_LC_DL];
assign                                                                  loopback = mcr[4];
 
// assign modem outputs
assign                                                                  rts_pad_o = mcr[`UART_MC_RTS];
assign                                                                  dtr_pad_o = mcr[`UART_MC_DTR];
 
// Interrupt signals
wire                                                                            rls_int;  // receiver line status interrupt
wire                                                                            rda_int;  // receiver data available interrupt
wire                                                                            ti_int;   // timeout indicator interrupt
wire                                                                            thre_int; // transmitter holding register empty interrupt
wire                                                                            ms_int;   // modem status interrupt
 
// FIFO signals
reg                                                                             tf_push;
reg                                                                             rf_pop;
wire [`UART_FIFO_REC_WIDTH-1:0]  rf_data_out;
wire                                                                            rf_error_bit; // an error (parity or framing) is inside the fifo
wire [`UART_FIFO_COUNTER_W-1:0]  rf_count;
wire [`UART_FIFO_COUNTER_W-1:0]  tf_count;
wire [2:0]                                                               tstate;
wire [3:0]                                                               rstate;
wire [9:0]                                                               counter_t;
 
 
// Transmitter Instance
uart_transmitter transmitter(clk, wb_rst_i, lcr, tf_push, wb_dat_i, enable, stx_pad_o, tstate, tf_count, tx_reset, lsr_mask);
 
// Receiver Instance
uart_receiver receiver(clk, wb_rst_i, lcr, rf_pop, srx_pad_i, enable, rda_int,
        counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate, rf_push);
 
 
// Asynchronous reading here because the outputs are sampled in uart_wb.v file 
always @(dl or dlab or ier or iir or scratch
                        or lcr or lsr or msr or rf_data_out or wb_addr_i or wb_re_i)   // asynchrounous reading
begin
        case (wb_addr_i)
                `UART_REG_RB   : wb_dat_o = dlab ? dl[`UART_DL1] : rf_data_out[10:3];
                `UART_REG_IE    : wb_dat_o = dlab ? dl[`UART_DL2] : ier;
                `UART_REG_II    : wb_dat_o = {4'b1100,iir};
                `UART_REG_LC    : wb_dat_o = lcr;
                `UART_REG_LS    : wb_dat_o = lsr;
                `UART_REG_MS    : wb_dat_o = msr;
                `UART_REG_SR    : wb_dat_o = scratch;
                default:  wb_dat_o = 8'b0; // ??
        endcase // case(wb_addr_i)
end // always @ (dl or dlab or ier or iir or scratch...
 
 
// rf_pop signal handling
always @(posedge clk or posedge wb_rst_i)
begin
        if (wb_rst_i)
                rf_pop <= #1 0;
        else
        if (rf_pop)     // restore the signal to 0 after one clock cycle
                rf_pop <= #1 0;
        else
        if (wb_re_i && wb_addr_i == `UART_REG_RB && !dlab)
                rf_pop <= #1 1; // advance read pointer
end
 
wire    lsr_mask_condition;
wire    iir_read;
wire  msr_read;
wire    fifo_read;
wire    fifo_write;
 
assign lsr_mask_condition = (wb_re_i && wb_addr_i == `UART_REG_LS && !dlab);
assign iir_read = (wb_re_i && wb_addr_i == `UART_REG_II && !dlab);
assign msr_read = (wb_re_i && wb_addr_i == `UART_REG_MS && !dlab);
assign fifo_read = (wb_re_i && wb_addr_i == `UART_REG_RB && !dlab);
assign fifo_write = (wb_we_i && wb_addr_i == `UART_REG_TR && !dlab);
 
// lsr_mask_d delayed signal handling
always @(posedge clk or posedge wb_rst_i)
begin
        if (wb_rst_i)
                lsr_mask_d <= #1 0;
        else // reset bits in the Line Status Register
                lsr_mask_d <= #1 lsr_mask_condition;
end
 
// lsr_mask is rise detected
assign lsr_mask = lsr_mask_condition && ~lsr_mask_d;
 
// msi_reset signal handling
always @(posedge clk or posedge wb_rst_i)
begin
        if (wb_rst_i)
                msi_reset <= #1 0;
        else
        if (msi_reset)
                msi_reset <= #1 0;
        else
        if (msr_read)
                msi_reset <= #1 1; // reset bits in Modem Status Register
end
 
 
//
//   WRITES AND RESETS   //
//
// Line Control Register
always @(posedge clk or posedge wb_rst_i)
        if (wb_rst_i)
                lcr <= #1 8'b00000011; // 8n1 setting
        else
        if (wb_we_i && wb_addr_i==`UART_REG_LC)
                lcr <= #1 wb_dat_i;
 
// Interrupt Enable Register or UART_DL2
always @(posedge clk or posedge wb_rst_i)
        if (wb_rst_i)
        begin
                ier <= #1 4'b0000; // no interrupts after reset
                dl[`UART_DL2] <= #1 8'b0;
        end
        else
        if (wb_we_i && wb_addr_i==`UART_REG_IE)
                if (dlab)
                begin
                        dl[`UART_DL2] <= #1 wb_dat_i;
                end
                else
                        ier <= #1 wb_dat_i[3:0]; // ier uses only 4 lsb
 
 
// FIFO Control Register and rx_reset, tx_reset signals
always @(posedge clk or posedge wb_rst_i)
        if (wb_rst_i) begin
                fcr <= #1 2'b11;
                rx_reset <= #1 0;
                tx_reset <= #1 0;
        end else
        if (wb_we_i && wb_addr_i==`UART_REG_FC) begin
                fcr <= #1 wb_dat_i[7:6];
                rx_reset <= #1 wb_dat_i[1];
                tx_reset <= #1 wb_dat_i[2];
        end else begin
                rx_reset <= #1 0;
                tx_reset <= #1 0;
        end
 
// Modem Control Register
always @(posedge clk or posedge wb_rst_i)
        if (wb_rst_i)
                mcr <= #1 5'b0;
        else
        if (wb_we_i && wb_addr_i==`UART_REG_MC)
                        mcr <= #1 wb_dat_i[4:0];
 
// Scratch register
// Line Control Register
always @(posedge clk or posedge wb_rst_i)
        if (wb_rst_i)
                scratch <= #1 0; // 8n1 setting
        else
        if (wb_we_i && wb_addr_i==`UART_REG_SR)
                scratch <= #1 wb_dat_i;
 
// TX_FIFO or UART_DL1
always @(posedge clk or posedge wb_rst_i)
        if (wb_rst_i)
        begin
                dl[`UART_DL1]  <= #1 8'b0;
                tf_push   <= #1 1'b0;
                start_dlc <= #1 1'b0;
        end
        else
        if (wb_we_i && wb_addr_i==`UART_REG_TR)
                if (dlab)
                begin
                        dl[`UART_DL1] <= #1 wb_dat_i;
                        start_dlc <= #1 1'b1; // enable DL counter
                        tf_push <= #1 1'b0;
                end
                else
                begin
                        tf_push   <= #1 1'b1;
                        start_dlc <= #1 1'b0;
                end // else: !if(dlab)
        else
        begin
                start_dlc <= #1 1'b0;
                tf_push   <= #1 1'b0;
        end // else: !if(dlab)
 
// Receiver FIFO trigger level selection logic (asynchronous mux)
always @(fcr)
        case (fcr[`UART_FC_TL])
                2'b00 : trigger_level = 1;
                2'b01 : trigger_level = 4;
                2'b10 : trigger_level = 8;
                2'b11 : trigger_level = 14;
        endcase // case(fcr[`UART_FC_TL])
 
//
//  STATUS REGISTERS  //
//
 
// Modem Status Register
always @(posedge clk or posedge wb_rst_i)
begin
        if (wb_rst_i)
                msr <= #1 0;
        else begin
                msr[`UART_MS_DDCD:`UART_MS_DCTS] <= #1 msi_reset ? 4'b0 :
                        msr[`UART_MS_DDCD:`UART_MS_DCTS] | ({dcd, ri, dsr, cts} ^ msr[`UART_MS_CDCD:`UART_MS_CCTS]);
                msr[`UART_MS_CDCD:`UART_MS_CCTS] <= #1 {dcd, ri, dsr, cts};
        end
end
 
// Line Status Register
 
// activation conditions
assign lsr0 = (rf_count==0 && rf_push);  // data in receiver fifo available set condition
assign lsr1 = rf_overrun;     // Receiver overrun error
assign lsr2 = rf_data_out[1]; // parity error bit
assign lsr3 = rf_data_out[0]; // framing error bit
assign lsr4 = rf_data_out[2]; // break error in the character
assign lsr5 = (tf_count==5'b0);  // transmitter fifo is empty
assign lsr6 = (tf_count==5'b0 && (tstate == /*`S_IDLE */ 0)); // transmitter empty
assign lsr7 = rf_error_bit;
 
// lsr bit0 (receiver data available)
reg      lsr0_d;
 
always @(posedge clk or posedge wb_rst_i)
        if (wb_rst_i) lsr0_d <= #1 0;
        else lsr0_d <= #1 lsr0;
 
always @(posedge clk or posedge wb_rst_i)
        if (wb_rst_i) lsr0r <= #1 0;
        else lsr0r <= #1 (rf_count==1 && fifo_read || rx_reset) ? 0 : // deassert condition
                                          lsr0r || (lsr0 && ~lsr0_d); // set on rise of lsr0 and keep asserted until deasserted 
 
// lsr bit 1 (receiver overrun)
reg lsr1_d; // delayed
 
always @(posedge clk or posedge wb_rst_i)
        if (wb_rst_i) lsr1_d <= #1 0;
        else lsr1_d <= #1 lsr1;
 
always @(posedge clk or posedge wb_rst_i)
        if (wb_rst_i) lsr1r <= #1 0;
        else    lsr1r <= #1     lsr_mask ? 0 : lsr1r || (lsr1 && ~lsr1_d); // set on rise
 
// lsr bit 2 (parity error)
reg lsr2_d; // delayed
 
always @(posedge clk or posedge wb_rst_i)
        if (wb_rst_i) lsr2_d <= #1 0;
        else lsr2_d <= #1 lsr2;
 
always @(posedge clk or posedge wb_rst_i)
        if (wb_rst_i) lsr2r <= #1 0;
        else lsr2r <= #1 lsr_mask ? 0 : lsr2r || (lsr2 && ~lsr2_d); // set on rise
 
// lsr bit 3 (framing error)
reg lsr3_d; // delayed
 
always @(posedge clk or posedge wb_rst_i)
        if (wb_rst_i) lsr3_d <= #1 0;
        else lsr3_d <= #1 lsr3;
 
always @(posedge clk or posedge wb_rst_i)
        if (wb_rst_i) lsr3r <= #1 0;
        else lsr3r <= #1 lsr_mask ? 0 : lsr3r || (lsr3 && ~lsr3_d); // set on rise
 
// lsr bit 4 (break indicator)
reg lsr4_d; // delayed
 
always @(posedge clk or posedge wb_rst_i)
        if (wb_rst_i) lsr4_d <= #1 0;
        else lsr4_d <= #1 lsr4;
 
always @(posedge clk or posedge wb_rst_i)
        if (wb_rst_i) lsr4r <= #1 0;
        else lsr4r <= #1 lsr_mask ? 0 : lsr4r || (lsr4 && ~lsr4_d);
 
// lsr bit 5 (transmitter fifo is empty)
reg lsr5_d;
 
always @(posedge clk or posedge wb_rst_i)
        if (wb_rst_i) lsr5_d <= #1 1;
        else lsr5_d <= #1 lsr5;
 
always @(posedge clk or posedge wb_rst_i)
        if (wb_rst_i) lsr5r <= #1 1;
        else lsr5r <= #1 (fifo_write) ? 0 :  lsr5r || (lsr5 && ~lsr5_d);
 
// lsr bit 6 (transmitter empty indicator)
reg lsr6_d;
 
always @(posedge clk or posedge wb_rst_i)
        if (wb_rst_i) lsr6_d <= #1 1;
        else lsr6_d <= #1 lsr6;
 
always @(posedge clk or posedge wb_rst_i)
        if (wb_rst_i) lsr6r <= #1 1;
        else lsr6r <= #1 (fifo_write) ? 0 : lsr6r || (lsr6 && ~lsr6_d);
 
// lsr bit 7 (error in fifo)
reg lsr7_d;
 
always @(posedge clk or posedge wb_rst_i)
        if (wb_rst_i) lsr7_d <= #1 0;
        else lsr7_d <= #1 lsr7;
 
always @(posedge clk or posedge wb_rst_i)
        if (wb_rst_i) lsr7r <= #1 0;
        else lsr7r <= #1 lsr_mask ? 0 : lsr7r || (lsr7 && ~lsr7_d);
 
// Frequency divider
always @(posedge clk or posedge wb_rst_i)
begin
        if (wb_rst_i)
                dlc <= #1 0;
        else
                if (start_dlc | ~ (|dlc))
                        dlc <= #1 dl - 1;               // preset counter
                else
                        dlc <= #1 dlc - 1;              // decrement counter
end
 
// Enable signal generation logic
always @(posedge clk or posedge wb_rst_i)
begin
        if (wb_rst_i)
                enable <= #1 1'b0;
        else
                if (|dl & ~(|dlc))     // dl>0 & dlc==0
                        enable <= #1 1'b1;
                else
                        enable <= #1 1'b0;
end
 
//
//      INTERRUPT LOGIC
//
 
assign rls_int  = ier[`UART_IE_RLS] && (lsr[`UART_LS_OE] || lsr[`UART_LS_PE] || lsr[`UART_LS_FE] || lsr[`UART_LS_BI]);
assign rda_int  = ier[`UART_IE_RDA] && (rf_count >= {1'b0,trigger_level});
assign thre_int = ier[`UART_IE_THRE] && lsr[`UART_LS_TFE];
assign ms_int   = ier[`UART_IE_MS] && (| msr[3:0]);
assign ti_int   = ier[`UART_IE_RDA] && (counter_t == 10'b0);
 
reg      rls_int_d;
reg      thre_int_d;
reg      ms_int_d;
reg      ti_int_d;
reg      rda_int_d;
 
// delay lines
always  @(posedge clk or posedge wb_rst_i)
        if (wb_rst_i) rls_int_d <= #1 0;
        else rls_int_d <= #1 rls_int;
 
always  @(posedge clk or posedge wb_rst_i)
        if (wb_rst_i) rda_int_d <= #1 0;
        else rda_int_d <= #1 rda_int;
 
always  @(posedge clk or posedge wb_rst_i)
        if (wb_rst_i) thre_int_d <= #1 0;
        else thre_int_d <= #1 thre_int;
 
always  @(posedge clk or posedge wb_rst_i)
        if (wb_rst_i) ms_int_d <= #1 0;
        else ms_int_d <= #1 ms_int;
 
always  @(posedge clk or posedge wb_rst_i)
        if (wb_rst_i) ti_int_d <= #1 0;
        else ti_int_d <= #1 ti_int;
 
// rise detection signals
 
wire     rls_int_rise;
wire     thre_int_rise;
wire     ms_int_rise;
wire     ti_int_rise;
wire     rda_int_rise;
 
assign rda_int_rise    = rda_int & ~rda_int_d;
assign rls_int_rise       = rls_int & ~rls_int_d;
assign thre_int_rise   = thre_int & ~thre_int_d;
assign ms_int_rise        = ms_int & ~ms_int_d;
assign ti_int_rise        = ti_int & ~ti_int_d;
 
// interrupt pending flags
reg     rls_int_pnd;
reg     rda_int_pnd;
reg     thre_int_pnd;
reg     ms_int_pnd;
reg     ti_int_pnd;
 
// interrupt pending flags assignments
always  @(posedge clk or posedge wb_rst_i)
        if (wb_rst_i) rls_int_pnd <= #1 0;
        else
                rls_int_pnd <= #1 lsr_mask ? 0 :                                                 // reset condition
                                                        rls_int_rise ? 1 :                                              // latch condition
                                                        rls_int_pnd && ier[`UART_IE_RLS];       // default operation: remove if masked
 
always  @(posedge clk or posedge wb_rst_i)
        if (wb_rst_i) rda_int_pnd <= #1 0;
        else
                rda_int_pnd <= #1 ((rf_count == {1'b0,trigger_level}) && fifo_read) ? 0 :        // reset condition
                                                        rda_int_rise ? 1 :                                              // latch condition
                                                        rda_int_pnd && ier[`UART_IE_RDA];       // default operation: remove if masked
 
always  @(posedge clk or posedge wb_rst_i)
        if (wb_rst_i) thre_int_pnd <= #1 0;
        else
                thre_int_pnd <= #1 fifo_write || (iir_read & ~iir[`UART_II_IP] & iir[`UART_II_II] == `UART_II_THRE)? 0 :
                                                        thre_int_rise ? 1 :
                                                        thre_int_pnd && ier[`UART_IE_THRE];
 
always  @(posedge clk or posedge wb_rst_i)
        if (wb_rst_i) ms_int_pnd <= #1 0;
        else
                ms_int_pnd <= #1 msr_read ? 0 :
                                                        ms_int_rise ? 1 :
                                                        ms_int_pnd && ier[`UART_IE_MS];
 
always  @(posedge clk or posedge wb_rst_i)
        if (wb_rst_i) ti_int_pnd <= #1 0;
        else
                ti_int_pnd <= #1 fifo_read ? 0 :
                                                        ti_int_rise ? 1 :
                                                        ti_int_pnd && ier[`UART_IE_RDA];
// end of pending flags
 
// INT_O logic
always @(posedge clk or posedge wb_rst_i)
begin
        if (wb_rst_i)
                int_o <= #1 1'b0;
        else
                int_o <= #1
                                        rls_int_pnd             ?       ~lsr_mask                                       :
                                        rda_int_pnd             ? 1                                                             :
                                        ti_int_pnd              ? ~fifo_read                                    :
                                        thre_int_pnd    ? !(fifo_write & iir_read) :
                                        ms_int_pnd              ? ~msr_read                                             :
                                        0;       // if no interrupt are pending
end
 
 
// Interrupt Identification register
always @(posedge clk or posedge wb_rst_i)
begin
        if (wb_rst_i)
                iir <= #1 1;
        else
        if (rls_int_pnd)  // interrupt is pending
        begin
                iir[`UART_II_II] <= #1 `UART_II_RLS;    // set identification register to correct value
                iir[`UART_II_IP] <= #1 1'b0;            // and clear the IIR bit 0 (interrupt pending)
        end else // the sequence of conditions determines priority of interrupt identification
        if (rda_int)
        begin
                iir[`UART_II_II] <= #1 `UART_II_RDA;
                iir[`UART_II_IP] <= #1 1'b0;
        end
        else if (ti_int_pnd)
        begin
                iir[`UART_II_II] <= #1 `UART_II_TI;
                iir[`UART_II_IP] <= #1 1'b0;
        end
        else if (thre_int_pnd)
        begin
                iir[`UART_II_II] <= #1 `UART_II_THRE;
                iir[`UART_II_IP] <= #1 1'b0;
        end
        else if (ms_int_pnd)
        begin
                iir[`UART_II_II] <= #1 `UART_II_MS;
                iir[`UART_II_IP] <= #1 1'b0;
        end else        // no interrupt is pending
        begin
                iir[`UART_II_II] <= #1 0;
                iir[`UART_II_IP] <= #1 1'b1;
        end
end
 
endmodule

Line No.	Rev	Author	Line
1	27	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// uart_regs.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the "UART 16550 compatible" project ////`
7			`//// http://www.opencores.org/cores/uart16550/ ////`
8			`//// ////`
9			`//// Documentation related to this project: ////`
10			`//// - http://www.opencores.org/cores/uart16550/ ////`
11			`//// ////`
12			`//// Projects compatibility: ////`
13			`//// - WISHBONE ////`
14			`//// RS232 Protocol ////`
15			`//// 16550D uart (mostly supported) ////`
16			`//// ////`
17			`//// Overview (main Features): ////`
18			`//// Registers of the uart 16550 core ////`
19			`//// ////`
20			`//// Known problems (limits): ////`
21			`//// Inserts 1 wait state in all WISHBONE transfers ////`
22			`//// ////`
23			`//// To Do: ////`
24			`//// Nothing or verification. ////`
25			`//// ////`
26			`//// Author(s): ////`
27			`//// - gorban@opencores.org ////`
28			`//// - Jacob Gorban ////`
29	29	mohor	`//// - Igor Mohor (igorm@opencores.org) ////`
30	27	mohor	`//// ////`
31			`//// Created: 2001/05/12 ////`
32			`//// Last Updated: (See log for the revision history ////`
33			`//// ////`
34			`//// ////`
35			`//////////////////////////////////////////////////////////////////////`
36			`//// ////`
37	29	mohor	`//// Copyright (C) 2000, 2001 Authors ////`
38	27	mohor	`//// ////`
39			`//// This source file may be used and distributed without ////`
40			`//// restriction provided that this copyright statement is not ////`
41			`//// removed from the file and that any derivative work contains ////`
42			`//// the original copyright notice and the associated disclaimer. ////`
43			`//// ////`
44			`//// This source file is free software; you can redistribute it ////`
45			`//// and/or modify it under the terms of the GNU Lesser General ////`
46			`//// Public License as published by the Free Software Foundation; ////`
47			`//// either version 2.1 of the License, or (at your option) any ////`
48			`//// later version. ////`
49			`//// ////`
50			`//// This source is distributed in the hope that it will be ////`
51			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
52			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
53			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
54			`//// details. ////`
55			`//// ////`
56			`//// You should have received a copy of the GNU Lesser General ////`
57			`//// Public License along with this source; if not, download it ////`
58			`//// from http://www.opencores.org/lgpl.shtml ////`
59			`//// ////`
60			`//////////////////////////////////////////////////////////////////////`
61			`//`
62			`// CVS Revision History`
63			`//`
64			`// $Log: not supported by cvs2svn $`
65	56	mohor	`// Revision 1.29 2001/12/12 09:05:46 mohor`
66			`// LSR status bit 0 was not cleared correctly in case of reseting the FCR (rx fifo).`
67			`//`
68	54	mohor	`// Revision 1.28 2001/12/10 19:52:41 gorban`
69			`// Scratch register added`
70			`//`
71	52	gorban	`// Revision 1.27 2001/12/06 14:51:04 gorban`
72			`// Bug in LSR[0] is fixed.`
73			`// All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.`
74			`//`
75	50	gorban	`// Revision 1.26 2001/12/03 21:44:29 gorban`
76			`// Updated specification documentation.`
77			`// Added full 32-bit data bus interface, now as default.`
78			`// Address is 5-bit wide in 32-bit data bus mode.`
79			`// Added wb_sel_i input to the core. It's used in the 32-bit mode.`
80			`// Added debug interface with two 32-bit read-only registers in 32-bit mode.`
81			`// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.`
82			`// My small test bench is modified to work with 32-bit mode.`
83			`//`
84	48	gorban	`// Revision 1.25 2001/11/28 19:36:39 gorban`
85			`// Fixed: timeout and break didn't pay attention to current data format when counting time`
86			`//`
87	47	gorban	`// Revision 1.24 2001/11/26 21:38:54 gorban`
88			`// Lots of fixes:`
89			`// Break condition wasn't handled correctly at all.`
90			`// LSR bits could lose their values.`
91			`// LSR value after reset was wrong.`
92			`// Timing of THRE interrupt signal corrected.`
93			`// LSR bit 0 timing corrected.`
94			`//`
95	45	gorban	`// Revision 1.23 2001/11/12 21:57:29 gorban`
96			`// fixed more typo bugs`
97			`//`
98	44	gorban	`// Revision 1.22 2001/11/12 15:02:28 mohor`
99			`// lsr1r error fixed.`
100			`//`
101	43	mohor	`// Revision 1.21 2001/11/12 14:57:27 mohor`
102			`// ti_int_pnd error fixed.`
103			`//`
104	42	mohor	`// Revision 1.20 2001/11/12 14:50:27 mohor`
105			`// ti_int_d error fixed.`
106			`//`
107	41	mohor	`// Revision 1.19 2001/11/10 12:43:21 gorban`
108			`// Synthesis bugs fixed. Some other minor changes`
109			`//`
110	40	gorban	`// Revision 1.18 2001/11/08 14:54:23 mohor`
111			`// Comments in Slovene language deleted, few small fixes for better work of`
112			`// old tools. IRQs need to be fix.`
113			`//`
114	39	mohor	`// Revision 1.17 2001/11/07 17:51:52 gorban`
115			`// Heavily rewritten interrupt and LSR subsystems.`
116			`// Many bugs hopefully squashed.`
117			`//`
118	37	gorban	`// Revision 1.16 2001/11/02 09:55:16 mohor`
119			`// no message`
120			`//`
121	36	mohor	`// Revision 1.15 2001/10/31 15:19:22 gorban`
122			`// Fixes to break and timeout conditions`
123			`//`
124	35	gorban	`// Revision 1.14 2001/10/29 17:00:46 gorban`
125			`// fixed parity sending and tx_fifo resets over- and underrun`
126			`//`
127	34	gorban	`// Revision 1.13 2001/10/20 09:58:40 gorban`
128			`// Small synopsis fixes`
129			`//`
130	33	gorban	`// Revision 1.12 2001/10/19 16:21:40 gorban`
131			`// Changes data_out to be synchronous again as it should have been.`
132			`//`
133	32	gorban	`// Revision 1.11 2001/10/18 20:35:45 gorban`
134			`// small fix`
135			`//`
136	31	gorban	`// Revision 1.10 2001/08/24 21:01:12 mohor`
137			`// Things connected to parity changed.`
138			`// Clock devider changed.`
139			`//`
140	29	mohor	`// Revision 1.9 2001/08/23 16:05:05 mohor`
141			`// Stop bit bug fixed.`
142			`// Parity bug fixed.`
143			`// WISHBONE read cycle bug fixed,`
144			`// OE indicator (Overrun Error) bug fixed.`
145			`// PE indicator (Parity Error) bug fixed.`
146			`// Register read bug fixed.`
147			`//`
148	27	mohor	`// Revision 1.10 2001/06/23 11:21:48 gorban`
149			`// DL made 16-bit long. Fixed transmission/reception bugs.`
150			`//`
151			`// Revision 1.9 2001/05/31 20:08:01 gorban`
152			`// FIFO changes and other corrections.`
153			`//`
154			`// Revision 1.8 2001/05/29 20:05:04 gorban`
155			`// Fixed some bugs and synthesis problems.`
156			`//`
157			`// Revision 1.7 2001/05/27 17:37:49 gorban`
158			`// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.`
159			`//`
160			`// Revision 1.6 2001/05/21 19:12:02 gorban`
161			`// Corrected some Linter messages.`
162			`//`
163			`// Revision 1.5 2001/05/17 18:34:18 gorban`
164			`// First 'stable' release. Should be sythesizable now. Also added new header.`
165			`//`
166			`// Revision 1.0 2001-05-17 21:27:11+02 jacob`
167			`// Initial revision`
168			`//`
169			`//`
170
171	33	gorban	`// synopsys translate_off`
172	27	mohor	`include "timescale.v"
173	33	gorban	`// synopsys translate_on`
174
175	27	mohor	`include "uart_defines.v"
176
177			`define UART_DL1 7:0
178			`define UART_DL2 15:8
179
180			`module uart_regs (clk,`
181			`wb_rst_i, wb_addr_i, wb_dat_i, wb_dat_o, wb_we_i, wb_re_i,`
182
183			`// additional signals`
184			`modem_inputs,`
185			`stx_pad_o, srx_pad_i,`
186	48	gorban
187			`ifdef DATA_BUS_WIDTH_8
188			`else
189			`// debug interface signals enabled`
190			`ier, iir, fcr, mcr, lcr, msr, lsr, rf_count, tf_count, tstate, rstate,`
191			`endif
192	27	mohor	`rts_pad_o, dtr_pad_o, int_o`
193			`);`
194
195	37	gorban	`input clk;`
196			`input wb_rst_i;`
197			input [`UART_ADDR_WIDTH-1:0] wb_addr_i;
198			`input [7:0] wb_dat_i;`
199			`output [7:0] wb_dat_o;`
200			`input wb_we_i;`
201			`input wb_re_i;`
202	27	mohor
203	37	gorban	`output stx_pad_o;`
204			`input srx_pad_i;`
205	27	mohor
206	37	gorban	`input [3:0] modem_inputs;`
207			`output rts_pad_o;`
208			`output dtr_pad_o;`
209			`output int_o;`
210	27	mohor
211	48	gorban	`ifdef DATA_BUS_WIDTH_8
212			`else
213			`// if 32-bit databus and debug interface are enabled`
214			`output [3:0] ier;`
215			`output [3:0] iir;`
216			`output [1:0] fcr; /// bits 7 and 6 of fcr. Other bits are ignored`
217			`output [4:0] mcr;`
218			`output [7:0] lcr;`
219			`output [7:0] msr;`
220			`output [7:0] lsr;`
221			output [`UART_FIFO_COUNTER_W-1:0] rf_count;
222			output [`UART_FIFO_COUNTER_W-1:0] tf_count;
223			`output [2:0] tstate;`
224			`output [3:0] rstate;`
225
226			`endif
227
228	37	gorban	`wire [3:0] modem_inputs;`
229			`reg enable;`
230			`wire stx_pad_o; // received from transmitter module`
231			`wire srx_pad_i;`
232	27	mohor
233	37	gorban	`reg [7:0] wb_dat_o;`
234	27	mohor
235	37	gorban	wire [`UART_ADDR_WIDTH-1:0] wb_addr_i;
236			`wire [7:0] wb_dat_i;`
237	27	mohor
238
239	37	gorban	`reg [3:0] ier;`
240			`reg [3:0] iir;`
241			`reg [1:0] fcr; /// bits 7 and 6 of fcr. Other bits are ignored`
242			`reg [4:0] mcr;`
243			`reg [7:0] lcr;`
244			`reg [7:0] msr;`
245			`reg [15:0] dl; // 32-bit divisor latch`
246	52	gorban	`reg [7:0] scratch; // UART scratch register`
247	37	gorban	`reg start_dlc; // activate dlc on writing to UART_DL1`
248			`reg lsr_mask_d; // delay for lsr_mask condition`
249			`reg msi_reset; // reset MSR 4 lower bits indicator`
250	40	gorban	`//reg threi_clear; // THRE interrupt clear flag`
251	37	gorban	`reg [15:0] dlc; // 32-bit divisor latch counter`
252			`reg int_o;`
253	27	mohor
254	37	gorban	`reg [3:0] trigger_level; // trigger level of the receiver FIFO`
255			`reg rx_reset;`
256			`reg tx_reset;`
257	27	mohor
258	37	gorban	`wire dlab; // divisor latch access bit`
259			`wire cts_pad_i, dsr_pad_i, ri_pad_i, dcd_pad_i; // modem status bits`
260			`wire loopback; // loopback bit (MCR bit 4)`
261			`wire cts, dsr, ri, dcd; // effective signals (considering loopback)`
262			`wire rts_pad_o, dtr_pad_o; // modem control outputs`
263	27	mohor
264	37	gorban	`// LSR bits wires and regs`
265			`wire [7:0] lsr;`
266			`wire lsr0, lsr1, lsr2, lsr3, lsr4, lsr5, lsr6, lsr7;`
267			`reg lsr0r, lsr1r, lsr2r, lsr3r, lsr4r, lsr5r, lsr6r, lsr7r;`
268			`wire lsr_mask; // lsr_mask`
269
270	27	mohor	`//`
271			`// ASSINGS`
272			`//`
273
274	37	gorban	`assign lsr[7:0] = { lsr7r, lsr6r, lsr5r, lsr4r, lsr3r, lsr2r, lsr1r, lsr0r };`
275	27	mohor
276	37	gorban	`assign {cts_pad_i, dsr_pad_i, ri_pad_i, dcd_pad_i} = modem_inputs;`
277			assign {cts, dsr, ri, dcd} = loopback ? {mcr[`UART_MC_RTS],mcr[`UART_MC_DTR],mcr[`UART_MC_OUT1],mcr[`UART_MC_OUT2]}
278			`: ~{cts_pad_i,dsr_pad_i,ri_pad_i,dcd_pad_i};`
279
280			assign dlab = lcr[`UART_LC_DL];
281			`assign loopback = mcr[4];`
282
283	27	mohor	`// assign modem outputs`
284	37	gorban	assign rts_pad_o = mcr[`UART_MC_RTS];
285			assign dtr_pad_o = mcr[`UART_MC_DTR];
286	27	mohor
287			`// Interrupt signals`
288	37	gorban	`wire rls_int; // receiver line status interrupt`
289			`wire rda_int; // receiver data available interrupt`
290			`wire ti_int; // timeout indicator interrupt`
291			`wire thre_int; // transmitter holding register empty interrupt`
292			`wire ms_int; // modem status interrupt`
293	27	mohor
294			`// FIFO signals`
295	37	gorban	`reg tf_push;`
296			`reg rf_pop;`
297			wire [`UART_FIFO_REC_WIDTH-1:0] rf_data_out;
298			`wire rf_error_bit; // an error (parity or framing) is inside the fifo`
299			wire [`UART_FIFO_COUNTER_W-1:0] rf_count;
300			wire [`UART_FIFO_COUNTER_W-1:0] tf_count;
301	48	gorban	`wire [2:0] tstate;`
302			`wire [3:0] rstate;`
303	37	gorban	`wire [9:0] counter_t;`
304	27	mohor
305	37	gorban
306	27	mohor	`// Transmitter Instance`
307	48	gorban	`uart_transmitter transmitter(clk, wb_rst_i, lcr, tf_push, wb_dat_i, enable, stx_pad_o, tstate, tf_count, tx_reset, lsr_mask);`
308	27	mohor
309			`// Receiver Instance`
310			`uart_receiver receiver(clk, wb_rst_i, lcr, rf_pop, srx_pad_i, enable, rda_int,`
311	50	gorban	`counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate, rf_push);`
312	27	mohor
313	32	gorban
314	48	gorban	`// Asynchronous reading here because the outputs are sampled in uart_wb.v file`
315	52	gorban	`always @(dl or dlab or ier or iir or scratch`
316	48	gorban	`or lcr or lsr or msr or rf_data_out or wb_addr_i or wb_re_i) // asynchrounous reading`
317	27	mohor	`begin`
318	52	gorban	`case (wb_addr_i)`
319			`UART_REG_RB : wb_dat_o = dlab ? dl[`UART_DL1] : rf_data_out[10:3];
320			`UART_REG_IE : wb_dat_o = dlab ? dl[`UART_DL2] : ier;
321			`UART_REG_II : wb_dat_o = {4'b1100,iir};
322			`UART_REG_LC : wb_dat_o = lcr;
323			`UART_REG_LS : wb_dat_o = lsr;
324			`UART_REG_MS : wb_dat_o = msr;
325			`UART_REG_SR : wb_dat_o = scratch;
326			`default: wb_dat_o = 8'b0; // ??`
327			`endcase // case(wb_addr_i)`
328			`end // always @ (dl or dlab or ier or iir or scratch...`
329	27	mohor
330	52	gorban
331	27	mohor	`// rf_pop signal handling`
332			`always @(posedge clk or posedge wb_rst_i)`
333			`begin`
334			`if (wb_rst_i)`
335			`rf_pop <= #1 0;`
336			`else`
337			`if (rf_pop) // restore the signal to 0 after one clock cycle`
338			`rf_pop <= #1 0;`
339			`else`
340			if (wb_re_i && wb_addr_i == `UART_REG_RB && !dlab)
341			`rf_pop <= #1 1; // advance read pointer`
342			`end`
343
344	37	gorban	`wire lsr_mask_condition;`
345			`wire iir_read;`
346			`wire msr_read;`
347			`wire fifo_read;`
348	45	gorban	`wire fifo_write;`
349	37	gorban
350			assign lsr_mask_condition = (wb_re_i && wb_addr_i == `UART_REG_LS && !dlab);
351			assign iir_read = (wb_re_i && wb_addr_i == `UART_REG_II && !dlab);
352			assign msr_read = (wb_re_i && wb_addr_i == `UART_REG_MS && !dlab);
353			assign fifo_read = (wb_re_i && wb_addr_i == `UART_REG_RB && !dlab);
354	45	gorban	assign fifo_write = (wb_we_i && wb_addr_i == `UART_REG_TR && !dlab);
355	37	gorban
356			`// lsr_mask_d delayed signal handling`
357	27	mohor	`always @(posedge clk or posedge wb_rst_i)`
358			`begin`
359			`if (wb_rst_i)`
360	37	gorban	`lsr_mask_d <= #1 0;`
361			`else // reset bits in the Line Status Register`
362			`lsr_mask_d <= #1 lsr_mask_condition;`
363	27	mohor	`end`
364
365	37	gorban	`// lsr_mask is rise detected`
366			`assign lsr_mask = lsr_mask_condition && ~lsr_mask_d;`
367	27	mohor
368			`// msi_reset signal handling`
369			`always @(posedge clk or posedge wb_rst_i)`
370			`begin`
371			`if (wb_rst_i)`
372			`msi_reset <= #1 0;`
373			`else`
374			`if (msi_reset)`
375			`msi_reset <= #1 0;`
376			`else`
377	47	gorban	`if (msr_read)`
378	27	mohor	`msi_reset <= #1 1; // reset bits in Modem Status Register`
379			`end`
380
381
382			`//`
383			`// WRITES AND RESETS //`
384			`//`
385			`// Line Control Register`
386			`always @(posedge clk or posedge wb_rst_i)`
387			`if (wb_rst_i)`
388			`lcr <= #1 8'b00000011; // 8n1 setting`
389			`else`
390			if (wb_we_i && wb_addr_i==`UART_REG_LC)
391			`lcr <= #1 wb_dat_i;`
392
393			`// Interrupt Enable Register or UART_DL2`
394			`always @(posedge clk or posedge wb_rst_i)`
395			`if (wb_rst_i)`
396			`begin`
397			`ier <= #1 4'b0000; // no interrupts after reset`
398			dl[`UART_DL2] <= #1 8'b0;
399			`end`
400			`else`
401			if (wb_we_i && wb_addr_i==`UART_REG_IE)
402			`if (dlab)`
403			`begin`
404			dl[`UART_DL2] <= #1 wb_dat_i;
405			`end`
406			`else`
407			`ier <= #1 wb_dat_i[3:0]; // ier uses only 4 lsb`
408
409
410			`// FIFO Control Register and rx_reset, tx_reset signals`
411			`always @(posedge clk or posedge wb_rst_i)`
412			`if (wb_rst_i) begin`
413			`fcr <= #1 2'b11;`
414			`rx_reset <= #1 0;`
415			`tx_reset <= #1 0;`
416			`end else`
417			if (wb_we_i && wb_addr_i==`UART_REG_FC) begin
418			`fcr <= #1 wb_dat_i[7:6];`
419			`rx_reset <= #1 wb_dat_i[1];`
420			`tx_reset <= #1 wb_dat_i[2];`
421	37	gorban	`end else begin`
422	27	mohor	`rx_reset <= #1 0;`
423			`tx_reset <= #1 0;`
424			`end`
425
426			`// Modem Control Register`
427			`always @(posedge clk or posedge wb_rst_i)`
428			`if (wb_rst_i)`
429			`mcr <= #1 5'b0;`
430			`else`
431			if (wb_we_i && wb_addr_i==`UART_REG_MC)
432			`mcr <= #1 wb_dat_i[4:0];`
433
434	52	gorban	`// Scratch register`
435			`// Line Control Register`
436			`always @(posedge clk or posedge wb_rst_i)`
437			`if (wb_rst_i)`
438			`scratch <= #1 0; // 8n1 setting`
439			`else`
440			if (wb_we_i && wb_addr_i==`UART_REG_SR)
441			`scratch <= #1 wb_dat_i;`
442
443	27	mohor	`// TX_FIFO or UART_DL1`
444			`always @(posedge clk or posedge wb_rst_i)`
445			`if (wb_rst_i)`
446			`begin`
447			dl[`UART_DL1] <= #1 8'b0;
448			`tf_push <= #1 1'b0;`
449			`start_dlc <= #1 1'b0;`
450			`end`
451			`else`
452			if (wb_we_i && wb_addr_i==`UART_REG_TR)
453			`if (dlab)`
454			`begin`
455			dl[`UART_DL1] <= #1 wb_dat_i;
456			`start_dlc <= #1 1'b1; // enable DL counter`
457			`tf_push <= #1 1'b0;`
458			`end`
459			`else`
460			`begin`
461			`tf_push <= #1 1'b1;`
462			`start_dlc <= #1 1'b0;`
463	37	gorban	`end // else: !if(dlab)`
464	27	mohor	`else`
465			`begin`
466			`start_dlc <= #1 1'b0;`
467			`tf_push <= #1 1'b0;`
468	37	gorban	`end // else: !if(dlab)`
469	27	mohor
470			`// Receiver FIFO trigger level selection logic (asynchronous mux)`
471	31	gorban	`always @(fcr)`
472	27	mohor	case (fcr[`UART_FC_TL])
473			`2'b00 : trigger_level = 1;`
474			`2'b01 : trigger_level = 4;`
475			`2'b10 : trigger_level = 8;`
476			`2'b11 : trigger_level = 14;`
477	37	gorban	endcase // case(fcr[`UART_FC_TL])
478	27	mohor
479			`//`
480			`// STATUS REGISTERS //`
481			`//`
482
483			`// Modem Status Register`
484			`always @(posedge clk or posedge wb_rst_i)`
485			`begin`
486			`if (wb_rst_i)`
487			`msr <= #1 0;`
488			`else begin`
489			msr[`UART_MS_DDCD:`UART_MS_DCTS] <= #1 msi_reset ? 4'b0 :
490			msr[`UART_MS_DDCD:`UART_MS_DCTS] \| ({dcd, ri, dsr, cts} ^ msr[`UART_MS_CDCD:`UART_MS_CCTS]);
491			msr[`UART_MS_CDCD:`UART_MS_CCTS] <= #1 {dcd, ri, dsr, cts};
492			`end`
493			`end`
494
495			`// Line Status Register`
496	37	gorban
497			`// activation conditions`
498	50	gorban	`assign lsr0 = (rf_count==0 && rf_push); // data in receiver fifo available set condition`
499	37	gorban	`assign lsr1 = rf_overrun; // Receiver overrun error`
500			`assign lsr2 = rf_data_out[1]; // parity error bit`

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[/] [uart16550/] [trunk/] [rtl/] [verilog/] [uart_regs.v] - Blame information for rev 56