| 1 |
79 |
gorban |
//////////////////////////////////////////////////////////////////////
|
| 2 |
|
|
//// ////
|
| 3 |
|
|
//// uart_tfifo.v ////
|
| 4 |
|
|
//// ////
|
| 5 |
|
|
//// ////
|
| 6 |
|
|
//// This file is part of the "UART 16550 compatible" project ////
|
| 7 |
|
|
//// http://www.opencores.org/cores/uart16550/ ////
|
| 8 |
|
|
//// ////
|
| 9 |
|
|
//// Documentation related to this project: ////
|
| 10 |
|
|
//// - http://www.opencores.org/cores/uart16550/ ////
|
| 11 |
|
|
//// ////
|
| 12 |
|
|
//// Projects compatibility: ////
|
| 13 |
|
|
//// - WISHBONE ////
|
| 14 |
|
|
//// RS232 Protocol ////
|
| 15 |
|
|
//// 16550D uart (mostly supported) ////
|
| 16 |
|
|
//// ////
|
| 17 |
|
|
//// Overview (main Features): ////
|
| 18 |
|
|
//// UART core transmitter FIFO ////
|
| 19 |
|
|
//// ////
|
| 20 |
|
|
//// To Do: ////
|
| 21 |
|
|
//// Nothing. ////
|
| 22 |
|
|
//// ////
|
| 23 |
|
|
//// Author(s): ////
|
| 24 |
|
|
//// - gorban@opencores.org ////
|
| 25 |
|
|
//// - Jacob Gorban ////
|
| 26 |
|
|
//// - Igor Mohor (igorm@opencores.org) ////
|
| 27 |
|
|
//// ////
|
| 28 |
|
|
//// Created: 2001/05/12 ////
|
| 29 |
|
|
//// Last Updated: 2002/07/22 ////
|
| 30 |
|
|
//// (See log for the revision history) ////
|
| 31 |
|
|
//// ////
|
| 32 |
|
|
//// ////
|
| 33 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 34 |
|
|
//// ////
|
| 35 |
|
|
//// Copyright (C) 2000, 2001 Authors ////
|
| 36 |
|
|
//// ////
|
| 37 |
|
|
//// This source file may be used and distributed without ////
|
| 38 |
|
|
//// restriction provided that this copyright statement is not ////
|
| 39 |
|
|
//// removed from the file and that any derivative work contains ////
|
| 40 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
| 41 |
|
|
//// ////
|
| 42 |
|
|
//// This source file is free software; you can redistribute it ////
|
| 43 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
| 44 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
| 45 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
| 46 |
|
|
//// later version. ////
|
| 47 |
|
|
//// ////
|
| 48 |
|
|
//// This source is distributed in the hope that it will be ////
|
| 49 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
| 50 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
| 51 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
| 52 |
|
|
//// details. ////
|
| 53 |
|
|
//// ////
|
| 54 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
| 55 |
|
|
//// Public License along with this source; if not, download it ////
|
| 56 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
| 57 |
|
|
//// ////
|
| 58 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 59 |
|
|
//
|
| 60 |
|
|
// CVS Revision History
|
| 61 |
|
|
//
|
| 62 |
|
|
// $Log: not supported by cvs2svn $
|
| 63 |
|
|
// Revision 1.16 2001/12/20 13:25:46 mohor
|
| 64 |
|
|
// rx push changed to be only one cycle wide.
|
| 65 |
|
|
//
|
| 66 |
|
|
// Revision 1.15 2001/12/18 09:01:07 mohor
|
| 67 |
|
|
// Bug that was entered in the last update fixed (rx state machine).
|
| 68 |
|
|
//
|
| 69 |
|
|
// Revision 1.14 2001/12/17 14:46:48 mohor
|
| 70 |
|
|
// overrun signal was moved to separate block because many sequential lsr
|
| 71 |
|
|
// reads were preventing data from being written to rx fifo.
|
| 72 |
|
|
// underrun signal was not used and was removed from the project.
|
| 73 |
|
|
//
|
| 74 |
|
|
// Revision 1.13 2001/11/26 21:38:54 gorban
|
| 75 |
|
|
// Lots of fixes:
|
| 76 |
|
|
// Break condition wasn't handled correctly at all.
|
| 77 |
|
|
// LSR bits could lose their values.
|
| 78 |
|
|
// LSR value after reset was wrong.
|
| 79 |
|
|
// Timing of THRE interrupt signal corrected.
|
| 80 |
|
|
// LSR bit 0 timing corrected.
|
| 81 |
|
|
//
|
| 82 |
|
|
// Revision 1.12 2001/11/08 14:54:23 mohor
|
| 83 |
|
|
// Comments in Slovene language deleted, few small fixes for better work of
|
| 84 |
|
|
// old tools. IRQs need to be fix.
|
| 85 |
|
|
//
|
| 86 |
|
|
// Revision 1.11 2001/11/07 17:51:52 gorban
|
| 87 |
|
|
// Heavily rewritten interrupt and LSR subsystems.
|
| 88 |
|
|
// Many bugs hopefully squashed.
|
| 89 |
|
|
//
|
| 90 |
|
|
// Revision 1.10 2001/10/20 09:58:40 gorban
|
| 91 |
|
|
// Small synopsis fixes
|
| 92 |
|
|
//
|
| 93 |
|
|
// Revision 1.9 2001/08/24 21:01:12 mohor
|
| 94 |
|
|
// Things connected to parity changed.
|
| 95 |
|
|
// Clock devider changed.
|
| 96 |
|
|
//
|
| 97 |
|
|
// Revision 1.8 2001/08/24 08:48:10 mohor
|
| 98 |
|
|
// FIFO was not cleared after the data was read bug fixed.
|
| 99 |
|
|
//
|
| 100 |
|
|
// Revision 1.7 2001/08/23 16:05:05 mohor
|
| 101 |
|
|
// Stop bit bug fixed.
|
| 102 |
|
|
// Parity bug fixed.
|
| 103 |
|
|
// WISHBONE read cycle bug fixed,
|
| 104 |
|
|
// OE indicator (Overrun Error) bug fixed.
|
| 105 |
|
|
// PE indicator (Parity Error) bug fixed.
|
| 106 |
|
|
// Register read bug fixed.
|
| 107 |
|
|
//
|
| 108 |
|
|
// Revision 1.3 2001/05/31 20:08:01 gorban
|
| 109 |
|
|
// FIFO changes and other corrections.
|
| 110 |
|
|
//
|
| 111 |
|
|
// Revision 1.3 2001/05/27 17:37:48 gorban
|
| 112 |
|
|
// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
|
| 113 |
|
|
//
|
| 114 |
|
|
// Revision 1.2 2001/05/17 18:34:18 gorban
|
| 115 |
|
|
// First 'stable' release. Should be sythesizable now. Also added new header.
|
| 116 |
|
|
//
|
| 117 |
|
|
// Revision 1.0 2001-05-17 21:27:12+02 jacob
|
| 118 |
|
|
// Initial revision
|
| 119 |
|
|
//
|
| 120 |
|
|
//
|
| 121 |
|
|
|
| 122 |
|
|
// synopsys translate_off
|
| 123 |
|
|
`include "timescale.v"
|
| 124 |
|
|
// synopsys translate_on
|
| 125 |
|
|
|
| 126 |
|
|
//`include "uart_defines.v"
|
| 127 |
|
|
|
| 128 |
|
|
module uart_tfifo (clk,
|
| 129 |
|
|
wb_rst_i, data_in, data_out,
|
| 130 |
|
|
// Control signals
|
| 131 |
|
|
push, // push strobe, active high
|
| 132 |
|
|
pop, // pop strobe, active high
|
| 133 |
|
|
// status signals
|
| 134 |
|
|
overrun,
|
| 135 |
|
|
count,
|
| 136 |
|
|
fifo_reset,
|
| 137 |
|
|
reset_status
|
| 138 |
|
|
);
|
| 139 |
|
|
|
| 140 |
|
|
|
| 141 |
|
|
// FIFO parameters
|
| 142 |
|
|
parameter fifo_width = `UART_FIFO_WIDTH;
|
| 143 |
|
|
parameter fifo_depth = `UART_FIFO_DEPTH;
|
| 144 |
|
|
parameter fifo_pointer_w = `UART_FIFO_POINTER_W;
|
| 145 |
|
|
parameter fifo_counter_w = `UART_FIFO_COUNTER_W;
|
| 146 |
|
|
|
| 147 |
|
|
input clk;
|
| 148 |
|
|
input wb_rst_i;
|
| 149 |
|
|
input push;
|
| 150 |
|
|
input pop;
|
| 151 |
|
|
input [fifo_width-1:0] data_in;
|
| 152 |
|
|
input fifo_reset;
|
| 153 |
|
|
input reset_status;
|
| 154 |
|
|
|
| 155 |
|
|
output [fifo_width-1:0] data_out;
|
| 156 |
|
|
output overrun;
|
| 157 |
|
|
output [fifo_counter_w-1:0] count;
|
| 158 |
|
|
|
| 159 |
|
|
wire [fifo_width-1:0] data_out;
|
| 160 |
|
|
|
| 161 |
|
|
// FIFO pointers
|
| 162 |
|
|
reg [fifo_pointer_w-1:0] top;
|
| 163 |
|
|
reg [fifo_pointer_w-1:0] bottom;
|
| 164 |
|
|
|
| 165 |
|
|
reg [fifo_counter_w-1:0] count;
|
| 166 |
|
|
reg overrun;
|
| 167 |
|
|
wire [fifo_pointer_w-1:0] top_plus_1 = top + 1'b1;
|
| 168 |
|
|
|
| 169 |
|
|
raminfr #(fifo_pointer_w,fifo_width,fifo_depth) tfifo
|
| 170 |
|
|
(.clk(clk),
|
| 171 |
|
|
.we(push),
|
| 172 |
|
|
.a(top),
|
| 173 |
|
|
.dpra(bottom),
|
| 174 |
|
|
.di(data_in),
|
| 175 |
|
|
.dpo(data_out)
|
| 176 |
|
|
);
|
| 177 |
|
|
|
| 178 |
|
|
|
| 179 |
|
|
always @(posedge clk or posedge wb_rst_i) // synchronous FIFO
|
| 180 |
|
|
begin
|
| 181 |
|
|
if (wb_rst_i)
|
| 182 |
|
|
begin
|
| 183 |
|
|
top <= #1 0;
|
| 184 |
|
|
bottom <= #1 1'b0;
|
| 185 |
|
|
count <= #1 0;
|
| 186 |
|
|
end
|
| 187 |
|
|
else
|
| 188 |
|
|
if (fifo_reset) begin
|
| 189 |
|
|
top <= #1 0;
|
| 190 |
|
|
bottom <= #1 1'b0;
|
| 191 |
|
|
count <= #1 0;
|
| 192 |
|
|
end
|
| 193 |
|
|
else
|
| 194 |
|
|
begin
|
| 195 |
|
|
case ({push, pop})
|
| 196 |
|
|
2'b10 : if (count<fifo_depth) // overrun condition
|
| 197 |
|
|
begin
|
| 198 |
|
|
top <= #1 top_plus_1;
|
| 199 |
|
|
count <= #1 count + 1'b1;
|
| 200 |
|
|
end
|
| 201 |
|
|
2'b01 : if(count>0)
|
| 202 |
|
|
begin
|
| 203 |
|
|
bottom <= #1 bottom + 1'b1;
|
| 204 |
|
|
count <= #1 count - 1'b1;
|
| 205 |
|
|
end
|
| 206 |
|
|
2'b11 : begin
|
| 207 |
|
|
bottom <= #1 bottom + 1'b1;
|
| 208 |
|
|
top <= #1 top_plus_1;
|
| 209 |
|
|
end
|
| 210 |
|
|
default: ;
|
| 211 |
|
|
endcase
|
| 212 |
|
|
end
|
| 213 |
|
|
end // always
|
| 214 |
|
|
|
| 215 |
|
|
always @(posedge clk or posedge wb_rst_i) // synchronous FIFO
|
| 216 |
|
|
begin
|
| 217 |
|
|
if (wb_rst_i)
|
| 218 |
|
|
overrun <= #1 1'b0;
|
| 219 |
|
|
else
|
| 220 |
|
|
if(fifo_reset | reset_status)
|
| 221 |
|
|
overrun <= #1 1'b0;
|
| 222 |
|
|
else
|
| 223 |
|
|
if(push & (count==fifo_depth))
|
| 224 |
|
|
overrun <= #1 1'b1;
|
| 225 |
|
|
end // always
|
| 226 |
|
|
|
| 227 |
|
|
endmodule
|
