URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

[/] [uart16550/] [trunk/] [rtl/] [verilog/] [uart_top.v] - Blame information for rev 48

Go to most recent revision | Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  uart_top.v                                                  ////
////                                                              ////
////                                                              ////
////  This file is part of the "UART 16550 compatible" project    ////
////  http://www.opencores.org/cores/uart16550/                   ////
////                                                              ////
////  Documentation related to this project:                      ////
////  - http://www.opencores.org/cores/uart16550/                 ////
////                                                              ////
////  Projects compatibility:                                     ////
////  - WISHBONE                                                  ////
////  RS232 Protocol                                              ////
////  16550D uart (mostly supported)                              ////
////                                                              ////
////  Overview (main Features):                                   ////
////  UART core top level.                                        ////
////                                                              ////
////  Known problems (limits):                                    ////
////  Note that transmitter and receiver instances are inside     ////
////  the uart_regs.v file.                                       ////
////                                                              ////
////  To Do:                                                      ////
////  Nothing so far.                                             ////
////                                                              ////
////  Author(s):                                                  ////
////      - gorban@opencores.org                                  ////
////      - Jacob Gorban                                          ////
////      - Igor Mohor (igorm@opencores.org)                      ////
////                                                              ////
////  Created:        2001/05/12                                  ////
////  Last Updated:   2001/05/17                                  ////
////                  (See log for the revision history)          ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000, 2001 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.14  2001/11/07 17:51:52  gorban
// Heavily rewritten interrupt and LSR subsystems.
// Many bugs hopefully squashed.
//
// Revision 1.13  2001/10/20 09:58:40  gorban
// Small synopsis fixes
//
// Revision 1.12  2001/08/25 15:46:19  gorban
// Modified port names again
//
// Revision 1.11  2001/08/24 21:01:12  mohor
// Things connected to parity changed.
// Clock devider changed.
//
// Revision 1.10  2001/08/23 16:05:05  mohor
// Stop bit bug fixed.
// Parity bug fixed.
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
//
// Revision 1.4  2001/05/31 20:08:01  gorban
// FIFO changes and other corrections.
//
// Revision 1.3  2001/05/21 19:12:02  gorban
// Corrected some Linter messages.
//
// Revision 1.2  2001/05/17 18:34:18  gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0  2001-05-17 21:27:12+02  jacob
// Initial revision
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
`include "uart_defines.v"
 
module uart_top (
        wb_clk_i,
 
        // Wishbone signals
        wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o, wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_sel_i,
        int_o, // interrupt request
 
        // UART signals
        // serial input/output
        stx_pad_o, srx_pad_i,
 
        // modem signals
        rts_pad_o, cts_pad_i, dtr_pad_o, dsr_pad_i, ri_pad_i, dcd_pad_i
 
        );
 
parameter                                                        uart_data_width = `UART_DATA_WIDTH;
parameter                                                        uart_addr_width = `UART_ADDR_WIDTH;
 
input                                                            wb_clk_i;
 
// WISHBONE interface
input                                                            wb_rst_i;
input [uart_addr_width-1:0]       wb_adr_i;
input [uart_data_width-1:0]       wb_dat_i;
output [uart_data_width-1:0]      wb_dat_o;
input                                                            wb_we_i;
input                                                            wb_stb_i;
input                                                            wb_cyc_i;
input [3:0]                                                       wb_sel_i;
output                                                           wb_ack_o;
output                                                           int_o;
 
// UART signals
input                                                            srx_pad_i;
output                                                           stx_pad_o;
output                                                           rts_pad_o;
input                                                            cts_pad_i;
output                                                           dtr_pad_o;
input                                                            dsr_pad_i;
input                                                            ri_pad_i;
input                                                            dcd_pad_i;
 
wire                                                                     stx_pad_o;
wire                                                                     rts_pad_o;
wire                                                                     dtr_pad_o;
 
wire [uart_addr_width-1:0]        wb_adr_i;
wire [uart_data_width-1:0]        wb_dat_i;
wire [uart_data_width-1:0]        wb_dat_o;
 
wire [7:0]                                                        wb_dat8_i; // 8-bit internal data input
wire [7:0]                                                        wb_dat8_o; // 8-bit internal data output
wire [31:0]                                               wb_dat32_o; // debug interface 32-bit output
wire [3:0]                                                        wb_sel_i;  // WISHBONE select signal
wire                                                                     we_o;  // Write enable for registers
wire                                 re_o;      // Read enable for registers
//
// MODULE INSTANCES
//
 
`ifdef DATA_BUS_WIDTH_8
`else
// debug interface wires
wire    [3:0] ier;
wire    [3:0] iir;
wire    [1:0] fcr;
wire    [4:0] mcr;
wire    [7:0] lcr;
wire    [7:0] msr;
wire    [7:0] lsr;
wire    [`UART_FIFO_COUNTER_W-1:0] rf_count;
wire    [`UART_FIFO_COUNTER_W-1:0] tf_count;
wire    [2:0] tstate;
wire    [3:0] rstate;
`endif
 
`ifdef DATA_BUS_WIDTH_8
////  WISHBONE interface module
uart_wb         wb_interface(
                .clk(           wb_clk_i                ),
                .wb_rst_i(      wb_rst_i        ),
        .wb_dat_i(wb_dat_i),
        .wb_dat_o(wb_dat_o),
        .wb_dat8_i(wb_dat8_i),
        .wb_dat8_o(wb_dat8_o),
         .wb_dat32_o(32'b0),
         .wb_sel_i(4'b0),
                .wb_we_i(       wb_we_i         ),
                .wb_stb_i(      wb_stb_i        ),
                .wb_cyc_i(      wb_cyc_i        ),
                .wb_ack_o(      wb_ack_o        ),
                .we_o(          we_o            ),
                .re_o(re_o)
                );
`else // !`ifdef DATA_BUS_WIDTH_8
uart_wb         wb_interface(
                .clk(           wb_clk_i                ),
                .wb_rst_i(      wb_rst_i        ),
        .wb_dat_i(wb_dat_i),
        .wb_dat_o(wb_dat_o),
        .wb_dat8_i(wb_dat8_i),
        .wb_dat8_o(wb_dat8_o),
         .wb_sel_i(wb_sel_i),
         .wb_dat32_o(wb_dat32_o),
                .wb_we_i(       wb_we_i         ),
                .wb_stb_i(      wb_stb_i        ),
                .wb_cyc_i(      wb_cyc_i        ),
                .wb_ack_o(      wb_ack_o        ),
                .we_o(          we_o            ),
                .re_o(re_o)
                );
`endif // !`ifdef DATA_BUS_WIDTH_8
 
// Registers
uart_regs       regs(
        .clk(           wb_clk_i                ),
        .wb_rst_i(      wb_rst_i        ),
        .wb_addr_i(     wb_adr_i        ),
        .wb_dat_i(      wb_dat8_i       ),
        .wb_dat_o(      wb_dat8_o       ),
        .wb_we_i(       we_o            ),
   .wb_re_i(re_o),
        .modem_inputs(  {cts_pad_i, dsr_pad_i,
        ri_pad_i,  dcd_pad_i}   ),
        .stx_pad_o(             stx_pad_o               ),
        .srx_pad_i(             srx_pad_i               ),
`ifdef DATA_BUS_WIDTH_8
`else
// debug interface signals      enabled
.ier(ier),
.iir(iir),
.fcr(fcr),
.mcr(mcr),
.lcr(lcr),
.msr(msr),
.lsr(lsr),
.rf_count(rf_count),
.tf_count(tf_count),
.tstate(tstate),
.rstate(rstate),
`endif
        .rts_pad_o(             rts_pad_o               ),
        .dtr_pad_o(             dtr_pad_o               ),
        .int_o(         int_o           )
);
 
`ifdef DATA_BUS_WIDTH_8
`else
uart_debug_if dbg(/*AUTOINST*/
                                                // Outputs
                                                .wb_dat32_o                              (wb_dat32_o[31:0]),
                                                // Inputs
                                                .wb_clk_i                                (wb_clk_i),
                                                .wb_rst_i                                (wb_rst_i),
                                                .wb_adr_i                                (wb_adr_i[`UART_ADDR_WIDTH-1:0]),
                                                .re_o                                            (re_o),
                                                .ier                                             (ier[3:0]),
                                                .iir                                             (iir[3:0]),
                                                .fcr                                             (fcr[1:0]),
                                                .mcr                                             (mcr[4:0]),
                                                .lcr                                             (lcr[7:0]),
                                                .msr                                             (msr[7:0]),
                                                .lsr                                             (lsr[7:0]),
                                                .rf_count                                (rf_count[`UART_FIFO_COUNTER_W-1:0]),
                                                .tf_count                                (tf_count[`UART_FIFO_COUNTER_W-1:0]),
                                                .tstate                                  (tstate[2:0]),
                                                .rstate                                  (rstate[3:0]));
`endif //  `ifdef DATA_BUS_WIDTH_8
 
endmodule
 
 

Line No.	Rev	Author	Line
1	27	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// uart_top.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the "UART 16550 compatible" project ////`
7			`//// http://www.opencores.org/cores/uart16550/ ////`
8			`//// ////`
9			`//// Documentation related to this project: ////`
10			`//// - http://www.opencores.org/cores/uart16550/ ////`
11			`//// ////`
12			`//// Projects compatibility: ////`
13			`//// - WISHBONE ////`
14			`//// RS232 Protocol ////`
15			`//// 16550D uart (mostly supported) ////`
16			`//// ////`
17			`//// Overview (main Features): ////`
18			`//// UART core top level. ////`
19			`//// ////`
20			`//// Known problems (limits): ////`
21			`//// Note that transmitter and receiver instances are inside ////`
22			`//// the uart_regs.v file. ////`
23			`//// ////`
24			`//// To Do: ////`
25			`//// Nothing so far. ////`
26			`//// ////`
27			`//// Author(s): ////`
28			`//// - gorban@opencores.org ////`
29			`//// - Jacob Gorban ////`
30	29	mohor	`//// - Igor Mohor (igorm@opencores.org) ////`
31	27	mohor	`//// ////`
32			`//// Created: 2001/05/12 ////`
33			`//// Last Updated: 2001/05/17 ////`
34			`//// (See log for the revision history) ////`
35			`//// ////`
36			`//// ////`
37			`//////////////////////////////////////////////////////////////////////`
38			`//// ////`
39	29	mohor	`//// Copyright (C) 2000, 2001 Authors ////`
40	27	mohor	`//// ////`
41			`//// This source file may be used and distributed without ////`
42			`//// restriction provided that this copyright statement is not ////`
43			`//// removed from the file and that any derivative work contains ////`
44			`//// the original copyright notice and the associated disclaimer. ////`
45			`//// ////`
46			`//// This source file is free software; you can redistribute it ////`
47			`//// and/or modify it under the terms of the GNU Lesser General ////`
48			`//// Public License as published by the Free Software Foundation; ////`
49			`//// either version 2.1 of the License, or (at your option) any ////`
50			`//// later version. ////`
51			`//// ////`
52			`//// This source is distributed in the hope that it will be ////`
53			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
54			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
55			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
56			`//// details. ////`
57			`//// ////`
58			`//// You should have received a copy of the GNU Lesser General ////`
59			`//// Public License along with this source; if not, download it ////`
60			`//// from http://www.opencores.org/lgpl.shtml ////`
61			`//// ////`
62			`//////////////////////////////////////////////////////////////////////`
63			`//`
64			`// CVS Revision History`
65			`//`
66			`// $Log: not supported by cvs2svn $`
67	48	gorban	`// Revision 1.14 2001/11/07 17:51:52 gorban`
68			`// Heavily rewritten interrupt and LSR subsystems.`
69			`// Many bugs hopefully squashed.`
70			`//`
71	37	gorban	`// Revision 1.13 2001/10/20 09:58:40 gorban`
72			`// Small synopsis fixes`
73			`//`
74	33	gorban	`// Revision 1.12 2001/08/25 15:46:19 gorban`
75			`// Modified port names again`
76			`//`
77	30	gorban	`// Revision 1.11 2001/08/24 21:01:12 mohor`
78			`// Things connected to parity changed.`
79			`// Clock devider changed.`
80			`//`
81	29	mohor	`// Revision 1.10 2001/08/23 16:05:05 mohor`
82			`// Stop bit bug fixed.`
83			`// Parity bug fixed.`
84			`// WISHBONE read cycle bug fixed,`
85			`// OE indicator (Overrun Error) bug fixed.`
86			`// PE indicator (Parity Error) bug fixed.`
87			`// Register read bug fixed.`
88			`//`
89	27	mohor	`// Revision 1.4 2001/05/31 20:08:01 gorban`
90			`// FIFO changes and other corrections.`
91			`//`
92			`// Revision 1.3 2001/05/21 19:12:02 gorban`
93			`// Corrected some Linter messages.`
94			`//`
95			`// Revision 1.2 2001/05/17 18:34:18 gorban`
96			`// First 'stable' release. Should be sythesizable now. Also added new header.`
97			`//`
98			`// Revision 1.0 2001-05-17 21:27:12+02 jacob`
99			`// Initial revision`
100			`//`
101			`//`
102	33	gorban	`// synopsys translate_off`
103			`include "timescale.v"
104			`// synopsys translate_on`
105	27	mohor
106			`include "uart_defines.v"
107
108			`module uart_top (`
109	30	gorban	`wb_clk_i,`
110	27	mohor
111			`// Wishbone signals`
112	48	gorban	`wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o, wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_sel_i,`
113	27	mohor	`int_o, // interrupt request`
114
115			`// UART signals`
116			`// serial input/output`
117			`stx_pad_o, srx_pad_i,`
118
119			`// modem signals`
120			`rts_pad_o, cts_pad_i, dtr_pad_o, dsr_pad_i, ri_pad_i, dcd_pad_i`
121
122			`);`
123
124	48	gorban	parameter uart_data_width = `UART_DATA_WIDTH;
125	27	mohor	parameter uart_addr_width = `UART_ADDR_WIDTH;
126
127	30	gorban	`input wb_clk_i;`
128	27	mohor
129			`// WISHBONE interface`
130			`input wb_rst_i;`
131	30	gorban	`input [uart_addr_width-1:0] wb_adr_i;`
132	27	mohor	`input [uart_data_width-1:0] wb_dat_i;`
133			`output [uart_data_width-1:0] wb_dat_o;`
134			`input wb_we_i;`
135			`input wb_stb_i;`
136			`input wb_cyc_i;`
137	48	gorban	`input [3:0] wb_sel_i;`
138	27	mohor	`output wb_ack_o;`
139			`output int_o;`
140
141			`// UART signals`
142			`input srx_pad_i;`
143			`output stx_pad_o;`
144			`output rts_pad_o;`
145			`input cts_pad_i;`
146			`output dtr_pad_o;`
147			`input dsr_pad_i;`
148			`input ri_pad_i;`
149			`input dcd_pad_i;`
150
151			`wire stx_pad_o;`
152			`wire rts_pad_o;`
153			`wire dtr_pad_o;`
154
155	30	gorban	`wire [uart_addr_width-1:0] wb_adr_i;`
156	27	mohor	`wire [uart_data_width-1:0] wb_dat_i;`
157			`wire [uart_data_width-1:0] wb_dat_o;`
158
159	48	gorban	`wire [7:0] wb_dat8_i; // 8-bit internal data input`
160			`wire [7:0] wb_dat8_o; // 8-bit internal data output`
161			`wire [31:0] wb_dat32_o; // debug interface 32-bit output`
162			`wire [3:0] wb_sel_i; // WISHBONE select signal`
163	27	mohor	`wire we_o; // Write enable for registers`
164	48	gorban	`wire re_o; // Read enable for registers`
165	27	mohor	`//`
166			`// MODULE INSTANCES`
167			`//`
168
169	48	gorban	`ifdef DATA_BUS_WIDTH_8
170			`else
171			`// debug interface wires`
172			`wire [3:0] ier;`
173			`wire [3:0] iir;`
174			`wire [1:0] fcr;`
175			`wire [4:0] mcr;`
176			`wire [7:0] lcr;`
177			`wire [7:0] msr;`
178			`wire [7:0] lsr;`
179			wire [`UART_FIFO_COUNTER_W-1:0] rf_count;
180			wire [`UART_FIFO_COUNTER_W-1:0] tf_count;
181			`wire [2:0] tstate;`
182			`wire [3:0] rstate;`
183			`endif
184
185			`ifdef DATA_BUS_WIDTH_8
186	27	mohor	`//// WISHBONE interface module`
187			`uart_wb wb_interface(`
188	30	gorban	`.clk( wb_clk_i ),`
189	27	mohor	`.wb_rst_i( wb_rst_i ),`
190	48	gorban	`.wb_dat_i(wb_dat_i),`
191			`.wb_dat_o(wb_dat_o),`
192			`.wb_dat8_i(wb_dat8_i),`
193			`.wb_dat8_o(wb_dat8_o),`
194			`.wb_dat32_o(32'b0),`
195			`.wb_sel_i(4'b0),`
196	27	mohor	`.wb_we_i( wb_we_i ),`
197			`.wb_stb_i( wb_stb_i ),`
198			`.wb_cyc_i( wb_cyc_i ),`
199			`.wb_ack_o( wb_ack_o ),`
200			`.we_o( we_o ),`
201			`.re_o(re_o)`
202			`);`
203	48	gorban	`else // !`ifdef DATA_BUS_WIDTH_8
204			`uart_wb wb_interface(`
205			`.clk( wb_clk_i ),`
206			`.wb_rst_i( wb_rst_i ),`
207			`.wb_dat_i(wb_dat_i),`
208			`.wb_dat_o(wb_dat_o),`
209			`.wb_dat8_i(wb_dat8_i),`
210			`.wb_dat8_o(wb_dat8_o),`
211			`.wb_sel_i(wb_sel_i),`
212			`.wb_dat32_o(wb_dat32_o),`
213			`.wb_we_i( wb_we_i ),`
214			`.wb_stb_i( wb_stb_i ),`
215			`.wb_cyc_i( wb_cyc_i ),`
216			`.wb_ack_o( wb_ack_o ),`
217			`.we_o( we_o ),`
218			`.re_o(re_o)`
219			`);`
220			`endif // !`ifdef DATA_BUS_WIDTH_8
221	27	mohor
222			`// Registers`
223			`uart_regs regs(`
224	37	gorban	`.clk( wb_clk_i ),`
225			`.wb_rst_i( wb_rst_i ),`
226			`.wb_addr_i( wb_adr_i ),`
227	48	gorban	`.wb_dat_i( wb_dat8_i ),`
228			`.wb_dat_o( wb_dat8_o ),`
229	37	gorban	`.wb_we_i( we_o ),`
230			`.wb_re_i(re_o),`
231			`.modem_inputs( {cts_pad_i, dsr_pad_i,`
232			`ri_pad_i, dcd_pad_i} ),`
233			`.stx_pad_o( stx_pad_o ),`
234			`.srx_pad_i( srx_pad_i ),`
235	48	gorban	`ifdef DATA_BUS_WIDTH_8
236			`else
237			`// debug interface signals enabled`
238			`.ier(ier),`
239			`.iir(iir),`
240			`.fcr(fcr),`
241			`.mcr(mcr),`
242			`.lcr(lcr),`
243			`.msr(msr),`
244			`.lsr(lsr),`
245			`.rf_count(rf_count),`
246			`.tf_count(tf_count),`
247			`.tstate(tstate),`
248			`.rstate(rstate),`
249			`endif
250	37	gorban	`.rts_pad_o( rts_pad_o ),`
251			`.dtr_pad_o( dtr_pad_o ),`
252			`.int_o( int_o )`
253			`);`
254	27	mohor
255	48	gorban	`ifdef DATA_BUS_WIDTH_8
256			`else
257			`uart_debug_if dbg(/AUTOINST/`
258			`// Outputs`
259			`.wb_dat32_o (wb_dat32_o[31:0]),`
260			`// Inputs`
261			`.wb_clk_i (wb_clk_i),`
262			`.wb_rst_i (wb_rst_i),`
263			.wb_adr_i (wb_adr_i[`UART_ADDR_WIDTH-1:0]),
264			`.re_o (re_o),`
265			`.ier (ier[3:0]),`
266			`.iir (iir[3:0]),`
267			`.fcr (fcr[1:0]),`
268			`.mcr (mcr[4:0]),`
269			`.lcr (lcr[7:0]),`
270			`.msr (msr[7:0]),`
271			`.lsr (lsr[7:0]),`
272			.rf_count (rf_count[`UART_FIFO_COUNTER_W-1:0]),
273			.tf_count (tf_count[`UART_FIFO_COUNTER_W-1:0]),
274			`.tstate (tstate[2:0]),`
275			`.rstate (rstate[3:0]));`
276			`endif // `ifdef DATA_BUS_WIDTH_8
277
278	27	mohor	`endmodule`
279	48	gorban
280

Browse

Tools

Subversion Repositories uart16550

[/] [uart16550/] [trunk/] [rtl/] [verilog/] [uart_top.v] - Blame information for rev 48