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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  uart_transmitter.v                                          ////
////                                                              ////
////                                                              ////
////  This file is part of the "UART 16550 compatible" project    ////
////  http://www.opencores.org/cores/uart16550/                   ////
////                                                              ////
////  Documentation related to this project:                      ////
////  - http://www.opencores.org/cores/uart16550/                 ////
////                                                              ////
////  Projects compatibility:                                     ////
////  - WISHBONE                                                  ////
////  RS232 Protocol                                              ////
////  16550D uart (mostly supported)                              ////
////                                                              ////
////  Overview (main Features):                                   ////
////  UART core transmitter logic                                 ////
////                                                              ////
////  Known problems (limits):                                    ////
////  None known                                                  ////
////                                                              ////
////  To Do:                                                      ////
////  Thourough testing.                                          ////
////                                                              ////
////  Author(s):                                                  ////
////      - gorban@opencores.org                                  ////
////      - Jacob Gorban                                          ////
////      - Igor Mohor (igorm@opencores.org)                      ////
////                                                              ////
////  Created:        2001/05/12                                  ////
////  Last Updated:   2001/05/17                                  ////
////                  (See log for the revision history)          ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000, 2001 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.16  2002/01/08 11:29:40  mohor
// tf_pop was too wide. Now it is only 1 clk cycle width.
//
// Revision 1.15  2001/12/17 14:46:48  mohor
// overrun signal was moved to separate block because many sequential lsr
// reads were preventing data from being written to rx fifo.
// underrun signal was not used and was removed from the project.
//
// Revision 1.14  2001/12/03 21:44:29  gorban
// Updated specification documentation.
// Added full 32-bit data bus interface, now as default.
// Address is 5-bit wide in 32-bit data bus mode.
// Added wb_sel_i input to the core. It's used in the 32-bit mode.
// Added debug interface with two 32-bit read-only registers in 32-bit mode.
// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
// My small test bench is modified to work with 32-bit mode.
//
// Revision 1.13  2001/11/08 14:54:23  mohor
// Comments in Slovene language deleted, few small fixes for better work of
// old tools. IRQs need to be fix.
//
// Revision 1.12  2001/11/07 17:51:52  gorban
// Heavily rewritten interrupt and LSR subsystems.
// Many bugs hopefully squashed.
//
// Revision 1.11  2001/10/29 17:00:46  gorban
// fixed parity sending and tx_fifo resets over- and underrun
//
// Revision 1.10  2001/10/20 09:58:40  gorban
// Small synopsis fixes
//
// Revision 1.9  2001/08/24 21:01:12  mohor
// Things connected to parity changed.
// Clock devider changed.
//
// Revision 1.8  2001/08/23 16:05:05  mohor
// Stop bit bug fixed.
// Parity bug fixed.
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
//
// Revision 1.6  2001/06/23 11:21:48  gorban
// DL made 16-bit long. Fixed transmission/reception bugs.
//
// Revision 1.5  2001/06/02 14:28:14  gorban
// Fixed receiver and transmitter. Major bug fixed.
//
// Revision 1.4  2001/05/31 20:08:01  gorban
// FIFO changes and other corrections.
//
// Revision 1.3  2001/05/27 17:37:49  gorban
// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
//
// Revision 1.2  2001/05/21 19:12:02  gorban
// Corrected some Linter messages.
//
// Revision 1.1  2001/05/17 18:34:18  gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0  2001-05-17 21:27:12+02  jacob
// Initial revision
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
//`include "uart_defines.v"
 
module uart_transmitter (clk, wb_rst_i, lcr, tf_push, wb_dat_i, enable, stx_pad_o, tstate, tf_count, tx_reset, lsr_mask);
 
input                                                                           clk;
input                                                                           wb_rst_i;
input [7:0]                                                              lcr;
input                                                                           tf_push;
input [7:0]                                                              wb_dat_i;
input                                                                           enable;
input                                                                           tx_reset;
input                                                                           lsr_mask; //reset of fifo
output                                                                          stx_pad_o;
output [2:0]                                                             tstate;
output [`UART_FIFO_COUNTER_W-1:0]        tf_count;
 
reg [2:0]                                                                        tstate;
reg [4:0]                                                                        counter;
reg [2:0]                                                                        bit_counter;   // counts the bits to be sent
reg [6:0]                                                                        shift_out;      // output shift register
reg                                                                                     stx_o_tmp;
reg                                                                                     parity_xor;  // parity of the word
reg                                                                                     tf_pop;
reg                                                                                     bit_out;
 
// TX FIFO instance
//
// Transmitter FIFO signals
wire [`UART_FIFO_WIDTH-1:0]                      tf_data_in;
wire [`UART_FIFO_WIDTH-1:0]                      tf_data_out;
wire                                                                                    tf_push;
wire                                                                                    tf_overrun;
wire [`UART_FIFO_COUNTER_W-1:0]          tf_count;
 
assign                                                                          tf_data_in = wb_dat_i;
 
uart_tfifo fifo_tx(     // error bit signal is not used in transmitter FIFO
        .clk(           clk             ),
        .wb_rst_i(      wb_rst_i        ),
        .data_in(       tf_data_in      ),
        .data_out(      tf_data_out     ),
        .push(          tf_push         ),
        .pop(           tf_pop          ),
        .overrun(       tf_overrun      ),
        .count(         tf_count        ),
        .fifo_reset(    tx_reset        ),
        .reset_status(lsr_mask)
);
 
// TRANSMITTER FINAL STATE MACHINE
 
parameter s_idle        = 3'd0;
parameter s_send_start  = 3'd1;
parameter s_send_byte   = 3'd2;
parameter s_send_parity = 3'd3;
parameter s_send_stop   = 3'd4;
parameter s_pop_byte    = 3'd5;
 
always @(posedge clk or posedge wb_rst_i)
begin
  if (wb_rst_i)
  begin
        tstate       <= #1 s_idle;
        stx_o_tmp       <= #1 1'b1;
        counter   <= #1 5'b0;
        shift_out   <= #1 7'b0;
        bit_out     <= #1 1'b0;
        parity_xor  <= #1 1'b0;
        tf_pop      <= #1 1'b0;
        bit_counter <= #1 3'b0;
  end
  else
  if (enable)
  begin
        case (tstate)
        s_idle   :      if (~|tf_count) // if tf_count==0
                        begin
                                tstate <= #1 s_idle;
                                stx_o_tmp <= #1 1'b1;
                        end
                        else
                        begin
                                tf_pop <= #1 1'b0;
                                stx_o_tmp  <= #1 1'b1;
                                tstate  <= #1 s_pop_byte;
                        end
        s_pop_byte :    begin
                                tf_pop <= #1 1'b1;
                                case (lcr[/*`UART_LC_BITS*/1:0])  // number of bits in a word
                                2'b00 : begin
                                        bit_counter <= #1 3'b100;
                                        parity_xor  <= #1 ^tf_data_out[4:0];
                                     end
                                2'b01 : begin
                                        bit_counter <= #1 3'b101;
                                        parity_xor  <= #1 ^tf_data_out[5:0];
                                     end
                                2'b10 : begin
                                        bit_counter <= #1 3'b110;
                                        parity_xor  <= #1 ^tf_data_out[6:0];
                                     end
                                2'b11 : begin
                                        bit_counter <= #1 3'b111;
                                        parity_xor  <= #1 ^tf_data_out[7:0];
                                     end
                                endcase
                                {shift_out[6:0], bit_out} <= #1 tf_data_out;
                                tstate <= #1 s_send_start;
                        end
        s_send_start :  begin
                                tf_pop <= #1 1'b0;
                                if (~|counter)
                                        counter <= #1 5'b01111;
                                else
                                if (counter == 5'b00001)
                                begin
                                        counter <= #1 0;
                                        tstate <= #1 s_send_byte;
                                end
                                else
                                        counter <= #1 counter - 1'b1;
                                stx_o_tmp <= #1 1'b0;
                        end
        s_send_byte :   begin
                                if (~|counter)
                                        counter <= #1 5'b01111;
                                else
                                if (counter == 5'b00001)
                                begin
                                        if (bit_counter > 3'b0)
                                        begin
                                                bit_counter <= #1 bit_counter - 1'b1;
                                                {shift_out[5:0],bit_out  } <= #1 {shift_out[6:1], shift_out[0]};
                                                tstate <= #1 s_send_byte;
                                        end
                                        else   // end of byte
                                        if (~lcr[`UART_LC_PE])
                                        begin
                                                tstate <= #1 s_send_stop;
                                        end
                                        else
                                        begin
                                                case ({lcr[`UART_LC_EP],lcr[`UART_LC_SP]})
                                                2'b00:  bit_out <= #1 ~parity_xor;
                                                2'b01:  bit_out <= #1 1'b1;
                                                2'b10:  bit_out <= #1 parity_xor;
                                                2'b11:  bit_out <= #1 1'b0;
                                                endcase
                                                tstate <= #1 s_send_parity;
                                        end
                                        counter <= #1 0;
                                end
                                else
                                        counter <= #1 counter - 1'b1;
                                stx_o_tmp <= #1 bit_out; // set output pin
                        end
        s_send_parity : begin
                                if (~|counter)
                                        counter <= #1 5'b01111;
                                else
                                if (counter == 5'b00001)
                                begin
                                        counter <= #1 4'b0;
                                        tstate <= #1 s_send_stop;
                                end
                                else
                                        counter <= #1 counter - 1'b1;
                                stx_o_tmp <= #1 bit_out;
                        end
        s_send_stop :  begin
                                if (~|counter)
                                  begin
                                                casex ({lcr[`UART_LC_SB],lcr[`UART_LC_BITS]})
                                                3'b0xx:   counter <= #1 5'b01101;     // 1 stop bit ok igor
                                                3'b100:   counter <= #1 5'b10101;     // 1.5 stop bit
                                                default:          counter <= #1 5'b11101;     // 2 stop bits
                                                endcase
                                        end
                                else
                                if (counter == 5'b00001)
                                begin
                                        counter <= #1 0;
                                        tstate <= #1 s_idle;
                                end
                                else
                                        counter <= #1 counter - 1'b1;
                                stx_o_tmp <= #1 1'b1;
                        end
 
                default : // should never get here
                        tstate <= #1 s_idle;
        endcase
  end // end if enable
  else
    tf_pop <= #1 1'b0;  // tf_pop must be 1 cycle width
end // transmitter logic
 
assign stx_pad_o = lcr[`UART_LC_BC] ? 1'b0 : stx_o_tmp;    // Break condition
 
endmodule

Line No.	Rev	Author	Line
1	27	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// uart_transmitter.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the "UART 16550 compatible" project ////`
7			`//// http://www.opencores.org/cores/uart16550/ ////`
8			`//// ////`
9			`//// Documentation related to this project: ////`
10			`//// - http://www.opencores.org/cores/uart16550/ ////`
11			`//// ////`
12			`//// Projects compatibility: ////`
13			`//// - WISHBONE ////`
14			`//// RS232 Protocol ////`
15			`//// 16550D uart (mostly supported) ////`
16			`//// ////`
17			`//// Overview (main Features): ////`
18			`//// UART core transmitter logic ////`
19			`//// ////`
20			`//// Known problems (limits): ////`
21			`//// None known ////`
22			`//// ////`
23			`//// To Do: ////`
24			`//// Thourough testing. ////`
25			`//// ////`
26			`//// Author(s): ////`
27			`//// - gorban@opencores.org ////`
28			`//// - Jacob Gorban ////`
29	29	mohor	`//// - Igor Mohor (igorm@opencores.org) ////`
30	27	mohor	`//// ////`
31			`//// Created: 2001/05/12 ////`
32			`//// Last Updated: 2001/05/17 ////`
33			`//// (See log for the revision history) ////`
34			`//// ////`
35			`//// ////`
36			`//////////////////////////////////////////////////////////////////////`
37			`//// ////`
38	29	mohor	`//// Copyright (C) 2000, 2001 Authors ////`
39	27	mohor	`//// ////`
40			`//// This source file may be used and distributed without ////`
41			`//// restriction provided that this copyright statement is not ////`
42			`//// removed from the file and that any derivative work contains ////`
43			`//// the original copyright notice and the associated disclaimer. ////`
44			`//// ////`
45			`//// This source file is free software; you can redistribute it ////`
46			`//// and/or modify it under the terms of the GNU Lesser General ////`
47			`//// Public License as published by the Free Software Foundation; ////`
48			`//// either version 2.1 of the License, or (at your option) any ////`
49			`//// later version. ////`
50			`//// ////`
51			`//// This source is distributed in the hope that it will be ////`
52			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
53			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
54			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
55			`//// details. ////`
56			`//// ////`
57			`//// You should have received a copy of the GNU Lesser General ////`
58			`//// Public License along with this source; if not, download it ////`
59			`//// from http://www.opencores.org/lgpl.shtml ////`
60			`//// ////`
61			`//////////////////////////////////////////////////////////////////////`
62			`//`
63			`// CVS Revision History`
64			`//`
65			`// $Log: not supported by cvs2svn $`
66	74	gorban	`// Revision 1.16 2002/01/08 11:29:40 mohor`
67			`// tf_pop was too wide. Now it is only 1 clk cycle width.`
68			`//`
69	70	mohor	`// Revision 1.15 2001/12/17 14:46:48 mohor`
70			`// overrun signal was moved to separate block because many sequential lsr`
71			`// reads were preventing data from being written to rx fifo.`
72			`// underrun signal was not used and was removed from the project.`
73			`//`
74	61	mohor	`// Revision 1.14 2001/12/03 21:44:29 gorban`
75			`// Updated specification documentation.`
76			`// Added full 32-bit data bus interface, now as default.`
77			`// Address is 5-bit wide in 32-bit data bus mode.`
78			`// Added wb_sel_i input to the core. It's used in the 32-bit mode.`
79			`// Added debug interface with two 32-bit read-only registers in 32-bit mode.`
80			`// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.`
81			`// My small test bench is modified to work with 32-bit mode.`
82			`//`
83	48	gorban	`// Revision 1.13 2001/11/08 14:54:23 mohor`
84			`// Comments in Slovene language deleted, few small fixes for better work of`
85			`// old tools. IRQs need to be fix.`
86			`//`
87	39	mohor	`// Revision 1.12 2001/11/07 17:51:52 gorban`
88			`// Heavily rewritten interrupt and LSR subsystems.`
89			`// Many bugs hopefully squashed.`
90			`//`
91	37	gorban	`// Revision 1.11 2001/10/29 17:00:46 gorban`
92			`// fixed parity sending and tx_fifo resets over- and underrun`
93			`//`
94	34	gorban	`// Revision 1.10 2001/10/20 09:58:40 gorban`
95			`// Small synopsis fixes`
96			`//`
97	33	gorban	`// Revision 1.9 2001/08/24 21:01:12 mohor`
98			`// Things connected to parity changed.`
99			`// Clock devider changed.`
100			`//`
101	29	mohor	`// Revision 1.8 2001/08/23 16:05:05 mohor`
102			`// Stop bit bug fixed.`
103			`// Parity bug fixed.`
104			`// WISHBONE read cycle bug fixed,`
105			`// OE indicator (Overrun Error) bug fixed.`
106			`// PE indicator (Parity Error) bug fixed.`
107			`// Register read bug fixed.`
108			`//`
109	27	mohor	`// Revision 1.6 2001/06/23 11:21:48 gorban`
110			`// DL made 16-bit long. Fixed transmission/reception bugs.`
111			`//`
112			`// Revision 1.5 2001/06/02 14:28:14 gorban`
113			`// Fixed receiver and transmitter. Major bug fixed.`
114			`//`
115			`// Revision 1.4 2001/05/31 20:08:01 gorban`
116			`// FIFO changes and other corrections.`
117			`//`
118			`// Revision 1.3 2001/05/27 17:37:49 gorban`
119			`// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.`
120			`//`
121			`// Revision 1.2 2001/05/21 19:12:02 gorban`
122			`// Corrected some Linter messages.`
123			`//`
124			`// Revision 1.1 2001/05/17 18:34:18 gorban`
125			`// First 'stable' release. Should be sythesizable now. Also added new header.`
126			`//`
127			`// Revision 1.0 2001-05-17 21:27:12+02 jacob`
128			`// Initial revision`
129			`//`
130			`//`
131
132	33	gorban	`// synopsys translate_off`
133	27	mohor	`include "timescale.v"
134	33	gorban	`// synopsys translate_on`
135
136	79	gorban	//`include "uart_defines.v"
137	27	mohor
138	48	gorban	`module uart_transmitter (clk, wb_rst_i, lcr, tf_push, wb_dat_i, enable, stx_pad_o, tstate, tf_count, tx_reset, lsr_mask);`
139	27	mohor
140	34	gorban	`input clk;`
141			`input wb_rst_i;`
142			`input [7:0] lcr;`
143			`input tf_push;`
144			`input [7:0] wb_dat_i;`
145			`input enable;`
146			`input tx_reset;`
147	37	gorban	`input lsr_mask; //reset of fifo`
148	34	gorban	`output stx_pad_o;`
149	48	gorban	`output [2:0] tstate;`
150	34	gorban	output [`UART_FIFO_COUNTER_W-1:0] tf_count;
151	27	mohor
152	48	gorban	`reg [2:0] tstate;`
153	34	gorban	`reg [4:0] counter;`
154			`reg [2:0] bit_counter; // counts the bits to be sent`
155			`reg [6:0] shift_out; // output shift register`
156			`reg stx_o_tmp;`
157			`reg parity_xor; // parity of the word`
158			`reg tf_pop;`
159			`reg bit_out;`
160	27	mohor
161			`// TX FIFO instance`
162			`//`
163			`// Transmitter FIFO signals`
164	34	gorban	wire [`UART_FIFO_WIDTH-1:0] tf_data_in;
165			wire [`UART_FIFO_WIDTH-1:0] tf_data_out;
166			`wire tf_push;`
167	79	gorban	`wire tf_overrun;`
168	34	gorban	wire [`UART_FIFO_COUNTER_W-1:0] tf_count;
169	27	mohor
170	34	gorban	`assign tf_data_in = wb_dat_i;`
171	27	mohor
172	79	gorban	`uart_tfifo fifo_tx( // error bit signal is not used in transmitter FIFO`
173	27	mohor	`.clk( clk ),`
174			`.wb_rst_i( wb_rst_i ),`
175			`.data_in( tf_data_in ),`
176			`.data_out( tf_data_out ),`
177			`.push( tf_push ),`
178			`.pop( tf_pop ),`
179	79	gorban	`.overrun( tf_overrun ),`
180	27	mohor	`.count( tf_count ),`
181			`.fifo_reset( tx_reset ),`
182	37	gorban	`.reset_status(lsr_mask)`
183	27	mohor	`);`
184
185			`// TRANSMITTER FINAL STATE MACHINE`
186
187			`parameter s_idle = 3'd0;`
188			`parameter s_send_start = 3'd1;`
189			`parameter s_send_byte = 3'd2;`
190			`parameter s_send_parity = 3'd3;`
191			`parameter s_send_stop = 3'd4;`
192			`parameter s_pop_byte = 3'd5;`
193
194			`always @(posedge clk or posedge wb_rst_i)`
195			`begin`
196			`if (wb_rst_i)`
197			`begin`
198	48	gorban	`tstate <= #1 s_idle;`
199	27	mohor	`stx_o_tmp <= #1 1'b1;`
200			`counter <= #1 5'b0;`
201			`shift_out <= #1 7'b0;`
202			`bit_out <= #1 1'b0;`
203			`parity_xor <= #1 1'b0;`
204			`tf_pop <= #1 1'b0;`
205			`bit_counter <= #1 3'b0;`
206			`end`
207			`else`
208			`if (enable)`
209			`begin`
210	48	gorban	`case (tstate)`
211	27	mohor	`s_idle : if (~\|tf_count) // if tf_count==0`
212			`begin`
213	48	gorban	`tstate <= #1 s_idle;`
214	27	mohor	`stx_o_tmp <= #1 1'b1;`
215			`end`
216			`else`
217			`begin`
218			`tf_pop <= #1 1'b0;`
219			`stx_o_tmp <= #1 1'b1;`
220	48	gorban	`tstate <= #1 s_pop_byte;`
221	27	mohor	`end`
222			`s_pop_byte : begin`
223			`tf_pop <= #1 1'b1;`
224			case (lcr[/`UART_LC_BITS/1:0]) // number of bits in a word
225			`2'b00 : begin`
226			`bit_counter <= #1 3'b100;`
227			`parity_xor <= #1 ^tf_data_out[4:0];`
228			`end`
229			`2'b01 : begin`
230			`bit_counter <= #1 3'b101;`
231			`parity_xor <= #1 ^tf_data_out[5:0];`
232			`end`
233			`2'b10 : begin`
234			`bit_counter <= #1 3'b110;`
235			`parity_xor <= #1 ^tf_data_out[6:0];`
236			`end`
237			`2'b11 : begin`
238			`bit_counter <= #1 3'b111;`
239			`parity_xor <= #1 ^tf_data_out[7:0];`
240			`end`
241			`endcase`
242			`{shift_out[6:0], bit_out} <= #1 tf_data_out;`
243	48	gorban	`tstate <= #1 s_send_start;`
244	27	mohor	`end`
245			`s_send_start : begin`
246			`tf_pop <= #1 1'b0;`
247			`if (~\|counter)`
248			`counter <= #1 5'b01111;`
249			`else`
250			`if (counter == 5'b00001)`
251			`begin`
252			`counter <= #1 0;`
253	48	gorban	`tstate <= #1 s_send_byte;`
254	27	mohor	`end`
255			`else`
256	39	mohor	`counter <= #1 counter - 1'b1;`
257	27	mohor	`stx_o_tmp <= #1 1'b0;`
258			`end`
259			`s_send_byte : begin`
260			`if (~\|counter)`
261			`counter <= #1 5'b01111;`
262			`else`
263			`if (counter == 5'b00001)`
264			`begin`
265			`if (bit_counter > 3'b0)`
266			`begin`
267	39	mohor	`bit_counter <= #1 bit_counter - 1'b1;`
268	27	mohor	`{shift_out[5:0],bit_out } <= #1 {shift_out[6:1], shift_out[0]};`
269	48	gorban	`tstate <= #1 s_send_byte;`
270	27	mohor	`end`
271			`else // end of byte`
272			if (~lcr[`UART_LC_PE])
273			`begin`
274	48	gorban	`tstate <= #1 s_send_stop;`
275	27	mohor	`end`
276			`else`
277			`begin`
278			case ({lcr[`UART_LC_EP],lcr[`UART_LC_SP]})
279	34	gorban	`2'b00: bit_out <= #1 ~parity_xor;`
280	27	mohor	`2'b01: bit_out <= #1 1'b1;`
281	34	gorban	`2'b10: bit_out <= #1 parity_xor;`
282	27	mohor	`2'b11: bit_out <= #1 1'b0;`
283			`endcase`
284	48	gorban	`tstate <= #1 s_send_parity;`
285	27	mohor	`end`
286			`counter <= #1 0;`
287			`end`
288			`else`
289	39	mohor	`counter <= #1 counter - 1'b1;`
290	27	mohor	`stx_o_tmp <= #1 bit_out; // set output pin`
291			`end`
292			`s_send_parity : begin`
293			`if (~\|counter)`
294			`counter <= #1 5'b01111;`
295			`else`
296			`if (counter == 5'b00001)`
297			`begin`
298			`counter <= #1 4'b0;`
299	48	gorban	`tstate <= #1 s_send_stop;`
300	27	mohor	`end`
301			`else`
302	39	mohor	`counter <= #1 counter - 1'b1;`
303	27	mohor	`stx_o_tmp <= #1 bit_out;`
304			`end`
305			`s_send_stop : begin`
306			`if (~\|counter)`
307			`begin`
308			casex ({lcr[`UART_LC_SB],lcr[`UART_LC_BITS]})
309			`3'b0xx: counter <= #1 5'b01101; // 1 stop bit ok igor`
310			`3'b100: counter <= #1 5'b10101; // 1.5 stop bit`
311	48	gorban	`default: counter <= #1 5'b11101; // 2 stop bits`
312	27	mohor	`endcase`
313			`end`
314			`else`
315			`if (counter == 5'b00001)`
316			`begin`
317			`counter <= #1 0;`
318	48	gorban	`tstate <= #1 s_idle;`
319	27	mohor	`end`
320			`else`
321	39	mohor	`counter <= #1 counter - 1'b1;`
322	27	mohor	`stx_o_tmp <= #1 1'b1;`
323			`end`
324
325			`default : // should never get here`
326	48	gorban	`tstate <= #1 s_idle;`
327	27	mohor	`endcase`
328			`end // end if enable`
329	70	mohor	`else`
330			`tf_pop <= #1 1'b0; // tf_pop must be 1 cycle width`
331	27	mohor	`end // transmitter logic`
332
333			assign stx_pad_o = lcr[`UART_LC_BC] ? 1'b0 : stx_o_tmp; // Break condition
334
335			`endmodule`

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