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mohor |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// uart_TX_FIFO.v ////
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//// ////
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//// ////
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//// This file is part of the "UART 16550 compatible" project ////
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//// http://www.opencores.org/cores/uart16550/ ////
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//// ////
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//// Documentation related to this project: ////
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//// - http://www.opencores.org/cores/uart16550/ ////
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//// ////
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//// Projects compatibility: ////
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//// - WISHBONE ////
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//// RS232 Protocol ////
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//// 16550D uart (mostly supported) ////
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//// ////
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//// Overview (main Features): ////
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//// UART core WISHBONE interface. ////
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//// ////
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//// Known problems (limits): ////
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//// Inserts one wait state on all transfers. ////
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//// Note affected signals and the way they are affected. ////
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//// ////
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//// To Do: ////
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//// Nothing. ////
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//// ////
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//// Author(s): ////
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//// - gorban@opencores.org ////
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//// - Jacob Gorban ////
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mohor |
//// - Igor Mohor (igorm@opencores.org) ////
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mohor |
//// ////
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//// Created: 2001/05/12 ////
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//// Last Updated: 2001/05/17 ////
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//// (See log for the revision history) ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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mohor |
//// Copyright (C) 2000, 2001 Authors ////
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mohor |
//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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mohor |
// Revision 1.7 2001/08/23 16:05:05 mohor
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// Stop bit bug fixed.
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// Parity bug fixed.
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// WISHBONE read cycle bug fixed,
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// OE indicator (Overrun Error) bug fixed.
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// PE indicator (Parity Error) bug fixed.
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// Register read bug fixed.
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//
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mohor |
// Revision 1.4 2001/05/31 20:08:01 gorban
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// FIFO changes and other corrections.
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//
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// Revision 1.3 2001/05/21 19:12:01 gorban
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// Corrected some Linter messages.
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//
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// Revision 1.2 2001/05/17 18:34:18 gorban
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// First 'stable' release. Should be sythesizable now. Also added new header.
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//
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// Revision 1.0 2001-05-17 21:27:13+02 jacob
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// Initial revision
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//
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//
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// UART core WISHBONE interface
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//
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// Author: Jacob Gorban (jacob.gorban@flextronicssemi.com)
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// Company: Flextronics Semiconductor
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//
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`include "timescale.v"
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module uart_wb (clk,
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wb_rst_i,
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wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o,
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we_o, re_o // Write and read enable output for the core
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);
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input clk;
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// WISHBONE interface
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input wb_rst_i;
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input wb_we_i;
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input wb_stb_i;
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input wb_cyc_i;
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output wb_ack_o;
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output we_o;
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output re_o;
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wire we_o;
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reg wb_ack_o;
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always @(posedge clk or posedge wb_rst_i)
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begin
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if (wb_rst_i)
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begin
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wb_ack_o <= #1 1'b0;
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end
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else
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begin
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// wb_ack_o <= #1 wb_stb_i & wb_cyc_i; // 1 clock wait state on all transfers
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wb_ack_o <= #1 wb_stb_i & wb_cyc_i & ~wb_ack_o; // 1 clock wait state on all transfers
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end
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end
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assign we_o = wb_we_i & wb_cyc_i & wb_stb_i; //WE for registers
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assign re_o = ~wb_we_i & wb_cyc_i & wb_stb_i; //RE for registers
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endmodule
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