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[/] [uart16550/] [trunk/] [rtl/] [verilog/] [uart_wb.v] - Blame information for rev 33

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  uart_wb.v                                                   ////
////                                                              ////
////                                                              ////
////  This file is part of the "UART 16550 compatible" project    ////
////  http://www.opencores.org/cores/uart16550/                   ////
////                                                              ////
////  Documentation related to this project:                      ////
////  - http://www.opencores.org/cores/uart16550/                 ////
////                                                              ////
////  Projects compatibility:                                     ////
////  - WISHBONE                                                  ////
////  RS232 Protocol                                              ////
////  16550D uart (mostly supported)                              ////
////                                                              ////
////  Overview (main Features):                                   ////
////  UART core WISHBONE interface.                               ////
////                                                              ////
////  Known problems (limits):                                    ////
////  Inserts one wait state on all transfers.                    ////
////  Note affected signals and the way they are affected.        ////
////                                                              ////
////  To Do:                                                      ////
////  Nothing.                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - gorban@opencores.org                                  ////
////      - Jacob Gorban                                          ////
////      - Igor Mohor (igorm@opencores.org)                      ////
////                                                              ////
////  Created:        2001/05/12                                  ////
////  Last Updated:   2001/05/17                                  ////
////                  (See log for the revision history)          ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000, 2001 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.8  2001/08/24 21:01:12  mohor
// Things connected to parity changed.
// Clock devider changed.
//
// Revision 1.7  2001/08/23 16:05:05  mohor
// Stop bit bug fixed.
// Parity bug fixed.
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
//
// Revision 1.4  2001/05/31 20:08:01  gorban
// FIFO changes and other corrections.
//
// Revision 1.3  2001/05/21 19:12:01  gorban
// Corrected some Linter messages.
//
// Revision 1.2  2001/05/17 18:34:18  gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0  2001-05-17 21:27:13+02  jacob
// Initial revision
//
//
 
// UART core WISHBONE interface 
//
// Author: Jacob Gorban   (jacob.gorban@flextronicssemi.com)
// Company: Flextronics Semiconductor
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
module uart_wb (clk,
        wb_rst_i,
        wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o,
        we_o, re_o // Write and read enable output for the core
 
        );
 
input                           clk;
 
// WISHBONE interface   
input                           wb_rst_i;
input                           wb_we_i;
input                           wb_stb_i;
input                           wb_cyc_i;
output                          wb_ack_o;
output                          we_o;
output                          re_o;
 
wire                            we_o;
reg                             wb_ack_o;
 
always @(posedge clk or posedge wb_rst_i)
begin
        if (wb_rst_i)
        begin
                wb_ack_o <= #1 1'b0;
        end
        else
        begin
//              wb_ack_o <= #1 wb_stb_i & wb_cyc_i; // 1 clock wait state on all transfers
                wb_ack_o <= #1 wb_stb_i & wb_cyc_i & ~wb_ack_o; // 1 clock wait state on all transfers
        end
end
 
assign we_o =  wb_we_i & wb_cyc_i & wb_stb_i; //WE for registers        
assign re_o = ~wb_we_i & wb_cyc_i & wb_stb_i; //RE for registers        
 
endmodule

Line No.	Rev	Author	Line
1	27	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3	33	gorban	`//// uart_wb.v ////`
4	27	mohor	`//// ////`
5			`//// ////`
6			`//// This file is part of the "UART 16550 compatible" project ////`
7			`//// http://www.opencores.org/cores/uart16550/ ////`
8			`//// ////`
9			`//// Documentation related to this project: ////`
10			`//// - http://www.opencores.org/cores/uart16550/ ////`
11			`//// ////`
12			`//// Projects compatibility: ////`
13			`//// - WISHBONE ////`
14			`//// RS232 Protocol ////`
15			`//// 16550D uart (mostly supported) ////`
16			`//// ////`
17			`//// Overview (main Features): ////`
18			`//// UART core WISHBONE interface. ////`
19			`//// ////`
20			`//// Known problems (limits): ////`
21			`//// Inserts one wait state on all transfers. ////`
22			`//// Note affected signals and the way they are affected. ////`
23			`//// ////`
24			`//// To Do: ////`
25			`//// Nothing. ////`
26			`//// ////`
27			`//// Author(s): ////`
28			`//// - gorban@opencores.org ////`
29			`//// - Jacob Gorban ////`
30	29	mohor	`//// - Igor Mohor (igorm@opencores.org) ////`
31	27	mohor	`//// ////`
32			`//// Created: 2001/05/12 ////`
33			`//// Last Updated: 2001/05/17 ////`
34			`//// (See log for the revision history) ////`
35			`//// ////`
36			`//// ////`
37			`//////////////////////////////////////////////////////////////////////`
38			`//// ////`
39	29	mohor	`//// Copyright (C) 2000, 2001 Authors ////`
40	27	mohor	`//// ////`
41			`//// This source file may be used and distributed without ////`
42			`//// restriction provided that this copyright statement is not ////`
43			`//// removed from the file and that any derivative work contains ////`
44			`//// the original copyright notice and the associated disclaimer. ////`
45			`//// ////`
46			`//// This source file is free software; you can redistribute it ////`
47			`//// and/or modify it under the terms of the GNU Lesser General ////`
48			`//// Public License as published by the Free Software Foundation; ////`
49			`//// either version 2.1 of the License, or (at your option) any ////`
50			`//// later version. ////`
51			`//// ////`
52			`//// This source is distributed in the hope that it will be ////`
53			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
54			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
55			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
56			`//// details. ////`
57			`//// ////`
58			`//// You should have received a copy of the GNU Lesser General ////`
59			`//// Public License along with this source; if not, download it ////`
60			`//// from http://www.opencores.org/lgpl.shtml ////`
61			`//// ////`
62			`//////////////////////////////////////////////////////////////////////`
63			`//`
64			`// CVS Revision History`
65			`//`
66			`// $Log: not supported by cvs2svn $`
67	33	gorban	`// Revision 1.8 2001/08/24 21:01:12 mohor`
68			`// Things connected to parity changed.`
69			`// Clock devider changed.`
70			`//`
71	29	mohor	`// Revision 1.7 2001/08/23 16:05:05 mohor`
72			`// Stop bit bug fixed.`
73			`// Parity bug fixed.`
74			`// WISHBONE read cycle bug fixed,`
75			`// OE indicator (Overrun Error) bug fixed.`
76			`// PE indicator (Parity Error) bug fixed.`
77			`// Register read bug fixed.`
78			`//`
79	27	mohor	`// Revision 1.4 2001/05/31 20:08:01 gorban`
80			`// FIFO changes and other corrections.`
81			`//`
82			`// Revision 1.3 2001/05/21 19:12:01 gorban`
83			`// Corrected some Linter messages.`
84			`//`
85			`// Revision 1.2 2001/05/17 18:34:18 gorban`
86			`// First 'stable' release. Should be sythesizable now. Also added new header.`
87			`//`
88			`// Revision 1.0 2001-05-17 21:27:13+02 jacob`
89			`// Initial revision`
90			`//`
91			`//`
92
93			`// UART core WISHBONE interface`
94			`//`
95			`// Author: Jacob Gorban (jacob.gorban@flextronicssemi.com)`
96			`// Company: Flextronics Semiconductor`
97			`//`
98
99	33	gorban	`// synopsys translate_off`
100	27	mohor	`include "timescale.v"
101	33	gorban	`// synopsys translate_on`
102	27	mohor
103			`module uart_wb (clk,`
104			`wb_rst_i,`
105			`wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o,`
106			`we_o, re_o // Write and read enable output for the core`
107
108			`);`
109
110			`input clk;`
111
112			`// WISHBONE interface`
113			`input wb_rst_i;`
114			`input wb_we_i;`
115			`input wb_stb_i;`
116			`input wb_cyc_i;`
117			`output wb_ack_o;`
118			`output we_o;`
119			`output re_o;`
120
121			`wire we_o;`
122			`reg wb_ack_o;`
123
124			`always @(posedge clk or posedge wb_rst_i)`
125			`begin`
126			`if (wb_rst_i)`
127			`begin`
128			`wb_ack_o <= #1 1'b0;`
129			`end`
130			`else`
131			`begin`
132			`// wb_ack_o <= #1 wb_stb_i & wb_cyc_i; // 1 clock wait state on all transfers`
133			`wb_ack_o <= #1 wb_stb_i & wb_cyc_i & ~wb_ack_o; // 1 clock wait state on all transfers`
134			`end`
135			`end`
136
137			`assign we_o = wb_we_i & wb_cyc_i & wb_stb_i; //WE for registers`
138			`assign re_o = ~wb_we_i & wb_cyc_i & wb_stb_i; //RE for registers`
139
140			`endmodule`

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[/] [uart16550/] [trunk/] [rtl/] [verilog/] [uart_wb.v] - Blame information for rev 33