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[/] [uart2spi/] [trunk/] [verif/] [models/] [st_m25p16/] [internal_logic.v] - Blame information for rev 3

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1 3 dinesha 
// Author: Hugues CREUSY modified by Xue feng
2 
// June 2004
3 
// Verilog model
4 
// project: M25P16 50 MHz,
5 
// release: 1.2
6 
 
7 
 
8 
 
9 
// These Verilog HDL models are provided "as is" without warranty
10 
// of any kind, included but not limited to, implied warranty
11 
// of merchantability and fitness for a particular purpose.
12 
 
13 
 
14 
 
15 
 
16 
 
17 
`timescale 1ns/1ns
18 
`include "parameter.v"
19 
 
20 
module internal_logic (c, d, w, s, hold, data_to_read, q, data_to_write, page_add_index, add_mem, write_op, read_op, be_enable, se_enable, add_pp_enable, pp_enable, read_enable, data_request, srwd_wrsr,write_protect, wrsr);
21 
   ////////////////////////////////
22 
   // declaration of the parameters
23 
   ////////////////////////////////
24 
   input c;
25 
   input d;
26 
   input w;
27 
   input s;
28 
   input hold;
29 
   input[(`NB_BIT_DATA - 1):0] data_to_read;
30 
 
31 
   output q;
32 
   reg q;
33 
 
34 
   output[(`NB_BIT_DATA - 1):0] data_to_write;
35 
   reg[(`NB_BIT_DATA - 1):0] data_to_write;
36 
 
37 
   output[(`LSB_TO_CODE_PAGE - 1):0] page_add_index;    // position to write data_to_write inside the page
38 
   reg[(`LSB_TO_CODE_PAGE - 1):0] page_add_index;
39 
 
40 
   output[(`NB_BIT_ADD_MEM - 1):0] add_mem;
41 
   reg[(`NB_BIT_ADD_MEM - 1):0] add_mem;
42 
 
43 
   output write_op;
44 
   reg write_op;
45 
 
46 
   output read_op;
47 
   reg read_op;
48 
 
49 
   output be_enable;
50 
   reg be_enable;
51 
 
52 
   output se_enable;
53 
   reg se_enable;
54 
 
55 
   output add_pp_enable;
56 
   reg add_pp_enable;
57 
 
58 
   output pp_enable;
59 
   reg pp_enable;
60 
 
61 
   output read_enable;
62 
   reg read_enable;
63 
 
64 
   output data_request;
65 
   reg data_request;
66 
 
67 
   output srwd_wrsr;
68 
   reg srwd_wrsr;
69 
 
70 
   output write_protect;
71 
   reg write_protect;
72 
 
73 
   output wrsr;
74 
   reg wrsr;
75 
 
76 
 
77 
   ///////////////////////////////////////////////
78 
   // declaration of internal variables
79 
   ///////////////////////////////////////////////
80 
   reg only_rdsr;
81 
   reg only_res;
82 
   //reg write_protect;
83 
   reg write_protect_toggle;
84 
   reg select_ok;
85 
   reg raz;
86 
   reg byte_ok;
87 
   reg wren;
88 
   reg wrdi;
89 
   reg rdsr;
90 
  // reg wrsr;
91 
   reg read_data;
92 
   reg fast_read;
93 
   reg pp;
94 
   reg se;
95 
   reg be;
96 
   reg dp;
97 
   reg res;
98 
   reg rdid;
99 
   reg q_bis;
100 
   reg protect;
101 
   reg wr_cycle;
102 
   reg hold_cond;
103 
   reg inhib_wren;
104 
   reg inhib_wrdi;
105 
   reg inhib_rdsr;
106 
   reg inhib_wrsr;
107 
   reg inhib_read;
108 
   reg inhib_pp;
109 
   reg inhib_se;
110 
   reg inhib_be;
111 
   reg inhib_dp;
112 
   reg inhib_res;
113 
   reg inhib_rdid;
114 
   reg reset_wel;
115 
   reg wel;
116 
   reg wip;
117 
   reg c_int;
118 
   reg[4:0] bit_id;     //modified by xue-feng hu
119 
   reg [23:0]  id;      //modified by xue-feng hu
120 
 
121 
   reg [2:0]   cpt;
122 
   reg [2:0]   bit_index;       // to allow shift inside a byte
123 
   reg [2:0]   bit_res;         // to allow shift inside signature
124 
   reg [2:0]   bit_register;    // to allow shift inside status register
125 
   reg [2:0]   k;       // to allow shift inside a byte
126 
 
127 
   reg [7:0]   data;
128 
   reg [7:0]   adress_1;
129 
   reg [7:0]   adress_2;
130 
   reg [7:0]   adress_3;
131 
   reg [7:0]   sr_mask;
132 
   reg [7:0]   signature;
133 
   reg [7:0]   manufacturerID;
134 
   reg [7:0]   memtype;
135 
   reg [7:0]   density;
136 
 
137 
 
138 
   reg [(`NB_BIT_DATA-1):0]   wr_latch;
139 
   reg [(`NB_BIT_DATA-1):0]   page_ini;
140 
   reg [(`NB_BIT_DATA-1):0]   data_latch;
141 
   reg [(`NB_BIT_DATA-1):0]   register_bis;
142 
   reg [(`NB_BIT_DATA-1):0]   register_temp;
143 
   reg [(`NB_BIT_DATA-1):0]   status_register;
144 
 
145 
   reg [(`NB_BPI-1):0]              bp;
146 
   reg [(`NB_BIT_ADD_MEM-1):0]      adress;
147 
   reg [(`BIT_TO_CODE_MEM-1):0]     cut_add;
148 
   reg [(`LSB_TO_CODE_PAGE -1) :0]  lsb_adress;
149 
 
150 
   integer     byte_cpt;
151 
   integer     int_add;
152 
   integer     i,j;
153 
   integer     count_enable;
154 
 
155 
   time        t_only_res ;
156 
   time        t_write_protect_toggle;
157 
 
158 
   initial
159 
   begin
160 
      ////////////////////////////////////////////
161 
      // Initialization of the internal variables
162 
      ////////////////////////////////////////////
163 
      only_rdsr      = `FALSE;
164 
      only_res       = `FALSE;
165 
      write_protect  = `FALSE;
166 
      select_ok      = `FALSE;
167 
      raz            = `FALSE;
168 
      byte_ok        = `FALSE;
169 
 
170 
      cpt         = 0;
171 
      byte_cpt    = 0;
172 
 
173 
      data_to_write  = 8'bxxxxxxxx;
174 
      data_latch     = 8'bxxxxxxxx;
175 
      data_request <= `FALSE;
176 
 
177 
      wren        = `FALSE;
178 
      wrdi        = `FALSE;
179 
      rdsr        = `FALSE;
180 
      wrsr        = `FALSE;
181 
      read_data   = `FALSE;
182 
      fast_read   = `FALSE;
183 
      pp          = `FALSE;
184 
      se          = `FALSE;
185 
      be          = `FALSE;
186 
      dp          = `FALSE;
187 
      res         = `FALSE;
188 
      rdid        = `FALSE;
189 
 
190 
      q_bis          = 1'bz;
191 
 
192 
      register_bis   = 8'b00000000;
193 
      wr_latch       = 8'b00000000;
194 
 
195 
      protect     = `FALSE;
196 
      wr_cycle    = `FALSE;
197 
      hold_cond   = `FALSE;
198 
      write_op    = `FALSE;
199 
      read_op     = `FALSE;
200 
 
201 
      inhib_wren  = `FALSE;
202 
      inhib_wrdi  = `FALSE;
203 
      inhib_rdsr  = `FALSE;
204 
      inhib_wrsr  = `FALSE;
205 
      inhib_read  = `FALSE;
206 
      inhib_pp    = `FALSE;
207 
      inhib_se    = `FALSE;
208 
      inhib_be    = `FALSE;
209 
      inhib_dp    = `FALSE;
210 
      inhib_res   = `FALSE;
211 
      inhib_rdid  = `FALSE;
212 
 
213 
      add_pp_enable  = `FALSE;
214 
      read_enable    = `FALSE;
215 
      pp_enable      = `FALSE;
216 
      be_enable      = `FALSE;
217 
      se_enable      = `FALSE;
218 
 
219 
 
220 
      count_enable   = `FALSE;
221 
      data           = 8'b00000000;
222 
 
223 
      // decode process
224 
      bit_index      = 8'b00000000;
225 
      bit_res        = 8'b00000000;
226 
      bit_register   = 8'b00000000;
227 
      k   = 8'b00000000;
228 
 
229 
 
230 
      bp          = `NB_BPI'h0 ;
231 
 
232 
      int_add     = 0;
233 
      sr_mask     = 8'b10000000;
234 
      page_ini    = 8'b11111111;
235 
 
236 
      reset_wel   = 1'b0;
237 
      wel         = 1'b0;
238 
      wip         = 1'b0;
239 
 
240 
      signature   = `SIGNATURE ;
241 
      manufacturerID = `manufacturerID;
242 
      memtype = `memtype;
243 
      density = `density;
244 
      /////////////////////////////////////////////////////////
245 
      id = {manufacturerID,memtype,density};    //modified by xue-feng hu
246 
      bit_id = 5'b00000;                        //modified by xue-feng hu
247 
      //////////////////////////////////////////////////////////
248 
   end // initial
249 
 
250 
   always @(register_bis) status_register = register_bis ;
251 
   //assign status_register = register_bis ; // Continuous Assignment
252 
 
253 
   //-----------------------------------------------------------
254 
   // This process generates the Hold condition when it is valid
255 
   always
256 
   begin : hold_com
257 
      @(hold);
258 
      begin
259 
      if ((hold == 1'b0) && (s == 1'b0))
260 
      begin
261 
         if (c == 1'b0)
262 
         begin
263 
            hold_cond <= `TRUE;
264 
            if ($time != 0) $display("%t:  NOTE: COMMUNICATION PAUSED",$realtime);
265 
         end
266 
         else
267 
         begin
268 
            @(c or hold);
269 
            if (c == 1'b0)
270 
            begin
271 
               hold_cond <= `TRUE;
272 
               if ($time != 0) $display("%t:  NOTE: COMMUNICATION PAUSED",$realtime);
273 
            end
274 
         end
275 
      end
276 
      else if (hold == 1'b1)
277 
      begin
278 
         if (c == 1'b0)
279 
         begin
280 
            hold_cond <= `FALSE;
281 
            if ($time != 0) $display("%t:  NOTE: COMMUNICATION (RE)STARTED",$realtime);
282 
         end
283 
         else
284 
         begin
285 
            @(c or hold);
286 
            if (c == 1'b0)
287 
            begin
288 
               hold_cond <= `FALSE;
289 
               if ($time != 0) $display("%t:  NOTE: COMMUNICATION (RE)STARTED",$realtime);
290 
            end
291 
         end
292 
      end
293 
      end
294 
   end
295 
 
296 
   //----------------------------------------------------------------------
297 
   // This process inhibits the internal clock when hold condition is valid
298 
   always
299 
   begin : horloge
300 
      @(c);
301 
      begin
302 
      if (!hold_cond)
303 
      begin
304 
         c_int <= c ;
305 
      end
306 
      else
307 
      begin
308 
         c_int <= 1'b0 ;
309 
      end
310 
      end
311 
   end
312 
 
313 
   //---------------------------------------------------------------
314 
   // This process inhibits data output when hold condition is valid
315 
   always @(posedge hold_cond ) q <= #`THLQZ 1'bz ;
316 
 
317 
   always @(negedge hold_cond) q <= #`THHQX q_bis ;
318 
 
319 
   always @ (q_bis or s)
320 
      if (!hold_cond)
321 
      begin
322 
         q <= q_bis ;
323 
      end
324 
 
325 
   //----------------------------------------------------------
326 
   // This process increments 2 counters:  one bit counter (cpt)
327 
   // one byte counter (byte_cpt)
328 
   always
329 
   begin : count_bit_raz
330 
         @(raz);
331 
         begin
332 
            if (raz || !select_ok)
333 
            begin
334 
               cpt <= 0 ;
335 
               byte_cpt <= 0 ;
336 
               count_enable = `FALSE;
337 
            end
338 
         end
339 
   end
340 
 
341 
   always
342 
   begin : count_bit_enable
343 
      @(posedge c_int or negedge raz);
344 
      begin
345 
            if (!raz && select_ok)
346 
            begin
347 
               // count enable is an intermediate variable which allows cpt to be
348 
               // constant during a whole period
349 
               count_enable = `TRUE;
350 
            end
351 
      end
352 
   end
353 
 
354 
 
355 
   always
356 
   begin : count_bit
357 
      @(negedge c_int);
358 
      begin
359 
         if (!raz && select_ok)
360 
         begin
361 
            if (count_enable)
362 
            begin
363 
               cpt <= cpt + 1 ;
364 
            end
365 
         end
366 
      end
367 
   end
368 
 
369 
   always @(negedge c_int)
370 
      if (byte_ok)
371 
      begin
372 
         //byte_cpt = (byte_cpt + 1) ;
373 
         byte_cpt <= (byte_cpt + 1) ;
374 
      end
375 
 
376 
   //---------------------------------------------------------------------
377 
   // This process latches every byte of data received and returns byte_ok
378 
   always
379 
   begin : data_in_reset
380 
 
381 
      @(c_int or select_ok);
382 
      begin
383 
         if (!select_ok)
384 
         begin
385 
            raz <= `TRUE ;
386 
            byte_ok <= `FALSE ;
387 
            data_latch <= 8'b00000000 ;
388 
            data = 8'b00000000;
389 
         end
390 
      end
391 
   end
392 
 
393 
   always
394 
   begin : data_in
395 
 
396 
      @(posedge c_int);
397 
      begin
398 
      if (select_ok)
399 
      begin
400 
         raz <= `FALSE ;
401 
         if (cpt == 0)
402 
         begin
403 
            data_latch <= 8'b00000000 ;
404 
            byte_ok <= `FALSE ;
405 
         end
406 
         data[7 - cpt] = d;
407 
         if (cpt == 7)
408 
         begin
409 
            byte_ok <= `TRUE ;
410 
            data_latch <= data ;
411 
         end
412 
         else data_latch <= 8'bxxxxxxxx;
413 
      end
414 
      end
415 
   end
416 
 
417 
   //-------------------------------------------------------------
418 
   //--------------- ASYNCHRONOUS DECODE PROCESS -----------------
419 
   //-------------------------------------------------------------
420 
   always
421 
   begin : decode
422 
      //-------------------------
423 
      // status register mask ini
424 
      //-------------------------
425 
      for(i = 0; i <= (`NB_BPI - 1); i = i + 1)
426 
      begin
427 
         sr_mask[i + 2] = 1'b1;
428 
      end
429 
 
430 
 
431 
      @(byte_ok);
432 
      if (byte_ok == 1'b1)
433 
      begin
434 
         //-----------------------------------------------------------
435 
         //-- op_code decode
436 
         //-----------------------------------------------------------
437 
         if (byte_cpt == 0)
438 
         begin
439 
            if (data_latch == 8'b00000110)
440 
            begin
441 
               if (only_rdsr)
442 
               begin
443 
                  if ($time != 0) $display("%t:  ERROR : This Opcode is not decoded during a Prog. Cycle",$realtime);
444 
               end
445 
               else if (only_res)
446 
               begin
447 
                  if ($time != 0) $display("%t:  ERROR :This Opcode is not decoded during a DEEP POWER DOWN ",$realtime);
448 
               end
449 
               else
450 
               begin
451 
                  wren <= `TRUE ;
452 
                  write_op <= `TRUE ;
453 
               end
454 
            end
455 
            else if (data_latch == 8'b00000100)
456 
            begin
457 
               if (only_rdsr)
458 
               begin
459 
                  if ($time != 0) $display("%t:  ERROR : This Opcode is not decoded during a Prog. Cycle ",$realtime);
460 
               end
461 
               else if (only_res)
462 
               begin
463 
                  if ($time != 0) $display("%t:  ERROR : This Opcode is not decoded during a DEEP POWER DOWN ",$realtime);
464 
               end
465 
               else
466 
               begin
467 
                  wrdi <= `TRUE ;
468 
                  write_op <= `TRUE ;
469 
               end
470 
            end
471 
            else if (data_latch == 8'b00000101)
472 
            begin
473 
               if (only_res)
474 
               begin
475 
                  if ($time != 0) $display("%t:  ERROR : This Opcode is not decoded during a DEEP POWER DOWN ",$realtime);
476 
               end
477 
               else
478 
               begin
479 
                  rdsr <= `TRUE ;
480 
               end
481 
            end
482 
            else if (data_latch == 8'b00000001)
483 
            begin
484 
               if (only_rdsr)
485 
               begin
486 
                  if ($time != 0) $display("%t:  ERROR : This Opcode is not decoded during a Prog. Cycle ",$realtime);
487 
               end
488 
               else if (only_res)
489 
               begin
490 
                  if ($time != 0) $display("%t:  ERROR : This Opcode is not decoded during a DEEP POWER DOWN ",$realtime);
491 
               end
492 
               else
493 
               begin
494 
                  wrsr <= `TRUE ;
495 
                  write_op <= `TRUE ;
496 
               end
497 
            end
498 
            else if (data_latch == 8'b00000011)
499 
            begin
500 
               if (only_rdsr)
501 
               begin
502 
                  if ($time != 0) $display("%t:  ERROR : This Opcode is not decoded during a Prog. Cycle ",$realtime);
503 
               end
504 
               else if (only_res)
505 
               begin
506 
                  if ($time != 0) $display("%t:  ERROR : This Opcode is not decoded during a DEEP POWER DOWN ",$realtime);
507 
               end
508 
               else
509 
               begin
510 
                  read_data <= `TRUE ;
511 
                  read_op <= `TRUE ;
512 
               end
513 
            end
514 
            else if (data_latch == 8'b00001011)
515 
            begin
516 
               if (only_rdsr)
517 
               begin
518 
                  if ($time != 0) $display("%t:  ERROR : This Opcode is not decoded during a Prog. Cycle ",$realtime);
519 
               end
520 
               else if (only_res)
521 
               begin
522 
                  if ($time != 0) $display("%t:  ERROR : This Opcode is not decoded during a DEEP POWER DOWN ",$realtime);
523 
               end
524 
               else
525 
               begin
526 
                  fast_read <= `TRUE ;
527 
               end
528 
            end
529 
            else if (data_latch == 8'b00000010)
530 
            begin
531 
               if (only_rdsr)
532 
               begin
533 
                  if ($time != 0) $display("%t:  ERROR : This Opcode is not decoded during a Prog. Cycle ",$realtime);
534 
               end
535 
               else if (only_res)
536 
               begin
537 
                  if ($time != 0) $display("%t:  ERROR : This Opcode is not decoded during a DEEP POWER DOWN ",$realtime);
538 
               end
539 
               else
540 
               begin
541 
                  pp <= `TRUE ;
542 
                  write_op <= `TRUE ;
543 
               end
544 
            end
545 
            else if (data_latch == 8'b11011000)
546 
            begin
547 
               if (only_rdsr)
548 
               begin
549 
                  if ($time != 0) $display("%t:  ERROR : This Opcode is not decoded during a Prog. Cycle ",$realtime);
550 
               end
551 
               else if (only_res)
552 
               begin
553 
                  if ($time != 0) $display("%t:  ERROR : This Opcode is not decoded during a DEEP POWER DOWN ",$realtime);
554 
               end
555 
               else
556 
               begin
557 
                  se <= `TRUE ;
558 
                  write_op <= `TRUE ;
559 
               end
560 
            end
561 
            else if (data_latch == 8'b11000111)
562 
            begin
563 
               if (only_rdsr)
564 
               begin
565 
                  if ($time != 0) $display("%t:  ERROR : This Opcode is not decoded during a Prog. Cycle ",$realtime);
566 
               end
567 
               else if (only_res)
568 
               begin
569 
                  if ($time != 0) $display("%t:  ERROR : This Opcode is not decoded during a DEEP POWER DOWN ",$realtime);
570 
               end
571 
               else
572 
               begin
573 
                  be <= `TRUE ;
574 
                  write_op <= `TRUE ;
575 
                  for(i = 0; i <= (`NB_BPI - 1); i = i + 1)
576 
                  begin
577 
                     bp[i] = status_register[i + 2];
578 
                  end
579 
                  if (bp != 3'b000)
580 
                  begin
581 
                     protect <= `TRUE ;
582 
                     write_op <= `FALSE ;
583 
                  end
584 
               end
585 
            end
586 
            else if (data_latch == 8'b10111001)
587 
            begin
588 
               if (only_rdsr)
589 
               begin
590 
                  if ($time != 0) $display("%t:  ERROR : This Opcode is not decoded during a Prog. Cycle ",$realtime);
591 
               end
592 
               else if (only_res)
593 
               begin
594 
                  if ($time != 0) $display("%t:  ERROR : This Opcode is not decoded during a DEEP POWER DOWN ",$realtime);
595 
               end
596 
               else
597 
               begin
598 
                  dp <= `TRUE ;
599 
               end
600 
            end
601 
            else if (data_latch == 8'b10101011)
602 
            begin
603 
               if (only_rdsr)
604 
               begin
605 
                  if ($time != 0) $display("%t:  ERROR : This Opcode is not decoded during a Prog. Cycle ",$realtime);
606 
               end
607 
               else
608 
               begin
609 
                  res <= `TRUE ;
610 
               end
611 
            end
612 
            else if (data_latch == 8'b10011111)
613 
            begin
614 
               if (only_rdsr)
615 
               begin
616 
                  if ($time != 0) $display("%t:  ERROR : This Opcode is not decoded during a Prog. Cycle ",$realtime);
617 
               end
618 
               else if (only_res)
619 
               begin
620 
                  if ($time != 0) $display("%t:  ERROR : This Opcode is not decoded during a DEEP POWER DOWN ",$realtime);
621 
               end
622 
               else
623 
               begin
624 
                  rdid <= `TRUE ;
625 
               end
626 
            end
627 
            else
628 
            begin
629 
               if ($time != 0) $display("%t:  ERROR : False instruction, please retry ",$realtime);
630 
            end
631 
         end
632 
         //---------------------------------------------------------------------
633 
         // addresses and data reception and treatment
634 
         //---------------------------------------------------------------------
635 
         if ( (byte_cpt == 1) && (!only_rdsr) && (!only_res))
636 
         begin
637 
            if (((read_data) || (fast_read) || (se) || (pp)) && (!rdsr))
638 
            begin
639 
               adress_1 = data_latch;
640 
            end
641 
            else if (wrsr && (!rdsr))
642 
            begin
643 
               wr_latch <= data_latch ;
644 
            end
645 
         end
646 
 
647 
         if ((byte_cpt == 2) && (!only_rdsr) && (!only_res))
648 
         begin
649 
            if (((read_data) || (fast_read) || (se) || (pp)) && (!rdsr))
650 
            begin
651 
               adress_2 = data_latch;
652 
            end
653 
         end
654 
         if ((byte_cpt == 3) && (!only_rdsr) && (!only_res))
655 
         begin
656 
            if (((read_data) || (fast_read) || (se) || (pp)) && (!rdsr))
657 
            begin
658 
               adress_3 = data_latch;
659 
               for(i = 0; i <= (`NB_BIT_ADD - 1); i = i + 1)
660 
               begin
661 
                  adress[i] = adress_3[i];
662 
                  adress[i + `NB_BIT_ADD] = adress_2[i];
663 
                  adress[i + 2 * `NB_BIT_ADD] = adress_1[i];
664 
                  add_mem <= adress ;
665 
               end
666 
               for(i = (`LSB_TO_CODE_PAGE - 1); i >= 0; i = i - 1)
667 
               begin
668 
                  lsb_adress[i] = adress[i];
669 
               end
670 
            end
671 
            if ((se || pp) && (!rdsr))
672 
            begin
673 
               //-----------------------------------------
674 
               // To ignore don't care MSB of the adress
675 
               //-----------------------------------------
676 
               for(i = 0; i <= `BIT_TO_CODE_MEM -1; i = i + 1)
677 
               begin
678 
                  cut_add[i] = adress[i];
679 
               end
680 
               int_add = cut_add;
681 
               //------------------------------------------------
682 
               // Sector protection detection
683 
               //------------------------------------------------
684 
               for(i = 0; i <= (`NB_BPI - 1); i = i + 1)
685 
               begin
686 
                  bp[i] = status_register[i + 2];
687 
               end
688 
               if (bp == 3'b111 || bp == 3'b110) //whole memory write protected
689 
               begin
690 
                  protect <= `TRUE ;
691 
                  write_op <= `FALSE ;
692 
               end
693 
               else if (bp == 3'b101) // address 100000 to 1FFFFF write protected
694 
               begin
695 
                   if (int_add >= ((`TOP_MEM + 1) / 2))
696 
                   begin
697 
                   protect <= `TRUE ;
698 
                   write_op <= `FALSE ;
699 
                   end
700 
               end
701 
               else if (bp == 3'b100) // address 180000 to 1FFFFF write protected
702 
               begin
703 
                   if (int_add >= ((`TOP_MEM + 1) / 4 * 3))
704 
                   begin
705 
                   protect <= `TRUE ;
706 
                   write_op <= `FALSE ;
707 
                   end
708 
               end
709 
               else if (bp == 3'b011) //address 1C0000 to 1FFFFF write protected
710 
               begin
711 
                  if (int_add >= ((`TOP_MEM + 1) * 7 / 8))
712 
                  begin
713 
                     protect <= `TRUE ;
714 
                     write_op <= `FALSE ;
715 
                  end
716 
               end
717 
               else if (bp == 3'b010) //address 1E0000 to 1FFFFF write protected
718 
               begin
719 
                  if (int_add >= ((`TOP_MEM + 1) * 15 / 16))
720 
                  begin
721 
                     protect <= `TRUE ;
722 
                     write_op <= `FALSE ;
723 
                  end
724 
               end
725 
               else if (bp == 3'b001) //address 1F0000 to 1FFFFF write protected
726 
               begin
727 
                   if (int_add >= ((`TOP_MEM + 1) * 31 / 32))
728 
                   begin
729 
                   protect <= `TRUE ;
730 
                   write_op <= `FALSE ;
731 
                   end
732 
               end
733 
               else
734 
               begin
735 
                  protect <= `FALSE ;
736 
               end
737 
            end
738 
         end
739 
         //---------------------------------------------------------------------------
740 
         // PAGE PROGRAM
741 
         // The adress's LSBs necessary to code a whole page are converted to a natural
742 
         // and used to fullfill the page buffer p_prog the same way as the memory page
743 
         // will be fullfilled.
744 
         //--------------------------------------------------------------------------
745 
         if ( (byte_cpt >= 4) && (pp) && (!only_rdsr) && (!rdsr))
746 
         begin
747 
            data_to_write = data_latch ;
748 
            page_add_index = (byte_cpt - 1 - (`NB_BIT_ADD_MEM / `NB_BIT_ADD) + lsb_adress);
749 
         end
750 
         else
751 
         begin
752 
            data_to_write  = 8'bxxxxxxxx;
753 
            page_add_index = 8'bxxxxxxxx;
754 
         end
755 
 
756 
         // to launch adress treatment in memory access
757 
         if (( read_data && (byte_cpt == 3)) || (fast_read && (byte_cpt == 4)))
758 
         begin
759 
            read_enable <= `TRUE ;
760 
         end
761 
         // to send a request for the data pointed by the adress
762 
         if (( read_data && (byte_cpt >= 3)) || ( fast_read && (byte_cpt >= 4)))
763 
         begin
764 
            data_request <= `TRUE ;
765 
         end
766 
      end   //(if byte_ok)
767 
   end   //(process decode)
768 
 
769 
   //-----------------------------------------
770 
   // adresses initialization and reset
771 
   //-----------------------------------------
772 
   always @(posedge select_ok)
773 
   begin
774 
      for(i = 0; i <= (`NB_BIT_ADD - 1); i = i + 1)
775 
      begin
776 
         adress_1[i] = 1'b0;
777 
         adress_2[i] = 1'b0;
778 
         adress_3[i] = 1'b0;
779 
      end
780 
      for(i = 0; i <= (`NB_BIT_ADD_MEM - 1); i = i + 1)
781 
      begin
782 
         adress[i] = 1'b0;
783 
      end
784 
      add_mem <= adress ;
785 
   end
786 
 
787 
 
788 
   always @(negedge byte_ok)
789 
   begin
790 
      if ((read_data && (byte_cpt > 3) ) || (fast_read && (byte_cpt > 4) ))
791 
      begin
792 
         data_request <= `FALSE ;
793 
 
794 
      end
795 
   end
796 
 
797 
   always @(posedge inhib_read)
798 
   begin
799 
         read_op <= `FALSE ;
800 
         read_data <= `FALSE ;
801 
         fast_read <= `FALSE ;
802 
         read_enable <= `FALSE ;
803 
         data_request <= `FALSE ;
804 
 
805 
   end
806 
   //------------------------------------------------------
807 
   // STATUS REGISTER INSTRUCTIONS
808 
   //------------------------------------------------------
809 
   // WREN/WRDI instructions
810 
   //-----------------------
811 
   always @(posedge wel)
812 
   begin
813 
      register_bis[1] <= 1'b1 ;
814 
 
815 
   end
816 
 
817 
   always @(posedge inhib_wren)
818 
   begin
819 
      wren <= `FALSE ;
820 
      write_op <= `FALSE ;
821 
   end
822 
 
823 
   always @(posedge inhib_wrdi)
824 
   begin
825 
      wrdi <= `FALSE ;
826 
      write_op <= `FALSE ;
827 
   end
828 
 
829 
   //----------------------
830 
   // RESET WEL instruction
831 
   //----------------------
832 
   always @(posedge reset_wel)
833 
   begin
834 
      register_bis[1] <= 1'b0 ;
835 
   end
836 
   //-------------------
837 
   // WRSR instructions
838 
   //-------------------
839 
   always @(posedge wr_cycle)
840 
      begin
841 
         if ($time != 0) $display("%t:  NOTE : Write status register cycle has begun ",$realtime);
842 
         register_bis <= ((register_bis) | (8'b00000011)) ;
843 
      end
844 
   always @(negedge wr_cycle)
845 
      begin
846 
         if ($time != 0) $display("%t:  NOTE : Write status register cycle is finished",$realtime);
847 
         register_bis <= ((wr_latch) & sr_mask) ;
848 
         wrsr <= `FALSE ;
849 
      end
850 
 
851 
   always @(posedge inhib_wrsr) wrsr <= `FALSE ;
852 
 
853 
   always @(negedge wrsr) wr_latch <= 8'b00000000 ;
854 
 
855 
   //------
856 
   // PROG
857 
   //------
858 
   always @(wip)
859 
   begin
860 
      if (wip == 1'b1)
861 
      begin
862 
         register_bis[0] <= 1'b1 ;
863 
      end
864 
      else
865 
      begin
866 
         register_bis[0] <= 1'b0 ;
867 
         write_op <= `FALSE ;
868 
 
869 
      end
870 
   end
871 
   //------------------
872 
   // rdsr instruction
873 
   //------------------
874 
   always @(posedge inhib_rdsr) rdsr <= `FALSE ;
875 
   //----------------------------------------------------------
876 
   // BULK/SECTOR ERASE INSTRUCTIONS
877 
   //----------------------------------------------------------
878 
   always @(posedge inhib_be)
879 
   begin
880 
      protect <= `FALSE ;
881 
      be <= `FALSE ;
882 
   end
883 
   always @(posedge inhib_se)
884 
   begin
885 
      protect <= `FALSE ;
886 
      se <= `FALSE ;
887 
   end
888 
   //----------------------------------------------------------
889 
   //PAGE PROGRAM INSTRUCTIONS
890 
   //----------------------------------------------------------
891 
   always @(posedge inhib_pp)
892 
   begin
893 
      protect <= `FALSE ;
894 
      pp <= `FALSE ;
895 
   end
896 
   //----------------------------------------------------------
897 
   // DEEP POWER DOWN
898 
   // RELEASE FROM DEEP POWER DOWN AND READ ELECTRONIC SIGNATURE
899 
   //-----------------------------------------------------------
900 
   always @(posedge inhib_dp) dp <= `FALSE ;
901 
 
902 
   always @(posedge inhib_res) res <= `FALSE ;
903 
 
904 
   //--------------------------------------
905 
   // READ JEDEC ID
906 
   //--------------------------------------
907 
   always @(posedge inhib_rdid) rdid <= `FALSE;
908 
   //--------------------------------------------------------
909 
   //--------------- SYNCHRONOUS PROCESS  ----------------
910 
   //--------------------------------------------------------
911 
   always
912 
   @(c_int or select_ok)
913 
   begin
914 
      wel <= 1'b0 ;
915 
      reset_wel <= 1'b0 ;
916 
   end
917 
 
918 
      //-------------------------------------------
919 
      // READ_data
920 
      //-------------------------------------------
921 
   always
922 
      @(c_int or select_ok)
923 
      begin
924 
         if ((!read_data) && (!fast_read))
925 
         begin
926 
            inhib_read <= `FALSE ;
927 
         end
928 
         if (((byte_cpt == 0) || (byte_cpt == 1) || (byte_cpt == 2) || ((byte_cpt == 3) && (cpt != 7))) && read_data && (!select_ok))
929 
         begin
930 
            if ($time != 0) $display("%t:  WARNING : Instruction canceled because the chip is deselected",$realtime);
931 
            inhib_read <= `TRUE ;
932 
            bit_index <= 8'b00000000;
933 
         end
934 
         if (read_data && (((byte_cpt == 3) && (cpt == 7)) || (byte_cpt >= 4)))
935 
         begin
936 
            if (!select_ok)
937 
            begin
938 
               inhib_read <= `TRUE ;
939 
               bit_index <= 8'b00000000;
940 
               q_bis <= #`TSHQZ 1'bz ;
941 
            end
942 
         end
943 
      end
944 
 
945 
   always
946 
   @(negedge c_int)
947 
   begin
948 
      if (read_data && (((byte_cpt == 3) && (cpt == 7)) || (byte_cpt >= 4)))
949 
      begin
950 
 
951 
         if (select_ok)
952 
         begin
953 
            q_bis <= #`TCLQV data_to_read[7 - bit_index] ;
954 
            bit_index = bit_index + 1;
955 
         end
956 
      end
957 
   end
958 
 
959 
      //------------------------------------------------------------------
960 
      // Fast_Read
961 
      //------------------------------------------------------------------
962 
   always
963 
      @(c_int or select_ok)
964 
      begin
965 
         if (((byte_cpt == 0) || (byte_cpt == 1) || (byte_cpt == 2) || (byte_cpt == 3) || ((byte_cpt == 4) && (cpt != 7))) && fast_read && (!select_ok))
966 
         begin
967 
            if ($time != 0) $display("%t:  WARNING : Instruction canceled because the chip is deselected",$realtime);
968 
            inhib_read <= `TRUE ;
969 
            bit_index <= 8'b00000000;
970 
         end
971 
         if (fast_read && (((byte_cpt == 4) && (cpt == 7)) || (byte_cpt >= 5)))
972 
         begin
973 
            if (!select_ok)
974 
            begin
975 
               inhib_read <= `TRUE ;
976 
               bit_index <= 8'b00000000;
977 
               q_bis <= #`TSHQZ 1'bz ;
978 
            end
979 
         end
980 
      end
981 
 
982 
   always
983 
      @(negedge c_int)
984 
      begin
985 
         if (fast_read && (((byte_cpt == 4) && (cpt == 7)) || (byte_cpt >= 5)))
986 
         begin
987 
            if (select_ok)
988 
            begin
989 
               q_bis <= #`TCLQV data_to_read[7 - bit_index] ;
990 
               bit_index = bit_index + 1 ;
991 
            end
992 
         end
993 
      end
994 
 
995 
      //-----------------------------------------
996 
      // Write_enable
997 
      //-----------------------------------------
998 
   always
999 
      @(c_int or select_ok)
1000 
      begin
1001 
         if (!wren)
1002 
         begin
1003 
            inhib_wren <= `FALSE ;
1004 
         end
1005 
         if (wren && (!only_rdsr) && (!only_res))
1006 
         begin
1007 
            if (!select_ok)
1008 
            begin
1009 
               wel <= 1'b1 ;
1010 
               inhib_wren <= `TRUE ;
1011 
            end
1012 
         end
1013 
      end
1014 
 
1015 
   always
1016 
      @(posedge c_int)
1017 
      begin
1018 
         if (wren && (!only_rdsr) && (!only_res) && select_ok)
1019 
         begin
1020 
            inhib_wren <= `TRUE ;
1021 
            if ($time != 0) $display("%t:  WARNING : Instruction canceled because the chip is still selected",$realtime);
1022 
         end
1023 
      end
1024 
 
1025 
      //-------------------------------------------
1026 
      // Write_disable
1027 
      //-------------------------------------------
1028 
   always
1029 
      @(c_int or select_ok)
1030 
      begin
1031 
         if (!wrdi)
1032 
         begin
1033 
            inhib_wrdi <= `FALSE ;
1034 
         end
1035 
         if (wrdi && (!only_rdsr) && (!only_res))
1036 
         begin
1037 
            if (!select_ok)
1038 
            begin
1039 
               reset_wel <= 1'b1 ;
1040 
               inhib_wrdi <= `TRUE ;
1041 
            end
1042 
         end
1043 
      end
1044 
 
1045 
   always
1046 
      @(posedge c_int)
1047 
      begin
1048 
         if (wrdi && (!only_rdsr) && (!only_res) && select_ok)
1049 
         begin
1050 
            inhib_wrdi <= `TRUE ;
1051 
            if ($time != 0) $display("%t:  WARNING : Instruction canceled because the chip is still selected",$realtime);
1052 
         end
1053 
      end
1054 
 
1055 
      //-----------------------------------------
1056 
      // Write_status_register
1057 
      //-----------------------------------------
1058 
   always
1059 
      @(c_int or select_ok)
1060 
      begin
1061 
         if (!wrsr)
1062 
         begin
1063 
            inhib_wrsr <= `FALSE ;
1064 
            srwd_wrsr <= `FALSE;
1065 
         end
1066 
         if (wrsr && (!only_rdsr) && (!only_res))
1067 
         begin
1068 
            if ((byte_cpt == 1) && ((cpt != 7) || (!byte_ok)) && (!wr_cycle))
1069 
            begin
1070 
               if (!select_ok)
1071 
               begin
1072 
                  if ($time != 0) $display("%t:  WARNING : Instruction canceled because the chip is deselected",$realtime);
1073 
                  inhib_wrsr <= `TRUE ;
1074 
               end
1075 
            end
1076 
            else if ((byte_cpt == 1) && (cpt == 7) && byte_ok)
1077 
            begin
1078 
               if (write_protect)
1079 
               begin
1080 
                  if ($time != 0) $display("%t:  WARNING : Instruction canceled because status register is hardware protected",$realtime);
1081 
                  inhib_wrsr <= `TRUE ;
1082 
                  srwd_wrsr <= `FALSE;
1083 
               end
1084 
            end
1085 
         end
1086 
      end
1087 
 
1088 
  //-------------------------------------------------------------------------------------------
1089 
  // this process returns an error if SRWD=1 and Wc has been switched during a WRSR instruction HC 20/01/03
1090 
  always
1091 
    @(wrsr or write_protect_toggle)
1092 
    begin
1093 
      if (wrsr && write_protect_toggle)
1094 
          begin
1095 
          if ($time != 0) $display("%d", t_write_protect_toggle,":  ERROR : It is not allowed to switch the Wc pin during a WRSR instruction");
1096 
          $finish;
1097 
          end
1098 
      if (wrsr && (status_register[7]) == 1'b1)
1099 
          begin
1100 
          srwd_wrsr <= `TRUE;  // becomes one when WRSR is decoded and WIP=1
1101 
          end
1102 
    end
1103 
 
1104 
 
1105 
   always
1106 
      @(negedge select_ok)
1107 
      begin
1108 
         if (wrsr && (!only_rdsr) && (!only_res))
1109 
         begin
1110 
            if ((byte_cpt == 1) && (cpt == 7) && byte_ok && (!write_protect))
1111 
            begin
1112 
               if ((status_register[1]) == 1'b0)
1113 
               begin
1114 
                  if ($time != 0) $display("%t:  WARNING : Instruction canceled because WEL is reset",$realtime);
1115 
                  inhib_wrsr <= `TRUE ;
1116 
               end
1117 
               else
1118 
               begin
1119 
                  wr_cycle <= `TRUE ;
1120 
                  wip <= 1'b1 ;
1121 
                  #`TW;
1122 
                  wip <= 1'b0 ;
1123 
                  wr_cycle <= `FALSE ;
1124 
               end
1125 
            end
1126 
            else if (byte_cpt == 2)
1127 
            begin
1128 
               if ((status_register[1]) == 1'b0)
1129 
               begin
1130 
                  if ($time != 0) $display("%t:  WARNING : Instruction canceled because WEL is reset",$realtime);
1131 
                  inhib_wrsr <= `TRUE ;
1132 
               end
1133 
               else
1134 
               begin
1135 
                  wr_cycle <= `TRUE ;
1136 
                  wip <= 1'b1 ;
1137 
                  #`TW;
1138 
                  wr_cycle <= `FALSE ;
1139 
                  wip <= 1'b0 ;
1140 
               end
1141 
            end
1142 
         end
1143 
      end
1144 
 
1145 
   always @(posedge c_int)
1146 
   begin
1147 
      if (wrsr && (!only_rdsr) && (!only_res))
1148 
         if (byte_cpt == 2 && !rdsr)
1149 
         begin
1150 
            if ($time != 0) $display("WARNING : Instruction canceled because the chip is still selected",$realtime);
1151 
            inhib_wrsr <= `TRUE ;
1152 
         end
1153 
      end
1154 
 
1155 
      //-------------------------------------------
1156 
      // Bulk_erase
1157 
      //-------------------------------------------
1158 
   always @( c_int or select_ok)
1159 
   begin
1160 
      if (!be)
1161 
      begin
1162 
         inhib_be <= `FALSE ;
1163 
      end
1164 
      if (be && (!only_rdsr) && (!only_res))
1165 
      begin
1166 
         if (!select_ok)
1167 
         begin
1168 
            if ((status_register[1]) == 1'b0)
1169 
            begin
1170 
               if ($time != 0) $display("%t:  WARNING : Instruction canceled because WEL is reset",$realtime);
1171 
               be_enable <= `FALSE ;
1172 
               inhib_be <= `TRUE ;
1173 
            end
1174 
            else if (protect && be)
1175 
            begin
1176 
               if ($time != 0) $display("%t:  WARNING : Instruction canceled because at least one sector is protected",$realtime);
1177 
               be_enable <= `FALSE ;
1178 
               inhib_be <= `TRUE ;
1179 
            end
1180 
            else
1181 
            begin
1182 
               if ($time != 0) $display("%t:  NOTE : Bulk erase cycle has begun",$realtime);
1183 
               be_enable <= `TRUE ;
1184 
               wip <= 1'b1 ;
1185 
              for(j = 1; j <= `TBE; j = j + 1) // Bulk erase duration = TBExTbase = TBE x 1s (to avoid number wider thab 32 bit)
1186 
                  begin
1187 
                    #`Tbase ;
1188 
                  end
1189 
               if ($time != 0) $display("%t:  NOTE : Bulk erase cycle is finished",$realtime);
1190 
               be_enable <= `FALSE ;
1191 
               inhib_be <= `TRUE ;
1192 
               wip <= 1'b0 ;
1193 
               reset_wel <= 1'b1 ;
1194 
            end
1195 
         end
1196 
      end
1197 
   end
1198 
 
1199 
   always @(posedge c_int)
1200 
   begin
1201 
      if (be && (!only_rdsr) && (!only_res))
1202 
      begin
1203 
         if ($time != 0) $display("%t:  WARNING : Instruction canceled because the chip is still selected",$realtime);
1204 
         inhib_be <= `TRUE ;
1205 
      end
1206 
   end
1207 
 
1208 
      //-------------------------------------------
1209 
      // Sector_erase
1210 
      //-------------------------------------------
1211 
   always @( c_int or select_ok)
1212 
   begin
1213 
      if (!se)
1214 
      begin
1215 
         inhib_se <= `FALSE ;
1216 
      end
1217 
      if (((byte_cpt == 0) || (byte_cpt == 1) || (byte_cpt == 2) || ((byte_cpt == 3) && ((cpt != 7) || !byte_ok))) && se && (!only_rdsr) && (!only_res))
1218 
      begin
1219 
         if (!select_ok)
1220 
         begin
1221 
            if ($time != 0) $display("%t:  WARNING : Instruction canceled because the chip is deselected",$realtime);
1222 
            inhib_se <= `TRUE ;
1223 
         end
1224 
      end
1225 
      if ( ((byte_cpt == 4) || ((byte_cpt == 3) && (cpt == 7) && byte_ok)) && se && (!only_rdsr) && (!only_res))
1226 
      begin
1227 
         if (!select_ok)
1228 
         begin
1229 
            if ((status_register[1]) == 1'b0)
1230 
            begin
1231 
               if ($time != 0) $display("%t:  WARNING : Instruction canceled because WEL is reset",$realtime);
1232 
               se_enable <= `FALSE ;
1233 
               inhib_se <= `TRUE ;
1234 
            end
1235 
            else if (protect && se)
1236 
            begin
1237 
               if ($time != 0) $display("%t:  WARNING : Instruction canceled because the SE sector is protected",$realtime);
1238 
               se_enable <= `FALSE ;
1239 
               inhib_se <= `TRUE ;
1240 
            end
1241 
            else
1242 
            begin
1243 
               if ($time != 0) $display("%t:  NOTE : Sector erase cycle has begun",$realtime);
1244 
               se_enable <= `TRUE ;
1245 
               wip <= 1'b1 ;
1246 
              for(j = 1; j <= `TSE; j = j + 1) // Sector erase duration = TSE x Tbase = TSE x 1s (to avoid number wider thab 32 bit)
1247 
                  begin
1248 
                    #`Tbase ;
1249 
                  end
1250 
               if ($time != 0) $display("%t:  NOTE : Sector erase cycle is finished",$realtime);
1251 
               se_enable <= `FALSE ;
1252 
               inhib_se <= `TRUE ;
1253 
               wip <= 1'b0 ;
1254 
               reset_wel <= 1'b1 ;
1255 
            end
1256 
         end
1257 
      end
1258 
   end
1259 
 
1260 
   always @(posedge c_int)
1261 
   begin
1262 
      if ( ((byte_cpt == 4) || ((byte_cpt == 3) && (cpt == 7) && byte_ok)) && se && (!only_rdsr) && (!only_res))
1263 
      begin
1264 
         if (byte_cpt == 4 && select_ok)
1265 
         begin
1266 
            if ($time != 0) $display("%t:  WARNING : Instruction canceled because the chip is still selected",$realtime);
1267 
            inhib_se <= `TRUE ;
1268 
         end
1269 
      end
1270 
   end
1271 
 
1272 
      //-------------------------------------------
1273 
      // Page_Program
1274 
      //-------------------------------------------
1275 
   always @(c_int or select_ok)
1276 
   begin
1277 
      if (!pp)
1278 
      begin
1279 
         inhib_pp <= `FALSE ;
1280 
         add_pp_enable <= `FALSE ;
1281 
         pp_enable <= `FALSE ;
1282 
      end
1283 
 
1284 
      if (((byte_cpt == 5) || ((byte_cpt == 4) && (cpt == 7))) && pp && (!only_rdsr) && (!only_res))
1285 
      begin
1286 
         add_pp_enable <= `TRUE ;
1287 
         if ((status_register[1]) == 1'b0)
1288 
         begin
1289 
            if ($time != 0) $display("%t:  WARNING : Instruction canceled because WEL is reset",$realtime);
1290 
            pp_enable <= `FALSE ;
1291 
            inhib_pp <= `TRUE ;
1292 
         end
1293 
         else if (protect && pp)
1294 
         begin
1295 
            if ($time != 0) $display("%t:  WARNING : Instruction canceled because the PP sector is protected",$realtime);
1296 
            pp_enable <= `FALSE ;
1297 
            inhib_pp <= `TRUE ;
1298 
         end
1299 
      end
1300 
   end
1301 
 
1302 
   always @(negedge select_ok)
1303 
   begin
1304 
      if (((byte_cpt == 0) || (byte_cpt == 1) || (byte_cpt == 2) || (byte_cpt == 3) || ((byte_cpt == 4) && ((cpt != 7) || !byte_ok))) && pp && (!only_rdsr) && (!only_res) && (!select_ok))
1305 
         begin
1306 
            if ($time != 0) $display("%t:  WARNING : Instruction canceled because the chip is deselected",$realtime);
1307 
            inhib_pp <= `TRUE ;
1308 
         end
1309 
      if (((byte_cpt == 5) || ((byte_cpt == 4) && (cpt == 7))) && pp && (!only_rdsr) && (!only_res))
1310 
      begin
1311 
         add_pp_enable <= `TRUE ;
1312 
         if (pp)
1313 
         begin
1314 
            if ($time != 0) $display("%t:  NOTE : Page program cycle is started",$realtime);
1315 
            wip <= 1'b1 ;
1316 
            #`TPP;
1317 
            if ($time != 0) $display("%t:  NOTE : Page program cycle is finished",$realtime);
1318 
            pp_enable <= `TRUE ;
1319 
            wip <= 1'b0 ;
1320 
            inhib_pp <= `TRUE ;
1321 
            reset_wel <= 1'b1 ;
1322 
         end
1323 
      end
1324 
      if ((byte_cpt > 5) && pp && (!only_rdsr) && (!only_res) && byte_ok)
1325 
      begin
1326 
         if ($time != 0) $display("%t:  NOTE : Page program cycle is started",$realtime);
1327 
         wip <= 1'b1 ;
1328 
         #`TPP;
1329 
         if ($time != 0) $display("%t:  NOTE : Page program cycle is finished",$realtime);
1330 
         pp_enable <= `TRUE ;
1331 
         wip <= 1'b0 ;
1332 
         inhib_pp <= `TRUE ;
1333 
         reset_wel <= 1'b1 ;
1334 
      end
1335 
      if ((byte_cpt > 5) && pp && (!only_rdsr) && (!only_res) && (!byte_ok))
1336 
      begin
1337 
         if ($time != 0) $display("%t:  WARNING : Instruction canceled because the chip is deselected",$realtime);
1338 
         inhib_pp <= `TRUE ;
1339 
         pp_enable <= `FALSE ;
1340 
      end
1341 
   end
1342 
 
1343 
      //-----------------------------------------
1344 
      // Deep Power Down
1345 
      //-----------------------------------------
1346 
   always @(c_int or select_ok)
1347 
   begin
1348 
      if (!dp)
1349 
      begin
1350 
         inhib_dp <= `FALSE ;
1351 
         only_res <= `FALSE ;
1352 
         t_only_res = 0;
1353 
      end
1354 
   end
1355 
 
1356 
   always @(posedge c_int)
1357 
   begin
1358 
      if (dp && (!only_rdsr) && (!only_res) && (!res))
1359 
      begin
1360 
         if ($time != 0) $display("%t:  WARNING : Instruction canceled because the chip is still selected",$realtime);
1361 
         inhib_dp <= `TRUE ;
1362 
         only_res <= `FALSE ;
1363 
         t_only_res = 0;
1364 
      end
1365 
   end
1366 
 
1367 
   always @(negedge select_ok)
1368 
   begin
1369 
      if (dp && (!only_rdsr) && (!only_res) && (!res))
1370 
      begin
1371 
         if ($time != 0) $display("%t:  NOTE : Chip is entering deep power down mode",$realtime);
1372 
         // useful when chip is selected again to inhib every op_code except RES
1373 
         // and to check tDP
1374 
         t_only_res = $time;
1375 
         only_res <= `TRUE ;
1376 
 
1377 
      end
1378 
   end
1379 
 
1380 
      //---------------------------------------------------------------------
1381 
      // Release from Deep Power Down Mode and Read Electronic Signature
1382 
      //---------------------------------------------------------------------
1383 
   always @(select_ok or c_int)
1384 
   begin
1385 
      if (!res)
1386 
      begin
1387 
         inhib_res <= `FALSE ;
1388 
         bit_res <= 0;
1389 
      end
1390 
 
1391 
      if (res && ((byte_cpt == 1) && (cpt == 0)) && (!only_rdsr) && (!select_ok))
1392 
      begin
1393 
      if (only_res)
1394 
         begin
1395 
         if ($time != 0) $display("%t:  NOTE : The chip is releasing from DEEP POWER DOWN",$realtime);
1396 
         inhib_res <= `FALSE; inhib_dp <= `FALSE; #`TRES1;
1397 
         inhib_res <= `TRUE; inhib_dp <= `TRUE;
1398 
         end
1399 
      else   inhib_res <= `TRUE;  inhib_dp <= `TRUE;
1400 
      end
1401 
      else if ((((byte_cpt == 1) && (cpt > 0)) || (byte_cpt == 2) || (byte_cpt == 3) || ((byte_cpt == 4) && ((cpt < 7) || (!byte_ok)))) && res && (!only_rdsr) && (!select_ok))
1402 
      begin
1403 
         if ($time != 0) $display("%t:  ERROR : Electronic Signature must be read at least once. Instruction not valid",$realtime);
1404 
      end
1405 
      else if ((((byte_cpt == 4) && (cpt == 7) && byte_ok) || (byte_cpt > 4)) && res && (!only_rdsr) && (!select_ok))
1406 
                  begin
1407 
                  if (only_res)
1408 
                      begin
1409 
                      if ($time != 0) $display("%t:  NOTE : The Chip is releasing from DEEP POWER DOWN",$realtime);
1410 
                      inhib_res <= `FALSE ; inhib_dp <=  `FALSE ;#`TRES2;
1411 
                      inhib_res <= `TRUE ; inhib_dp <=  `TRUE;
1412 
                      end
1413 
                  else   inhib_res <= `TRUE ; inhib_dp <=  `TRUE;
1414 
                  q_bis <= 1'bz ;
1415 
                  end
1416 
      end
1417 
 
1418 
 
1419 
   always @(negedge c_int)
1420 
   begin
1421 
      if ((((byte_cpt == 3) && (cpt == 7)) || (byte_cpt >= 4)) && res && (!only_rdsr) )
1422 
      begin
1423 
         q_bis <= #`TCLQV signature[7 - bit_res] ;
1424 
         bit_res = bit_res + 1;
1425 
      end
1426 
   end
1427 
 
1428 
 
1429 
   /////////////////////////////////////////////////////// //modified by xue-feng hu  06/04/04
1430 
   // This process shifts out identification on data output
1431 
   always
1432 
      @(c_int or select_ok or rdid)
1433 
      begin
1434 
         if (!rdid)
1435 
         begin
1436 
            inhib_rdid <= `FALSE;
1437 
         end
1438 
         if(rdid && (!select_ok))
1439 
         begin
1440 
            bit_id <= 0;
1441 
            q_bis <= #`TSHQZ 1'bz;
1442 
            inhib_rdid <= `TRUE;
1443 
         end
1444 
      end
1445 
    always
1446 
        @(negedge c_int)
1447 
        begin
1448 
            if(rdid && (select_ok))
1449 
            begin
1450 
              q_bis <= #`TCLQV id[23 - bit_id];
1451 
              bit_id = bit_id + 1;
1452 
              if(bit_id > 23)   bit_id = 0;
1453 
            end
1454 
        end
1455 
   //---------------------
1456 
   // READ JEDEC ID    //HC 18/02/04
1457 
   //---------------------
1458 
   //always @(select_ok or c_int)
1459 
   //begin
1460 
   //        if (!rdid)
1461 
   //            begin
1462 
   //            inhib_rdid <= `FALSE;
1463 
   //            end
1464 
   //        if (rdid && ((byte_cpt==0 && cpt==7) || byte_cpt >=1))
1465 
   //            begin
1466 
   //            if (!select_ok)
1467 
   //               begin
1468 
   //               inhib_rdid <= `TRUE;
1469 
   //               k <= 0;
1470 
   //               q_bis <= #`TSHQZ 1'bz;
1471 
   //               end
1472 
   //            else if (c_int == 0 && byte_cpt ==1)
1473 
   //                begin
1474 
   //                q_bis <= #`TCLQV manufacturerID[7-k];
1475 
   //                k= k+1;
1476 
   //                end
1477 
   //            else if (c_int == 0 && byte_cpt == 2)
1478 
   //                begin
1479 
   //                q_bis <= #`TCLQV memtype[7-k];
1480 
   //                k= k+1;
1481 
   //                end
1482 
   //            else if (c_int == 0 && byte_cpt == 3)
1483 
   //                begin
1484 
   //                q_bis <= #`TCLQV density[7-k];
1485 
   //                k= k+1;
1486 
   //                end
1487 
   //            else if (c_int == 0 && byte_cpt >= 4)
1488 
   //                begin
1489 
   //                q_bis <= #`TCLQV 1'b0;
1490 
   //                end
1491 
   //            end
1492 
   //    end
1493 
 
1494 
 
1495 
   //-------------------------------------------------------
1496 
   // This process shifts out status register on data output
1497 
   always
1498 
      @(c_int or select_ok or rdsr)
1499 
      begin
1500 
         if (!rdsr)
1501 
         begin
1502 
            inhib_rdsr <= `FALSE ;
1503 
         end
1504 
         if (rdsr && (!select_ok))
1505 
         begin
1506 
            bit_register <= 0;
1507 
            q_bis <= #`TSHQZ 1'bz ;
1508 
            inhib_rdsr <= `TRUE ;
1509 
         end
1510 
      end
1511 
 
1512 
   always
1513 
      @(negedge c_int)
1514 
      begin
1515 
         if (rdsr && (select_ok))
1516 
         begin
1517 
            q_bis <= #`TCLQV status_register[7 - bit_register] ;
1518 
            bit_register = bit_register + 1;
1519 
         end
1520 
      end
1521 
   //--------------------------------------------------------------------------------------
1522 
   // This process checks select and deselect conditions. Some other conditions are tested:
1523 
   // prog cycle, deep power down mode and read electronic signature.
1524 
   always
1525 
   begin : pin_s
1526 
      @(s);
1527 
      begin
1528 
      if (s == 1'b0)
1529 
      begin
1530 
         if (res && only_res)
1531 
         begin
1532 
            if ($time != 0) $display("%t:  ERROR : The chip must not be selected until tRES",$realtime);
1533 
         end
1534 
         else if (dp)
1535 
         begin
1536 
            if (($time - t_only_res) < `TDP)
1537 
            begin
1538 
               if ($time != 0) $display("%t:  ERROR : The chip must not be selected until tDP",$realtime);
1539 
            end
1540 
            else
1541 
            begin
1542 
               if ($time != 0) $display("%t:  NOTE : Only a Read Electronic Signature instruction will be valid",$realtime);
1543 
            end
1544 
         end
1545 
         select_ok <= `TRUE ;
1546 
         if (pp || wrsr || be || se)
1547 
         begin
1548 
            if ($time != 0) $display("%t:  NOTE : Only a Read Status Register instruction will be valid",$realtime);
1549 
            only_rdsr <= `TRUE ;
1550 
         end
1551 
      end
1552 
      else
1553 
      begin
1554 
         select_ok <= `FALSE ;
1555 
         only_rdsr <= `FALSE ;
1556 
      end
1557 
      end
1558 
   end
1559 
 
1560 
   //--------------------------------------------------------------
1561 
   // This Process detects the hardware protection mode
1562 
   always
1563 
      @(w or c_int)
1564 
      begin
1565 
         if ((w == 1'b0) && ((status_register[7]) == 1'b1))
1566 
         begin
1567 
            write_protect <= `TRUE ;
1568 
         end
1569 
         if (w == 1'b1)
1570 
         begin
1571 
            write_protect <= `FALSE ;
1572 
         end
1573 
      end
1574 
 
1575 
 
1576 
   //--------------------------------------------------------------
1577 
   // this process detects if write_protect toggles during an instruction
1578 
   always
1579 
   @(select_ok)
1580 
   begin
1581 
       if (select_ok)
1582 
       begin
1583 
            @(write_protect)
1584 
            write_protect_toggle <= `TRUE;
1585 
            if ($time != 0)
1586 
                begin
1587 
                t_write_protect_toggle = $time;
1588 
                end
1589 
       end
1590 
       if (!select_ok)
1591 
       begin
1592 
            write_protect_toggle <= `FALSE;
1593 
       end
1594 
   end
1595 
endmodule
1596 
 
1597 
 

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