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[/] [uart2spi/] [trunk/] [verif/] [models/] [st_m25p16/] [m25p16_driver.v] - Blame information for rev 3

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Line No. Rev Author Line
1 3 dinesha 
// Author: Hugues CREUSY modified by Xue feng
2 
// June 2004
3 
// Verilog model
4 
// project: M25P16 50 MHz,
5 
// release: 1.2
6 
 
7 
 
8 
 
9 
// These Verilog HDL models are provided "as is" without warranty
10 
// of any kind, included but not limited to, implied warranty
11 
// of merchantability and fitness for a particular purpose.
12 
 
13 
 
14 
 
15 
 
16 
 
17 
`timescale 1ns/1ns
18 
`include "parameter.v"
19 
 
20 
module m25p16_driver (clk, din, cs_valid, hard_protect, hold);
21 
 
22 
 
23 
   output clk;
24 
   reg clk;
25 
 
26 
   output din;
27 
   reg din;
28 
 
29 
   output cs_valid;
30 
   reg cs_valid;
31 
 
32 
   output hard_protect;
33 
   reg hard_protect;
34 
 
35 
   output hold;
36 
   reg hold;
37 
 
38 
   initial
39 
   begin : init_driver
40 
/*      $monitor($time,,,
41 
               "C = %b D = %b _S = %b _W = %b _H = %b",
42 
               clk,din,cs_valid,hard_protect,hold);
43 
*/
44 
      clk = 1'b0 ;
45 
      din = 1'b1 ;
46 
      cs_valid = 1'b1 ;
47 
      hold = 1'b1 ;
48 
      hard_protect = 1'b1 ;
49 
 
50 
   end
51 
 
52 
   always
53 
   begin : driver
54 
      parameter thigh = 20;
55 
      parameter tlow = 20;
56 
      #100000
57 
    /////////////////////////////// modified by xue-feng hu, for RDID verilication
58 
    rdid(thigh,tlow,26);
59 
    $stop;
60 
 
61 
// Checking memory initialization at higher speed
62 
      fast_read( thigh,tlow, 24'b111111111111111111111111, 2);
63 
      #(5 * tlow);
64 
      fast_read( thigh,tlow, 24'b000000010000000000000000, 15);
65 
      #(5 * tlow);
66 
      fast_read( thigh,tlow, 24'b000000100000000000000000, 15);
67 
      #(5 * tlow);
68 
      fast_read( thigh,tlow, 24'b000000110000000000000000, 15);
69 
      #(5 * tlow);
70 
 
71 
// hold condition test during a WREN
72 
      hold_wren( thigh,tlow);
73 
      #(5 * tlow);
74 
      rdsr( thigh,tlow, 1);
75 
      #(5 * tlow);
76 
      wrdi( thigh,tlow);
77 
      #(5 * tlow);
78 
      rdsr( thigh,tlow, 1);
79 
      #(5 * tlow);
80 
 
81 
// WREN/WRDI test
82 
      wren( thigh,tlow);
83 
      #(5 * tlow);
84 
      rdsr( thigh,tlow, 1);
85 
      #(5 * tlow);
86 
      wrdi( thigh,tlow);
87 
      #(5 * tlow);
88 
      rdsr( thigh,tlow, 1);
89 
      #(5 * tlow);
90 
 
91 
// WRSR : Protect All sectors + Set SRWD
92 
      wren( thigh,tlow);
93 
      #(5 * tlow);
94 
      wrsr( thigh,tlow, 8'b11111111);
95 
      #14965000;     // WRSR not completed if Tw < 15ms
96 
// WIP Polling during Prog Cycle
97 
      rdsr(thigh, tlow, 120);
98 
      #(5 * tlow);
99 
 
100 
// WRSR canceled by HPM (SRWD bit is still set)
101 
      wren( thigh,tlow);
102 
      #(5 * tlow);
103 
      hard_protect <= 1'b0 ;
104 
      #(5 * tlow);
105 
      wrsr( thigh,tlow,8'b00000000);
106 
      #(5 * tlow);
107 
      hard_protect <= 1'b1 ;
108 
      #(5 * tlow);   // All sectors are still protected
109 
 
110 
// OPCODES sent during Deep Power Down Mode will have no effect on device
111 
      dp( thigh,tlow);
112 
      #3001;               // Deep Power Down Mode is active after 3us
113 
      wren( thigh,tlow);
114 
      #(5 * tlow);
115 
      rdsr( thigh,tlow, 1);
116 
      #(5 * tlow);
117 
      pp( thigh,tlow, 24'b000011111100001111000011, 8'b10101010, 15);
118 
      #(5 * tlow);
119 
      read(2 * thigh, 2 * tlow, 24'b000011111100001111000011, 15);
120 
      #(5 * tlow);
121 
      read(2 * thigh, 2 * tlow, 24'b000011111100001111000011, 15);
122 
      #(5 * tlow);
123 
      be(thigh, tlow);
124 
      #(5 * tlow);
125 
      se(thigh, tlow, 24'b000000000000000000000000);
126 
      #(5 * tlow);
127 
      fast_read( thigh,tlow, 24'b111111111111111111111111, 15);
128 
      #(5 * tlow);
129 
      wrdi(thigh, tlow);
130 
      #(5 * tlow);
131 
      res(thigh, tlow);
132 
      #3001;               // Device is returned into StandBy Mode
133 
 
134 
      read_es(thigh, tlow);
135 
      #(5 * tlow);
136 
      read_es(thigh, tlow);
137 
      #(5 * tlow);
138 
 
139 
// Page prog on protected sectors will have no effect
140 
      pp(thigh, tlow, 24'b000011111100001111000011, 8'b10101010, 15);
141 
      #(5 * tlow);
142 
// Device content still virgin
143 
      fast_read( thigh,tlow, 24'h0FC3C3, 15);
144 
      #(5 * tlow);
145 
 
146 
// WRSR to reset BP(i) bits ; All sectors unprotected
147 
      wren(thigh, tlow);
148 
      #(5 * tlow);
149 
      wrsr(thigh, tlow, 8'b00000000);
150 
      #14965000;                          // WRSR not completed if Tw < 15ms
151 
      rdsr(thigh, tlow, 120);             // WIP polling during Write progress
152 
      #(5 * tlow);                        // device is not protected anymore
153 
 
154 
// Sector Erase Instruction Check
155 
      wren(thigh, tlow);
156 
      #(5 * tlow);
157 
      be(thigh, tlow);                          // Erase all device
158 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
159 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
160 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
161 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
162 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
163 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
164 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
165 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
166 
      #`Tbase ;  #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
167 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
168 
      #`Tbase ;  #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
169 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
170 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
171 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
172 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
173 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
174 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
175 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
176 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
177 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
178 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
179 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
180 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
181 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
182 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
183 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
184 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
185 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
186 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
187 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
188 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
189 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
190 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
191 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
192 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
193 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
194 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
195 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
196 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
197 
       #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;#(`Tbase+1) ; // 200s
198 
      wren(thigh, tlow);
199 
      #(5 * tlow);
200 
      pp(thigh, tlow, 24'h00000, 8'h00, 1);   // prog first byte of sector 0
201 
      #5000001;
202 
      fast_read( thigh,tlow, 24'h3FFFF, 3);   // read last and 2 first byte of memory
203 
      #(5 * tlow);
204 
 
205 
      wren(thigh, tlow);
206 
      #(5 * tlow);
207 
      pp(thigh, tlow, 24'h2FFFF, 8'h88, 255);   // prog last row of sector 2 except 1 byte to check roll over in write inside a page
208 
      #5000001;   // 5ms
209 
      fast_read( thigh,tlow, 24'h2FFFD, 3);   // read 3 last byte of sector 2
210 
      #(5 * tlow);
211 
      wren(thigh, tlow);
212 
      #(5 * tlow);
213 
      pp(thigh, tlow, 24'h30000, 8'hAA, 256);   // prog first row of sector 3
214 
      #5000001;
215 
      fast_read( thigh,tlow, 24'h2FF00, 512);   // read two previous rows
216 
      #(5 * tlow);
217 
 
218 
      wren(thigh, tlow);
219 
      #(5 * tlow);
220 
      wrsr(thigh, tlow, 8'b00000100);           // protection of sector 3 (30000h to 3FFFFh )
221 
      #15000001;  // 15ms
222 
      rdsr(thigh, tlow, 1);
223 
      #(5 * tlow);
224 
 
225 
      wren(thigh, tlow);
226 
      #(5 * tlow);
227 
      pp(thigh, tlow, 24'h30000, 8'h55, 256);   // prog first row of sector 3 (protected)
228 
      #5000001;
229 
      fast_read( thigh,tlow, 24'h2FF00, 512);   // read first row of sector 3 & last row of sector 2
230 
      #(5 * tlow);
231 
 
232 
      wren(thigh, tlow);
233 
      #(5 * tlow);
234 
      se(thigh, tlow, 24'h2FFFF);   // Erase sector 2 (not protected)
235 
      #`Tbase ;
236 
      #`Tbase ;
237 
      #(`Tbase+1) ;      // 3s
238 
      wren(thigh, tlow);
239 
      #(5 * tlow);
240 
      se(thigh, tlow, 24'h30000);   // Erase  sector 3 (protected)
241 
      #`Tbase ;
242 
      #`Tbase ;
243 
      #(`Tbase+1) ;      // 3s
244 
 
245 
      fast_read( thigh,tlow, 24'h2FF00, 1);   // read first byte of last page of sector 2
246 
      #(5 * tlow);
247 
      fast_read( thigh,tlow, 24'h2FFFD, 4);   // read 3 last bytes of sector 2 & first byte of sector 3
248 
      #(5 * tlow);
249 
      fast_read( thigh,tlow, 24'h3FFFF, 3);   // read last byte of sector 3 & first byte of sector 1 to check roll over in read inside memory array
250 
      #(5 * tlow);
251 
 
252 
      wren(thigh, tlow);
253 
      #(5 * tlow);
254 
      wrsr(thigh, tlow, 8'h00);           // Unprotect sector 3
255 
      #15000001;
256 
// End Sector Erase Instruction Check
257 
 
258 
// deep power down mode AND release from deep power down + read electronic signature
259 
      dp(thigh, tlow);
260 
      #3001;
261 
      read_es(thigh, tlow);
262 
      #1801;      // 1.8us
263 
 
264 
// READ programmed bytes preceded and followed by one non programmed byte
265 
      wren(thigh, tlow);
266 
      #(5 * tlow);
267 
      pp(thigh, tlow, 24'h00101, 8'b10101010, 10);
268 
      #4965000;
269 
      rdsr(thigh, tlow, 120);    //WIP Polling
270 
      #(5 * tlow);
271 
 
272 
 
273 
// Program 55h on AAh
274 
      wren(thigh, tlow);
275 
      #(5 * tlow);
276 
      pp(thigh, tlow, 24'h00102, 8'b01010101, 8);
277 
      #4965000;
278 
      rdsr(thigh, tlow, 120);    // WIP Polling
279 
      #(5 * tlow);
280 
// READ: AAh+55h=>00h
281 
      fast_read(thigh, tlow, 24'h00100, 12);
282 
      #(5 * tlow);
283 
      read(2 * thigh, 2 * tlow, 24'h00100, 12);
284 
      #(5 * tlow);
285 
 
286 
// Page prog of more than 256 bytes in the sectors 1 and 2.
287 
// Note: the PP task sends automatically 00h when byte number is higher than 256
288 
      wren(thigh, tlow);
289 
      #(5 * tlow);
290 
      pp(thigh, tlow, 24'b000000010000000000000000, 8'b01010101, 280);
291 
      #5010000;   // 5.01ms
292 
      read(2 * thigh, 2 * tlow, 24'b000000010000000000000000, 256);
293 
      #(5 * tlow);
294 
      wren(thigh, tlow);
295 
      #(5 * tlow);
296 
      pp(thigh, tlow, 24'b000000100000000000000000, 8'b01010101, 280);
297 
      #5010000;
298 
      read(2 * thigh, 2 * tlow, 24'b000000100000000000000000, 256);
299 
      #(5 * tlow);
300 
 
301 
// Erase all memory content
302 
      wren(thigh, tlow);
303 
      #(5 * tlow);
304 
      wren(thigh, tlow);
305 
      #(5 * tlow);
306 
      be(thigh, tlow);
307 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
308 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
309 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
310 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
311 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
312 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
313 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
314 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
315 
      #`Tbase ;  #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
316 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
317 
      #`Tbase ;  #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
318 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
319 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
320 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
321 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
322 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
323 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
324 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
325 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
326 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
327 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
328 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
329 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
330 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
331 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
332 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
333 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
334 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
335 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
336 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
337 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
338 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
339 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
340 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
341 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
342 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
343 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
344 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
345 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
346 
       #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;#(`Tbase+1) ; // 200s
347 
 
348 
// protects the fisrt 1/8
349 
      wren(thigh, tlow);
350 
      #(5 * tlow);
351 
      wren(thigh, tlow);
352 
      #(5 * tlow);
353 
      wrsr(thigh, tlow, 8'b00000100);  // protect sector 3
354 
      #15001000;        // 15ms
355 
      rdsr(thigh, tlow, 1);
356 
      #(5 * tlow);
357 
 
358 
// Bulk erase on a protected area
359 
      wren(thigh, tlow);
360 
      wren(thigh, tlow);
361 
      #(5 * tlow);
362 
      be(thigh, tlow);
363 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
364 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
365 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
366 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
367 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
368 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
369 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
370 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
371 
      #`Tbase ;  #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
372 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
373 
      #`Tbase ;  #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
374 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
375 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
376 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
377 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
378 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
379 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
380 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
381 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
382 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
383 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
384 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
385 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
386 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
387 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
388 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
389 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
390 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
391 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
392 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
393 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
394 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
395 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
396 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
397 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
398 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
399 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
400 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
401 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
402 
       #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;#(`Tbase+1) ; // 200s
403 
 
404 
// unprotects memory
405 
      wren(thigh, tlow);
406 
      #(5 * tlow);
407 
      wrsr(thigh, tlow, 8'b00000000);  // unprotect sector 3
408 
      #15001000;        // 15ms
409 
      rdsr(thigh, tlow, 1);
410 
      #(5 * tlow);
411 
 
412 
// Bulk erase on an unprotected device
413 
      wren(thigh, tlow);
414 
      #(5 * tlow);
415 
      wren(thigh, tlow);
416 
      #(5 * tlow);
417 
      be(thigh, tlow);
418 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
419 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
420 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
421 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
422 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
423 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
424 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
425 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
426 
      #`Tbase ;  #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
427 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
428 
      #`Tbase ;  #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
429 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
430 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
431 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
432 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
433 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
434 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
435 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
436 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
437 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
438 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
439 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
440 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
441 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
442 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
443 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
444 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
445 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
446 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
447 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
448 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
449 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
450 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
451 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
452 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
453 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
454 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
455 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
456 
      #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;
457 
       #`Tbase ; #`Tbase ; #`Tbase ; #`Tbase ;#(`Tbase+1) ; // 200s
458 
 
459 
// READ again to check BE
460 
      wren(thigh, tlow);
461 
      #(5 * tlow);
462 
      read(2 * thigh, 2 * tlow, 24'b000011111100001111000010, 17);
463 
      #(5 * tlow);
464 
      read(2 * thigh, 2 * tlow, 24'b000000000000000000000000, 15);
465 
      #(5 * tlow);
466 
      read(2 * thigh, 2 * tlow, 24'b000000111111111111111111, 15);
467 
      #(5 * tlow);
468 
      read(2 * thigh, 2 * tlow, 24'b000000111111111100000000, 15);
469 
      #(5 * tlow);
470 
      read(2 * thigh, 2 * tlow, 24'b000000010000000000000000, 1);
471 
      #(5 * tlow);
472 
      read(2 * thigh, 2 * tlow, 24'b000000100000000000000000, 1);
473 
      #(5 * tlow);
474 
      #100000 $finish;
475 
   end
476 
 
477 
 
478 
      task stop;
479 
            input t0;
480 
            time t0;
481 
            input t1;
482 
            time t1;
483 
 
484 
            begin
485 
               hold <= 1'b1 ;
486 
 
487 
               #t0 hold <= 1'b0 ;
488 
               #t1 hold <= 1'b1 ;
489 
            end
490 
      endtask
491 
 
492 
      task hold_wren;
493 
         input t1;
494 
         time t1;
495 
         input t0;
496 
         time t0;
497 
         integer i;
498 
 
499 
         begin
500 
            cs_valid <= 1'b1 ;
501 
            hold <= 1'b1 ;
502 
            clk <= 1'b0 ;
503 
            #t0;
504 
               for(i = 0; i <= 17; i = i + 1)
505 
               begin
506 
                  if (i == 0)
507 
                  begin
508 
                     cs_valid <= 1'b0 ;
509 
                     hold <= 1'b1 ;
510 
                     din <= 1'b0 ;
511 
                  end
512 
                  if ((i == 5) || (i == 6))
513 
                  begin
514 
                     din <= 1'b1 ;
515 
                  end
516 
                  else
517 
                  begin
518 
                     din <= 1'b0 ;
519 
                  end
520 
                  clk <= 1'b0 ;
521 
                  #t0;
522 
                  clk <= 1'b1 ;
523 
                  if (i == 12)
524 
                  begin
525 
                     cs_valid <= 1'b1 ;
526 
                  end
527 
                  #((t1 / 2));
528 
                  if (i == 7)
529 
                  begin
530 
                     hold <= 1'b0 ;
531 
                  end
532 
                  #((t1 / 2));
533 
               end
534 
 
535 
            hold <= 1'b0 ;
536 
            clk <= 1'b0 ;
537 
            #(t0 / 4);
538 
 
539 
            hold <= 1'b1 ;
540 
            clk <= 1'b0 ;
541 
         end
542 
      endtask
543 
 
544 
      task waitc;
545 
         input t1;
546 
         time t1;
547 
         input t0;
548 
         time t0;
549 
 
550 
         input n;
551 
         integer n;
552 
         integer i;
553 
 
554 
         begin
555 
               for(i = 0; i <= (n - 1); i = i + 1)
556 
               begin
557 
                  clk <= 1'b0 ;
558 
                  #t0;
559 
                  clk <= 1'b1 ;
560 
                  #t1;
561 
               end
562 
         end
563 
      endtask
564 
 
565 
 
566 
      task rdsr;
567 
         input t1;
568 
         time t1;
569 
         input t0;
570 
         time t0;
571 
 
572 
         input n;
573 
         integer n;
574 
 
575 
         integer i;
576 
 
577 
         begin
578 
            cs_valid <= 1'b1 ;
579 
            clk <= 1'b0 ;
580 
            #t0;
581 
            cs_valid <= 1'b0 ;
582 
            clk <= 1'b0 ;
583 
            if (n == 1)
584 
            begin
585 
                  for(i = 0; i <= 15; i = i + 1)
586 
                  begin
587 
                     if ((i == 5) || (i == 7))
588 
                     begin
589 
                        din <= 1'b1 ;
590 
                     end
591 
                     else
592 
                     begin
593 
                        din <= 1'b0 ;
594 
                     end
595 
                     clk <= 1'b0 ;
596 
                     #t0;
597 
                     clk <= 1'b1 ;
598 
                     #t1;
599 
                  end
600 
            end
601 
            else
602 
            begin
603 
                  for(i = 0; i <= (8 * (n + 1) - 1); i = i + 1)
604 
                  begin
605 
                     if ((i == 5) || (i == 7))
606 
                     begin
607 
                        din <= 1'b1 ;
608 
                     end
609 
                     else
610 
                     begin
611 
                        din <= 1'b0 ;
612 
                     end
613 
                     clk <= 1'b0 ;
614 
                     #t0;
615 
                     clk <= 1'b1 ;
616 
                     #t1;
617 
                  end
618 
            end
619 
            clk <= 1'b0 ;
620 
            #t0;
621 
            cs_valid <= 1'b1 ;
622 
         end
623 
      endtask
624 
 
625 
 
626 
 
627 
 
628 
      task rdsr_11;
629 
         input t1;
630 
         time t1;
631 
         input t0;
632 
         time t0;
633 
 
634 
         input n;
635 
         integer n;
636 
 
637 
         integer i;
638 
 
639 
         begin
640 
            cs_valid <= 1'b1 ;
641 
            clk <= 1'b1 ;
642 
            #(t0/2);
643 
            cs_valid <= 1'b0 ;
644 
            #(t0/2);
645 
            clk <= 1'b0 ;
646 
            if (n == 1)
647 
            begin
648 
                  for(i = 0; i <= 15; i = i + 1)
649 
                  begin
650 
                     if ((i == 5) || (i == 7))
651 
                     begin
652 
                        din <= 1'b1 ;
653 
                     end
654 
                     else
655 
                     begin
656 
                        din <= 1'b0 ;
657 
                     end
658 
                     clk <= 1'b0 ;
659 
                     #t0;
660 
                     clk <= 1'b1 ;
661 
                     #t1;
662 
                  end
663 
            end
664 
            else
665 
            begin
666 
                  for(i = 0; i <= (8 * (n + 1) - 1); i = i + 1)
667 
                  begin
668 
                     if ((i == 5) || (i == 7))
669 
                     begin
670 
                        din <= 1'b1 ;
671 
                     end
672 
                     else
673 
                     begin
674 
                        din <= 1'b0 ;
675 
                     end
676 
                     clk <= 1'b0 ;
677 
                     #t0;
678 
                     clk <= 1'b1 ;
679 
                     #(t1/2);
680 
                  end
681 
            end
682 
            cs_valid <= 1'b1;
683 
            #(t1/2);
684 
            clk <= 1'b0 ;
685 
         end
686 
      endtask
687 
 
688 
 
689 
      task wrsr;
690 
         input t1;
691 
         time t1;
692 
         input t0;
693 
         time t0;
694 
 
695 
         input[(`NB_BIT_DATA-1):0] status;
696 
 
697 
         integer i;
698 
 
699 
         begin
700 
            cs_valid <= 1'b1 ;
701 
            clk <= 1'b0 ;
702 
            cs_valid <= 1'b0 ;
703 
            clk <= 1'b0 ;
704 
               for(i = 0; i <= 15; i = i + 1)
705 
               begin
706 
                  if (i == 7)
707 
                  begin
708 
                     din <= 1'b1 ;
709 
                  end
710 
                  else if ((i >= 8) && ((status[15 - i]) == 1'b1))
711 
                  begin
712 
                     din <= 1'b1 ;
713 
                  end
714 
                  else
715 
                  begin
716 
                     din <= 1'b0 ;
717 
                  end
718 
                  clk <= 1'b0 ;
719 
                  #t0;
720 
                  clk <= 1'b1 ;
721 
                  #t1;
722 
               end
723 
            clk <= 1'b0 ;
724 
            #t0;
725 
            cs_valid <= 1'b1 ;
726 
         end
727 
      endtask
728 
 
729 
 
730 
 
731 
      task wren_wc0;  // FOR DEBUG ONLY HC
732 
               input t1;
733 
               time t1;
734 
               input t0;
735 
               time t0;
736 
 
737 
               integer i;
738 
 
739 
               begin
740 
                  cs_valid <= 1'b1 ;
741 
                  clk <= 1'b0 ;
742 
                  #t0;
743 
                     for(i = 0; i <= 7; i = i + 1)
744 
                     begin
745 
                        if (i == 0)
746 
                        begin
747 
                           cs_valid <= 1'b0 ;
748 
                           din <= 1'b0 ;
749 
                        end
750 
                        if ((i == 5) || (i == 6))
751 
                        begin
752 
                           hard_protect <= 1'b0;
753 
                           din <= 1'b1 ;
754 
                        end
755 
                        else
756 
                        begin
757 
                           din <= 1'b0 ;
758 
                        end
759 
                        clk <= 1'b0 ;
760 
                        #t0;
761 
                        hard_protect <= 1'b1;
762 
                        clk <= 1'b1 ;
763 
                        #t1;
764 
                     end
765 
                  clk <= 1'b0 ;
766 
                  #t0;
767 
                  cs_valid <= 1'b1 ;
768 
               end
769 
      endtask
770 
 
771 
      task wrsr_wc0;  // FOR DEBUG ONLY HC
772 
               input t1;
773 
               time t1;
774 
               input t0;
775 
               time t0;
776 
 
777 
               input[(`NB_BIT_DATA-1):0] status;
778 
 
779 
               integer i;
780 
 
781 
               begin
782 
                  //hard_protect <=1'b0;
783 
                  cs_valid <= 1'b1 ;
784 
                  clk <= 1'b0 ;
785 
                  //#t0;
786 
                  hard_protect <=1'b1;
787 
                  #t0;
788 
                  cs_valid <= 1'b0 ;
789 
                  clk <= 1'b0 ;
790 
                     for(i = 0; i <= 15; i = i + 1)
791 
                     begin
792 
                        if (i == 2)
793 
                           begin
794 
                           // hard_protect <=1'b0;
795 
                           // din <= 1'b1 ;
796 
                           end
797 
                        if (i == 7)
798 
                           begin
799 
                           //hard_protect <=1'b0;
800 
                           din <= 1'b1 ;
801 
                           end
802 
                        else if ((i >= 8) && ((status[15 - i]) == 1'b1))
803 
                           begin
804 
                           //hard_protect <=1'b1;
805 
                           din <= 1'b1 ;
806 
                           end
807 
                        else
808 
                           begin
809 
                           din <= 1'b0 ;
810 
                           end
811 
                        clk <= 1'b0 ;
812 
                        #t0;
813 
                        clk <= 1'b1 ;
814 
                        #t1;
815 
                     end
816 
                  clk <= 1'b0 ;
817 
                  #t0;
818 
                  cs_valid <= 1'b1 ;
819 
 
820 
               end
821 
      endtask
822 
 
823 
 
824 
      task wren;
825 
         input t1;
826 
         time t1;
827 
         input t0;
828 
         time t0;
829 
 
830 
         integer i;
831 
 
832 
         begin
833 
            cs_valid <= 1'b1 ;
834 
            clk <= 1'b0 ;
835 
            #t0;
836 
               for(i = 0; i <= 7; i = i + 1)
837 
               begin
838 
                  if (i == 0)
839 
                  begin
840 
                     cs_valid <= 1'b0 ;
841 
                     din <= 1'b0 ;
842 
                  end
843 
                  if ((i == 5) || (i == 6))
844 
                  begin
845 
                     din <= 1'b1 ;
846 
                  end
847 
                  else
848 
                  begin
849 
                     din <= 1'b0 ;
850 
                  end
851 
                  clk <= 1'b0 ;
852 
                  #t0;
853 
                  clk <= 1'b1 ;
854 
                  #t1;
855 
               end
856 
            clk <= 1'b0 ;
857 
            #t0;
858 
            cs_valid <= 1'b1 ;
859 
         end
860 
      endtask
861 
 
862 
 
863 
 
864 
 
865 
 
866 
 
867 
 
868 
 
869 
      task wrdi;
870 
         input t1;
871 
         time t1;
872 
         input t0;
873 
         time t0;
874 
 
875 
         integer i;
876 
 
877 
         begin
878 
            cs_valid <= 1'b1 ;
879 
            clk <= 1'b0 ;
880 
            #t0;
881 
            cs_valid <= 1'b0 ;
882 
            clk <= 1'b0 ;
883 
               for(i = 0; i <= 7; i = i + 1)
884 
               begin
885 
                  if (i == 5)
886 
                  begin
887 
                     din <= 1'b1 ;
888 
                  end
889 
                  else
890 
                  begin
891 
                     din <= 1'b0 ;
892 
                  end
893 
                  clk <= 1'b0 ;
894 
                  #t0;
895 
                  clk <= 1'b1 ;
896 
                  #t1;
897 
               end
898 
            clk <= 1'b0 ;
899 
            #t0;
900 
            cs_valid <= 1'b1 ;
901 
         end
902 
      endtask
903 
 
904 
 
905 
      task read;
906 
         input t1;
907 
         time t1;
908 
         input t0;
909 
         time t0;
910 
 
911 
         input[(`NB_BIT_ADD_MEM-1):0] address;
912 
         input n;
913 
         integer n;
914 
 
915 
         integer i;
916 
 
917 
         begin
918 
            cs_valid <= 1'b1 ;
919 
            clk <= 1'b0 ;
920 
            #t0;
921 
            cs_valid <= 1'b0 ;
922 
            clk <= 1'b0 ;
923 
               for(i = 0; i <= 7; i = i + 1)
924 
               begin
925 
                  if (i == 0)
926 
                  begin
927 
                  end
928 
                  if ((i == 6) || (i == 7))
929 
                  begin
930 
                     din <= 1'b1 ;
931 
                  end
932 
                  else
933 
                  begin
934 
                     din <= 1'b0 ;
935 
                  end
936 
                  clk <= 1'b0 ;
937 
                  #t0;
938 
                  clk <= 1'b1 ;
939 
                  #t1;
940 
               end
941 
               for(i = 0; i <= 23; i = i + 1)
942 
               begin
943 
                  if ((address[23 - i]) == 1'b1)
944 
                  begin
945 
                     din <= 1'b1 ;
946 
                  end
947 
                  else
948 
                  begin
949 
                     din <= 1'b0 ;
950 
                  end
951 
                  clk <= 1'b0 ;
952 
                  #t0;
953 
                  clk <= 1'b1 ;
954 
                  #t1;
955 
               end
956 
               for(i = 0; i <= (8 * n - 1); i = i + 1)
957 
               begin
958 
                  if (i == 0)
959 
                  begin
960 
                     din <= 1'b0 ;
961 
                  end
962 
                  clk <= 1'b0 ;
963 
                  #t0;
964 
                  clk <= 1'b1 ;
965 
                  #t1;
966 
               end
967 
            clk <= 1'b0 ;
968 
            #t0;
969 
            cs_valid <= 1'b1 ;
970 
         end
971 
      endtask
972 
 
973 
 
974 
      task fast_read;
975 
         input t1;
976 
         time t1;
977 
         input t0;
978 
         time t0;
979 
 
980 
         input[(`NB_BIT_ADD_MEM-1):0] address;
981 
         input n;
982 
         integer n;
983 
 
984 
         integer i;
985 
 
986 
         begin
987 
            cs_valid <= 1'b1 ;
988 
            clk <= 1'b0 ;
989 
            #t0;
990 
            cs_valid <= 1'b0 ;
991 
            clk <= 1'b0 ;
992 
               for(i = 0; i <= 7; i = i + 1)
993 
               begin
994 
                  if (i == 0)
995 
                  begin
996 
                  end
997 
                  if ((i == 4) || (i == 6) || (i == 7))
998 
                  begin
999 
                     din <= 1'b1 ;
1000 
                  end
1001 
                  else
1002 
                  begin
1003 
                     din <= 1'b0 ;
1004 
                  end
1005 
                  clk <= 1'b0 ;
1006 
                  #t0;
1007 
                  clk <= 1'b1 ;
1008 
                  #t1;
1009 
               end
1010 
               for(i = 0; i <= 23; i = i + 1)
1011 
               begin
1012 
                  if ((address[23 - i]) == 1'b1)
1013 
                  begin
1014 
                     din <= 1'b1 ;
1015 
                  end
1016 
                  else
1017 
                  begin
1018 
                     din <= 1'b0 ;
1019 
                  end
1020 
                  clk <= 1'b0 ;
1021 
                  #t0;
1022 
                  clk <= 1'b1 ;
1023 
                  #t1;
1024 
               end
1025 
               for(i = 0; i <= 7; i = i + 1)
1026 
               begin
1027 
                  din <= 1'b0 ;
1028 
                  clk <= 1'b0 ;
1029 
                  #t0;
1030 
                  clk <= 1'b1 ;
1031 
                  #t1;
1032 
               end
1033 
               for(i = 0; i <= (8 * n - 1); i = i + 1)
1034 
               begin
1035 
                  if (i == 0)
1036 
                  begin
1037 
                     din <= 1'b0 ;
1038 
                  end
1039 
                  clk <= 1'b0 ;
1040 
                  #t0;
1041 
                  clk <= 1'b1 ;
1042 
                  #t1;
1043 
               end
1044 
            clk <= 1'b0 ;
1045 
            #t0;
1046 
            cs_valid <= 1'b1 ;
1047 
         end
1048 
      endtask
1049 
 
1050 
 
1051 
      task fast_read_no_select ;
1052 
         input t1;
1053 
         time t1;
1054 
         input t0;
1055 
         time t0;
1056 
 
1057 
         input[(`NB_BIT_ADD_MEM-1):0] address;
1058 
         input n;
1059 
         integer n;
1060 
 
1061 
         integer i;
1062 
 
1063 
         begin
1064 
            cs_valid <= 1'b1 ;
1065 
            clk <= 1'b0 ;
1066 
            #t0;
1067 
            cs_valid <= 1'b1 ;
1068 
            clk <= 1'b0 ;
1069 
               for(i = 0; i <= 7; i = i + 1)
1070 
               begin
1071 
                  if (i == 0)
1072 
                  begin
1073 
                  end
1074 
                  if ((i == 4) || (i == 6) || (i == 7))
1075 
                  begin
1076 
                     din <= 1'b1 ;
1077 
                  end
1078 
                  else
1079 
                  begin
1080 
                     din <= 1'b0 ;
1081 
                  end
1082 
                  clk <= 1'b0 ;
1083 
                  #t0;
1084 
                  clk <= 1'b1 ;
1085 
                  #t1;
1086 
               end
1087 
               for(i = 0; i <= 23; i = i + 1)
1088 
               begin
1089 
                  if ((address[23 - i]) == 1'b1)
1090 
                  begin
1091 
                     din <= 1'b1 ;
1092 
                  end
1093 
                  else
1094 
                  begin
1095 
                     din <= 1'b0 ;
1096 
                  end
1097 
                  clk <= 1'b0 ;
1098 
                  #t0;
1099 
                  clk <= 1'b1 ;
1100 
                  #t1;
1101 
               end
1102 
               for(i = 0; i <= 7; i = i + 1)
1103 
               begin
1104 
                  din <= 1'b0 ;
1105 
                  clk <= 1'b0 ;
1106 
                  #t0;
1107 
                  clk <= 1'b1 ;
1108 
                  #t1;
1109 
               end
1110 
               for(i = 0; i <= (8 * n - 1); i = i + 1)
1111 
               begin
1112 
                  if (i == 0)
1113 
                  begin
1114 
                     din <= 1'b0 ;
1115 
                  end
1116 
                  clk <= 1'b0 ;
1117 
                  #t0;
1118 
                  clk <= 1'b1 ;
1119 
                  #t1;
1120 
               end
1121 
            clk <= 1'b0 ;
1122 
            #t0;
1123 
            cs_valid <= 0'b1 ;
1124 
         end
1125 
      endtask
1126 
 
1127 
 
1128 
 
1129 
      task pp;
1130 
         input t1;
1131 
         time t1;
1132 
         input t0;
1133 
         time t0;
1134 
 
1135 
         input[(`NB_BIT_ADD_MEM-1):0] address;
1136 
         input[(`NB_BIT_DATA-1):0] data;
1137 
         input n;
1138 
         integer n;
1139 
 
1140 
         integer i;
1141 
 
1142 
         begin
1143 
            cs_valid <= 1'b1 ;
1144 
            clk <= 1'b0 ;
1145 
            #t0;
1146 
            cs_valid <= 1'b0 ;
1147 
            clk <= 1'b0 ;
1148 
               for(i = 0; i <= 7; i = i + 1)
1149 
               begin
1150 
                  // send  Instruction Byte
1151 
                  if (i == 6)
1152 
                  begin
1153 
                     din <= 1'b1 ;
1154 
                  end
1155 
                  else
1156 
                  begin
1157 
                     din <= 1'b0 ;
1158 
                  end
1159 
                  clk <= 1'b0 ;
1160 
                  #t0;
1161 
                  clk <= 1'b1 ;
1162 
                  #t1;
1163 
               end
1164 
               for(i = 0; i <= 23; i = i + 1)
1165 
               begin
1166 
                  // send Address Byte of the Page to Program
1167 
                  if ((address[23 - i]) == 1'b1)
1168 
                  begin
1169 
                     din <= 1'b1 ;
1170 
                  end
1171 
                  else
1172 
                  begin
1173 
                     din <= 1'b0 ;
1174 
                  end
1175 
                  clk <= 1'b0 ;
1176 
                  #t0;
1177 
                  clk <= 1'b1 ;
1178 
                  #t1;
1179 
               end
1180 
               for(i = 0; i <= (8 * n - 1); i = i + 1)
1181 
               begin
1182 
                  // send Data Bytes to Program
1183 
                  if (i > 2047)
1184 
                  begin
1185 
                     din <= 1'b0 ;
1186 
                  end
1187 
                  else if ((i % 8 == 0) && (i != (8 * n)) && ((data[7]) == 1'b1))
1188 
                  begin
1189 
                     din <= 1'b1 ;
1190 
                  end
1191 
                  else if ((i % 8 == 1) && ((data[6]) == 1'b1))
1192 
                  begin
1193 
                     din <= 1'b1 ;
1194 
                  end
1195 
                  else if ((i % 8 == 2) && ((data[5]) == 1'b1))
1196 
                  begin
1197 
                     din <= 1'b1 ;
1198 
                  end
1199 
                  else if ((i % 8 == 3) && ((data[4]) == 1'b1))
1200 
                  begin
1201 
                     din <= 1'b1 ;
1202 
                  end
1203 
                  else if ((i % 8 == 4) && ((data[3]) == 1'b1))
1204 
                  begin
1205 
                     din <= 1'b1 ;
1206 
                  end
1207 
                  else if ((i % 8 == 5) && ((data[2]) == 1'b1))
1208 
                  begin
1209 
                     din <= 1'b1 ;
1210 
                  end
1211 
                  else if ((i % 8 == 6) && ((data[1]) == 1'b1))
1212 
                  begin
1213 
                     din <= 1'b1 ;
1214 
                  end
1215 
                  else if ((i % 8 == 7) && ((data[0]) == 1'b1))
1216 
                  begin
1217 
                     din <= 1'b1 ;
1218 
                  end
1219 
                  else
1220 
                  begin
1221 
                     din <= 1'b0 ;
1222 
                  end
1223 
                  clk <= 1'b0 ;
1224 
                  #t0;
1225 
                  clk <= 1'b1 ;
1226 
                  #t1;
1227 
               end
1228 
            clk <= 1'b0 ;
1229 
            #t0;
1230 
            cs_valid <= 1'b1 ;
1231 
         end
1232 
      endtask
1233 
 
1234 
      task se;
1235 
         input t1;
1236 
         time t1;
1237 
         input t0;
1238 
         time t0;
1239 
 
1240 
         input[(`NB_BIT_ADD_MEM-1):0] address;
1241 
 
1242 
         integer i;
1243 
 
1244 
         begin
1245 
            cs_valid <= 1'b1 ;
1246 
            clk <= 1'b0 ;
1247 
            #t0;
1248 
            cs_valid <= 1'b0 ;
1249 
            clk <= 1'b0 ;
1250 
               for(i = 0; i <= 7; i = i + 1)
1251 
               begin
1252 
                  if (i == 0 || i == 1 || i == 3 || i == 4)
1253 
                  begin
1254 
                     din <= 1'b1 ;
1255 
                  end
1256 
                  else
1257 
                  begin
1258 
                     din <= 1'b0 ;
1259 
                  end
1260 
                  clk <= 1'b0 ;
1261 
                  #t0;
1262 
                  clk <= 1'b1 ;
1263 
                  #t1;
1264 
               end
1265 
               for(i = 0; i <= 23; i = i + 1)
1266 
               begin
1267 
                  if (((address[23 - i]) == 1'b1))
1268 
                  begin
1269 
                     din <= 1'b1 ;
1270 
                  end
1271 
                  else
1272 
                  begin
1273 
                     din <= 1'b0 ;
1274 
                  end
1275 
                  clk <= 1'b0 ;
1276 
                  #t0;
1277 
                  clk <= 1'b1 ;
1278 
                  #t1;
1279 
               end
1280 
            clk <= 1'b0 ;
1281 
            #t0;
1282 
            cs_valid <= 1'b1 ;
1283 
         end
1284 
      endtask
1285 
 
1286 
 
1287 
      task be;
1288 
         input t1;
1289 
         time t1;
1290 
         input t0;
1291 
         time t0;
1292 
 
1293 
         integer i;
1294 
 
1295 
         begin
1296 
            cs_valid <= 1'b1 ;
1297 
            #t0;
1298 
            cs_valid <= 1'b0 ;
1299 
               for(i = 0; i <= 7; i = i + 1)
1300 
               begin
1301 
                  if (i == 0 || i == 1 || i == 5 || i == 6 || i == 7)
1302 
                  begin
1303 
                     din <= 1'b1 ;
1304 
                  end
1305 
                  else
1306 
                  begin
1307 
                     din <= 1'b0 ;
1308 
                  end
1309 
                  clk <= 1'b0 ;
1310 
                  #t0;
1311 
                  clk <= 1'b1 ;
1312 
                  #t1;
1313 
               end
1314 
            clk <= 1'b0 ;
1315 
            #t0;
1316 
            cs_valid <= 1'b1 ;
1317 
         end
1318 
      endtask
1319 
 
1320 
 
1321 
      task dp;
1322 
         input t1;
1323 
         time t1;
1324 
         input t0;
1325 
         time t0;
1326 
 
1327 
         integer i;
1328 
 
1329 
         begin
1330 
            cs_valid <= 1'b1 ;
1331 
            clk <= 1'b0 ;
1332 
            #t0;
1333 
            cs_valid <= 1'b0 ;
1334 
               for(i = 0; i <= 7; i = i + 1)
1335 
               begin
1336 
                  if (i == 1 || i == 5 || i == 6)
1337 
                  begin
1338 
                     din <= 1'b0 ;
1339 
                  end
1340 
                  else
1341 
                  begin
1342 
                     din <= 1'b1 ;
1343 
                  end
1344 
                  clk <= 1'b0 ;
1345 
                  #t0;
1346 
                  clk <= 1'b1 ;
1347 
                  #t1;
1348 
               end
1349 
            clk <= 1'b0 ;
1350 
            #t0;
1351 
            cs_valid <= 1'b1 ;
1352 
         end
1353 
      endtask
1354 
 
1355 
 
1356 
      task res;
1357 
         input t1;
1358 
         time t1;
1359 
         input t0;
1360 
         time t0;
1361 
 
1362 
         integer i;
1363 
 
1364 
         begin
1365 
            cs_valid <= 1'b1 ;
1366 
            clk <= 1'b0 ;
1367 
            #t0;
1368 
            cs_valid <= 1'b0 ;
1369 
               for(i = 0; i <= 7; i = i + 1)
1370 
               begin
1371 
                  if (i == 1 || i == 3 || i == 5)
1372 
                  begin
1373 
                     din <= 1'b0 ;
1374 
                  end
1375 
                  else
1376 
                  begin
1377 
                     din <= 1'b1 ;
1378 
                  end
1379 
                  clk <= 1'b0 ;
1380 
                  #t0;
1381 
                  clk <= 1'b1 ;
1382 
                  #t1;
1383 
               end
1384 
            clk <= 1'b0 ;
1385 
            #t0;
1386 
            cs_valid <= 1'b1 ;
1387 
         end
1388 
      endtask
1389 
 
1390 
 
1391 
      task read_es;
1392 
         input t1;
1393 
         time t1;
1394 
         input t0;
1395 
         time t0;
1396 
 
1397 
         integer i;
1398 
 
1399 
         begin
1400 
            cs_valid <= 1'b1 ;
1401 
            clk <= 1'b0 ;
1402 
            #t0;
1403 
            cs_valid <= 1'b0 ;
1404 
               for(i = 0; i <= 7; i = i + 1)
1405 
               begin
1406 
                  if (i == 1 || i == 3 || i == 5)
1407 
                  begin
1408 
                     din <= 1'b0 ;
1409 
                  end
1410 
                  else
1411 
                  begin
1412 
                     din <= 1'b1 ;
1413 
                  end
1414 
                  clk <= 1'b0 ;
1415 
                  #t0;
1416 
                  clk <= 1'b1 ;
1417 
                  #t1;
1418 
               end
1419 
               for(i = 0; i <= 31; i = i + 1)
1420 
               begin
1421 
                  din <= 1'b0 ;
1422 
                  clk <= 1'b0 ;
1423 
                  #t0;
1424 
                  clk <= 1'b1 ;
1425 
                  #t1;
1426 
               end
1427 
            clk <= 1'b0 ;
1428 
            #t0;
1429 
            cs_valid <= 1'b1 ;
1430 
         end
1431 
      endtask
1432 
 
1433 
            task rdid;
1434 
               input t1;
1435 
               time t1;
1436 
               input t0;
1437 
               time t0;
1438 
 
1439 
               input n;
1440 
               integer n;
1441 
 
1442 
               integer i;
1443 
 
1444 
               begin
1445 
                  cs_valid <= 1'b1 ;
1446 
                  clk <= 1'b0 ;
1447 
                  #t0;
1448 
                  cs_valid <= 1'b0 ;
1449 
                  clk <= 1'b0 ;
1450 
                     for(i = 0; i <= 7; i = i + 1)
1451 
                            begin
1452 
                            if ((i == 1) || (i == 2))
1453 
                                begin
1454 
                                din <= 1'b0 ;
1455 
                                end
1456 
                             else din <= 1'b1 ;
1457 
                             clk <= 1'b0 ;
1458 
                             #t0;
1459 
                             clk <= 1'b1 ;
1460 
                             #t1;
1461 
                             end
1462 
                     for(i = 0; i <= ( n - 1); i = i + 1)
1463 
                     begin
1464 
                        if (i == 0)
1465 
                           begin
1466 
                           din <= 1'b0 ;
1467 
                           end
1468 
                        clk <= 1'b0 ;
1469 
                        #t0;
1470 
                        clk <= 1'b1 ;
1471 
                        #t1;
1472 
                     end
1473 
                  clk <= 1'b0 ;
1474 
                  #t0;
1475 
                  cs_valid <= 1'b1 ;
1476 
               end
1477 
      endtask
1478 
 
1479 
endmodule
1480 
 
1481 
 

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