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dinesha |
// Author: Mehdi SEBBANE
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// May 2002
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// Verilog model
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// project: M25P20 25 MHz,
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// release: 1.4.1
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// These Verilog HDL models are provided "as is" without warranty
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// of any kind, included but not limited to, implied warranty
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// of merchantability and fitness for a particular purpose.
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`timescale 1ns/1ns
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`define SIZE 2097152 // 2Mbit
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`define PLENGTH 256 // page length
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`define SSIZE 524288 // Sector size
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`define NB_BPI 2 // number of BPi bits
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`define SIGNATURE 8'b00010001 // electronic signature
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`define BIT_TO_CODE_MEM 18 // number of bit to code a 2Mbits memory
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`define LSB_TO_CODE_PAGE 8 // number of bit to code a PLENGTH page
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`define NB_BIT_ADD_MEM 24
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`define NB_BIT_ADD 8
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`define NB_BIT_DATA 8
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`define TOP_MEM (`SIZE/`NB_BIT_DATA)-1
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`define MASK_SECTOR 24'hFF0000 // anded with address to find first sector adress to erase
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`define TRUE 1'b1
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`define FALSE 1'b0
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`define TC 40 // Minimum Clock period
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`define TR 50 // Minimum Clock period for read instruction
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`define TSLCH 10 // notS active setup time (relative to C)
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`define TCHSL 10 // notS not active hold time
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`define TCH 18 // Clock high time
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`define TCL 18 // Clock low time
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`define TDVCH 5 // Data in Setup Time
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`define TCHDX 5 // Data in Hold Time
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`define TCHSH 10 // notS active hold time (relative to C)
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`define TSHCH 10 // notS not active setup time (relative to C)
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`define TSHSL 100 // /S deselect time
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`define TSHQZ 15 // Output disable Time
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`define TCLQV 15 // clock low to output valid
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`define THLCH 10 // NotHold active setup time
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`define TCHHH 10 // NotHold not active hold time
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`define THHCH 10 // NotHold not active setup time
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`define TCHHL 10 // NotHold active hold time
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`define THHQX 15 // NotHold high to Output Low-Z
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`define THLQZ 20 // NotHold low to Output High-Z
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`define TDP 3000 // notS high to deep power down mode
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`define TRES1 3000 // notS high to Stand-By power mode w-o ID Read
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`define TRES2 1800 // notS high to Stand-By power mode with ID Read
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//`define TW 15000000 // write status register cycle time (15ms)
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//`define TPP 5000000 // page program cycle time (5ms)
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//`define TSE 3000000000 // sector erase cycle time (3s)
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//`define TBE 6000000000 // bulk erase cycle time (6s)
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`define TW 15000 // write status register cycle time (.015ms)
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`define TPP 5000 // page program cycle time (.005ms)
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`define TSE 30000 // sector erase cycle time (.00003s)
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`define TBE 60000 // bulk erase cycle time (.00006s)
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