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URL https://opencores.org/ocsvn/uart2spi/uart2spi/trunk

Subversion Repositories uart2spi

[/] [uart2spi/] [trunk/] [verif/] [run/] [run_modelsim] - Blame information for rev 3

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Line No. Rev Author Line
1 3 dinesha
#!/bin/csh -f
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#
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# test for uart
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#
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echo " Compiling with MODELSIM "
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if(! -e work) then
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   vlib work
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endif
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vlog -work work  +define+SFLASH_SPDUP \
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+incdir+../models/st_m25p16 \
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+incdir+../tb  \
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./time_scale.v \
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../../rtl/top/top.v \
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../../rtl/uart_core/uart_core.v \
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../../rtl/uart_core/clk_ctl.v \
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../../rtl/uart_core/uart_rxfsm.v \
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../../rtl/uart_core/uart_txfsm.v \
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../../rtl/msg_hand/uart_msg_handler.v \
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../../rtl/spi/spi_core.v  \
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../../rtl/spi/spi_ctl.v  \
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../../rtl/spi/spi_if.v \
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../../rtl/spi/spi_cfg.v \
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../../rtl/lib/registers.v \
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../tb/tb_top.v  \
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../models/st_m25p16/acdc_check.v  \
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../models/st_m25p16/internal_logic.v  \
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../models/st_m25p16/memory_access.v  \
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../models/st_m25p16/M25p16.v \
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../tb/uart_agent.v  \
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-l ../log/compile_modelsim.log
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vsim -do modelsim.do -c tb_top | tee  ../log/run_modelsim.log

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