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[/] [uart2spi/] [trunk/] [verif/] [tb/] [uart_agent.v] - Blame information for rev 3

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`timescale  1ns/1ps
 
module uart_agent (
        test_clk,
        sin,
        dsr_n,
        cts_n,
        dcd_n,
 
        sout,
        dtr_n,
        rts_n,
        out1_n,
        out2_n);
 
input   test_clk;
output  sin;
output  dsr_n;
output  cts_n;
output  dcd_n;
 
input   sout;
input   dtr_n;
input   rts_n;
input   out1_n;
input   out2_n;
 
event   uart_read_done, uart_write_done;
event   error_detected,uart_parity_error, uart_stop_error1, uart_stop_error2;
event   uart_timeout_error;
event   abort;
 
reg [15:0] rx_count;
reg [15:0] tx_count;
reg [15:0] par_err_count;
reg [15:0] stop_err1_cnt;
reg [15:0] stop_err2_cnt;
reg [15:0] timeout_err_cnt;
reg [15:0] err_cnt;
 
reg        sin, read, write;
reg        dcd_n;
reg        dsr_n, cts_n;
wire       test_rx_clk;
reg        test_tx_clk;
reg        stop_err_check;
 
integer timeout_count;
integer data_bit_number;
reg [2:0] clk_count;
 
reg      error_ind; // 1 indicate error
 
initial
begin
        sin = 1'b1;
        dsr_n = 1'b1;
        cts_n = 1'b1;
        dcd_n = 1'b1;
        test_tx_clk = 0;
        clk_count = 0;
        stop_err_check = 0;
  error_ind = 0;
end
 
always @(posedge test_clk)
begin
        if (clk_count == 3'h0)
                test_tx_clk = ~test_tx_clk;
 
        clk_count = clk_count + 1;
end
assign test_rx_clk = ~test_tx_clk;
 
always @(posedge test_clk)
begin
        timeout_count = timeout_count + 1;
        if (timeout_count == (control_setup.maxtime * 16))
                -> abort;
end
 
always @uart_read_done
        rx_count = rx_count + 1;
 
always @uart_write_done
        tx_count = tx_count + 1;
 
always @uart_parity_error begin
  error_ind = 1;
        par_err_count = par_err_count + 1;
end
 
always @uart_stop_error1 begin
  error_ind = 1;
        stop_err1_cnt = stop_err1_cnt + 1;
end
 
always @uart_stop_error2 begin
  error_ind = 1;
        stop_err2_cnt = stop_err2_cnt + 1;
end
 
always @uart_timeout_error begin
  error_ind = 1;
        timeout_err_cnt = timeout_err_cnt + 1;
end
 
 
always @error_detected begin
  error_ind = 1;
        err_cnt = err_cnt + 1;
end
 
 
////////////////////////////////////////////////////////////////////////////////
task uart_init;
begin
  read = 0;
  write = 0;
        tx_count = 0;
        rx_count = 0;
  stop_err_check = 0;
  par_err_count = 0;
  stop_err1_cnt = 0;
  stop_err2_cnt = 0;
  timeout_err_cnt = 0;
  err_cnt = 0;
 
end
endtask
 
 
////////////////////////////////////////////////////////////////////////////////
task read_char_chk;
input   expected_data;
 
integer i;
reg     [7:0] expected_data;
reg     [7:0] data;
reg     parity;
 
begin
        data <= 8'h0;
        parity <= 1;
        timeout_count = 0;
 
fork
   begin : loop_1
        @(abort)
         $display (">>>>>  Exceed time limit, uart no responce.\n");
         ->uart_timeout_error;
         disable loop_2;
   end
 
   begin : loop_2
 
// start cycle
        @(negedge sout)
         disable loop_1;
         read <= 1;
 
// data cycle
        @(posedge test_rx_clk);
         for (i = 0; i < data_bit_number; i = i + 1)
          begin
            @(posedge test_rx_clk)
            data[i] <=  sout;
            parity <= parity ^ sout;
          end
 
// parity cycle
        if(control_setup.parity_en)
        begin
          @(posedge test_rx_clk);
          if ((control_setup.even_odd_parity && (sout == parity)) ||
             (!control_setup.even_odd_parity && (sout != parity)))
             begin
                $display (">>>>>  Parity Error");
                -> error_detected;
                -> uart_parity_error;
             end
        end
 
// stop cycle 1
        @(posedge test_rx_clk);
          if (!sout)
             begin
                $display (">>>>>  Stop signal 1 Error");
                -> error_detected;
                -> uart_stop_error1;
             end
 
// stop cycle 2
        if (control_setup.stop_bit_number)
        begin
              @(posedge test_rx_clk);   // stop cycle 2
                if (!sout)
                  begin
                    $display (">>>>>  Stop signal 2 Error");
                    -> error_detected;
                    -> uart_stop_error2;
                  end
        end
 
/*      Who Cares
// the stop bits transmitted is one and a half if it is 5-bit
        if (data_bit_number == 5)
        begin
                @(posedge test_rx_clk); // stop cycle for 5-bit/per char
                if (!sout)
                  begin
                    $display (">>>>>  Stop signal 2 Error (5-Bit)");
                    -> error_detected;
                    -> uart_stop_error2;
                  end
        end
        else
*/
 
// wait another half cycle for tx_done signal
                @(negedge test_rx_clk);
        read <= 0;
        -> uart_read_done;
 
        if (expected_data != data)
        begin
                $display ("Error! Data return is %h, expecting %h", data, expected_data);
                -> error_detected;
        end
        else
                $display ("(%m) Data match  %h", expected_data);
 
        $display ("... Read Data from UART done cnt :%d...",rx_count +1);
   end
join
 
end
 
endtask
 
////////////////////////////////////////////////////////////////////////////////
task read_char;
output [7:0]     rxd_data;
output          timeout; // 1-> timeout
integer i;
reg     [7:0] rxd_data;
reg     [7:0] data;
reg     parity;
 
begin
        data <= 8'h0;
        parity <= 1;
        timeout_count = 0;
        timeout = 0;
 
fork
   begin : loop_1
        @(abort)
         //$display (">>>>>  Exceed time limit, uart no responce.\n");
         //->uart_timeout_error;
          timeout = 1;
         disable loop_2;
   end
 
   begin : loop_2
 
// start cycle
        @(negedge sout)
         disable loop_1;
         read <= 1;
 
// data cycle
        @(posedge test_rx_clk);
         for (i = 0; i < data_bit_number; i = i + 1)
          begin
            @(posedge test_rx_clk)
            data[i] <=  sout;
            parity <= parity ^ sout;
          end
 
// parity cycle
        if(control_setup.parity_en)
        begin
          @(posedge test_rx_clk);
          if ((control_setup.even_odd_parity && (sout == parity)) ||
             (!control_setup.even_odd_parity && (sout != parity)))
             begin
                $display (">>>>>  Parity Error");
                -> error_detected;
                -> uart_parity_error;
             end
        end
 
// stop cycle 1
        @(posedge test_rx_clk);
          if (!sout)
             begin
                $display (">>>>>  Stop signal 1 Error");
                -> error_detected;
                -> uart_stop_error1;
             end
 
// stop cycle 2
        if (control_setup.stop_bit_number)
        begin
              @(posedge test_rx_clk);   // stop cycle 2
                if (!sout)
                  begin
                    $display (">>>>>  Stop signal 2 Error");
                    -> error_detected;
                    -> uart_stop_error2;
                  end
        end
 
// wait another half cycle for tx_done signal
                @(negedge test_rx_clk);
        read <= 0;
        -> uart_read_done;
 
//        $display ("(%m) Received Data  %c", data);
//      $display ("... Read Data from UART done cnt :%d...",rx_count +1);
        $write ("%c",data);
        rxd_data = data;
   end
join
 
end
 
endtask
 
////////////////////////////////////////////////////////////////////////////////
task write_char;
input [7:0] data;
 
integer i;
reg parity;     // 0: odd parity, 1: even parity
 
begin
        parity <=  #1 1;
 
// start cycle
        @(posedge test_tx_clk)
         begin
                sin <= #1 0;
                write <= #1 1;
         end
 
// data cycle
        begin
           for (i = 0; i < data_bit_number; i = i + 1)
           begin
                @(posedge test_tx_clk)
                    sin <= #1 data[i];
                parity <= parity ^ data[i];
           end
        end
 
// parity cycle
        if (control_setup.parity_en)
        begin
                @(posedge test_tx_clk)
                        sin <= #1
                                control_setup.even_odd_parity ? !parity : parity;
        end
 
// stop cycle 1
        @(posedge test_tx_clk)
                sin <= #1 stop_err_check ? 0 : 1;
 
// stop cycle 2
        @(posedge test_tx_clk);
                sin <= #1 1;
        if (data_bit_number == 5)
                @(negedge test_tx_clk);
        else if (control_setup.stop_bit_number)
                @(posedge test_tx_clk);
 
        write <= #1 0;
        // $display ("... Write data %h to UART done cnt : %d ...\n", data,tx_count+1);
        $write ("%c",data);
        -> uart_write_done;
end
endtask
 
 
////////////////////////////////////////////////////////////////////////////////
task control_setup;
input     [1:0] data_bit_set;
input           stop_bit_number;
input           parity_en;
input           even_odd_parity;
input    [15:0] maxtime;
input           fifo_enable;
 
begin
        data_bit_number = data_bit_set + 5;
end
endtask
 
 
////////////////////////////////////////////////////////////////////////////////
task report_status;
output  [15:0] rx_nu;
output  [15:0] tx_nu;
begin
        $display ("-------------------- Reporting Configuration --------------------");
        $display ("     Data bit number setting is : %0d", data_bit_number);
        $display ("     Stop bit number setting is : %0d", control_setup.stop_bit_number + 1);
        if (control_setup.parity_en)
        $display ("     Parity is enable");
        else
        $display ("     Parity is disable");
 
        if (control_setup.even_odd_parity)
        $display ("     Even parity setting");
        else
        $display ("     Odd parity setting");
 
        if (control_setup.fifo_enable)
        $display ("     FIFO mode is enable");
        else
        $display ("     FIFO mode is disable");
 
        $display ("-----------------------------------------------------------------");
 
        $display ("-------------------- Reporting Status --------------------\n");
        $display ("     Number of character received is : %d", rx_count);
        $display ("     Number of character sent     is : %d", tx_count);
        $display ("     Number of parity error rxd   is : %d", par_err_count);
        $display ("     Number of stop1  error rxd   is : %d", stop_err1_cnt);
        $display ("     Number of stop2  error rxd   is : %d", stop_err2_cnt);
        $display ("     Number of timeout error      is : %d", timeout_err_cnt);
        $display ("     Number of error              is : %d", err_cnt);
        $display ("-----------------------------------------------------------------");
 
        rx_nu = rx_count;
        tx_nu = tx_count;
end
endtask
 
 
////////////////////////////////////////////////////////////////////////////////
endmodule

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Subversion Repositories uart2spi

[/] [uart2spi/] [trunk/] [verif/] [tb/] [uart_agent.v] - Blame information for rev 3

Line No.	Rev	Author	Line
1	3	dinesha
2			`timescale 1ns/1ps
3
4			`module uart_agent (`
5			`test_clk,`
6			`sin,`
7			`dsr_n,`
8			`cts_n,`
9			`dcd_n,`
10
11			`sout,`
12			`dtr_n,`
13			`rts_n,`
14			`out1_n,`
15			`out2_n);`
16
17			`input test_clk;`
18			`output sin;`
19			`output dsr_n;`
20			`output cts_n;`
21			`output dcd_n;`
22
23			`input sout;`
24			`input dtr_n;`
25			`input rts_n;`
26			`input out1_n;`
27			`input out2_n;`
28
29			`event uart_read_done, uart_write_done;`
30			`event error_detected,uart_parity_error, uart_stop_error1, uart_stop_error2;`
31			`event uart_timeout_error;`
32			`event abort;`
33
34			`reg [15:0] rx_count;`
35			`reg [15:0] tx_count;`
36			`reg [15:0] par_err_count;`
37			`reg [15:0] stop_err1_cnt;`
38			`reg [15:0] stop_err2_cnt;`
39			`reg [15:0] timeout_err_cnt;`
40			`reg [15:0] err_cnt;`
41
42			`reg sin, read, write;`
43			`reg dcd_n;`
44			`reg dsr_n, cts_n;`
45			`wire test_rx_clk;`
46			`reg test_tx_clk;`
47			`reg stop_err_check;`
48
49			`integer timeout_count;`
50			`integer data_bit_number;`
51			`reg [2:0] clk_count;`
52
53			`reg error_ind; // 1 indicate error`
54
55			`initial`
56			`begin`
57			`sin = 1'b1;`
58			`dsr_n = 1'b1;`
59			`cts_n = 1'b1;`
60			`dcd_n = 1'b1;`
61			`test_tx_clk = 0;`
62			`clk_count = 0;`
63			`stop_err_check = 0;`
64			`error_ind = 0;`
65			`end`
66
67			`always @(posedge test_clk)`
68			`begin`
69			`if (clk_count == 3'h0)`
70			`test_tx_clk = ~test_tx_clk;`
71
72			`clk_count = clk_count + 1;`
73			`end`
74			`assign test_rx_clk = ~test_tx_clk;`
75
76			`always @(posedge test_clk)`
77			`begin`
78			`timeout_count = timeout_count + 1;`
79			`if (timeout_count == (control_setup.maxtime * 16))`
80			`-> abort;`
81			`end`
82
83			`always @uart_read_done`
84			`rx_count = rx_count + 1;`
85
86			`always @uart_write_done`
87			`tx_count = tx_count + 1;`
88
89			`always @uart_parity_error begin`
90			`error_ind = 1;`
91			`par_err_count = par_err_count + 1;`
92			`end`
93
94			`always @uart_stop_error1 begin`
95			`error_ind = 1;`
96			`stop_err1_cnt = stop_err1_cnt + 1;`
97			`end`
98
99			`always @uart_stop_error2 begin`
100			`error_ind = 1;`
101			`stop_err2_cnt = stop_err2_cnt + 1;`
102			`end`
103
104			`always @uart_timeout_error begin`
105			`error_ind = 1;`
106			`timeout_err_cnt = timeout_err_cnt + 1;`
107			`end`
108
109
110			`always @error_detected begin`
111			`error_ind = 1;`
112			`err_cnt = err_cnt + 1;`
113			`end`
114
115
116			`////////////////////////////////////////////////////////////////////////////////`
117			`task uart_init;`
118			`begin`
119			`read = 0;`
120			`write = 0;`
121			`tx_count = 0;`
122			`rx_count = 0;`
123			`stop_err_check = 0;`
124			`par_err_count = 0;`
125			`stop_err1_cnt = 0;`
126			`stop_err2_cnt = 0;`
127			`timeout_err_cnt = 0;`
128			`err_cnt = 0;`
129
130			`end`
131			`endtask`
132
133
134			`////////////////////////////////////////////////////////////////////////////////`
135			`task read_char_chk;`
136			`input expected_data;`
137
138			`integer i;`
139			`reg [7:0] expected_data;`
140			`reg [7:0] data;`
141			`reg parity;`
142
143			`begin`
144			`data <= 8'h0;`
145			`parity <= 1;`
146			`timeout_count = 0;`
147
148			`fork`
149			`begin : loop_1`
150			`@(abort)`
151			`$display (">>>>> Exceed time limit, uart no responce.\n");`
152			`->uart_timeout_error;`
153			`disable loop_2;`
154			`end`
155
156			`begin : loop_2`
157
158			`// start cycle`
159			`@(negedge sout)`
160			`disable loop_1;`
161			`read <= 1;`
162
163			`// data cycle`
164			`@(posedge test_rx_clk);`
165			`for (i = 0; i < data_bit_number; i = i + 1)`
166			`begin`
167			`@(posedge test_rx_clk)`
168			`data[i] <= sout;`
169			`parity <= parity ^ sout;`
170			`end`
171
172			`// parity cycle`
173			`if(control_setup.parity_en)`
174			`begin`
175			`@(posedge test_rx_clk);`
176			`if ((control_setup.even_odd_parity && (sout == parity)) \|\|`
177			`(!control_setup.even_odd_parity && (sout != parity)))`
178			`begin`
179			`$display (">>>>> Parity Error");`
180			`-> error_detected;`
181			`-> uart_parity_error;`
182			`end`
183			`end`
184
185			`// stop cycle 1`
186			`@(posedge test_rx_clk);`
187			`if (!sout)`
188			`begin`
189			`$display (">>>>> Stop signal 1 Error");`
190			`-> error_detected;`
191			`-> uart_stop_error1;`
192			`end`
193
194			`// stop cycle 2`
195			`if (control_setup.stop_bit_number)`
196			`begin`
197			`@(posedge test_rx_clk); // stop cycle 2`
198			`if (!sout)`
199			`begin`
200			`$display (">>>>> Stop signal 2 Error");`
201			`-> error_detected;`
202			`-> uart_stop_error2;`
203			`end`
204			`end`
205
206			`/* Who Cares`
207			`// the stop bits transmitted is one and a half if it is 5-bit`
208			`if (data_bit_number == 5)`
209			`begin`
210			`@(posedge test_rx_clk); // stop cycle for 5-bit/per char`
211			`if (!sout)`
212			`begin`
213			`$display (">>>>> Stop signal 2 Error (5-Bit)");`
214			`-> error_detected;`
215			`-> uart_stop_error2;`
216			`end`
217			`end`
218			`else`
219			`*/`
220
221			`// wait another half cycle for tx_done signal`
222			`@(negedge test_rx_clk);`
223			`read <= 0;`
224			`-> uart_read_done;`
225
226			`if (expected_data != data)`
227			`begin`
228			`$display ("Error! Data return is %h, expecting %h", data, expected_data);`
229			`-> error_detected;`
230			`end`
231			`else`
232			`$display ("(%m) Data match %h", expected_data);`
233
234			`$display ("... Read Data from UART done cnt :%d...",rx_count +1);`
235			`end`
236			`join`
237
238			`end`
239
240			`endtask`
241
242			`////////////////////////////////////////////////////////////////////////////////`
243			`task read_char;`
244			`output [7:0] rxd_data;`
245			`output timeout; // 1-> timeout`
246			`integer i;`
247			`reg [7:0] rxd_data;`
248			`reg [7:0] data;`
249			`reg parity;`
250
251			`begin`
252			`data <= 8'h0;`
253			`parity <= 1;`
254			`timeout_count = 0;`
255			`timeout = 0;`
256
257			`fork`
258			`begin : loop_1`
259			`@(abort)`
260			`//$display (">>>>> Exceed time limit, uart no responce.\n");`
261			`//->uart_timeout_error;`
262			`timeout = 1;`
263			`disable loop_2;`
264			`end`
265
266			`begin : loop_2`
267
268			`// start cycle`
269			`@(negedge sout)`
270			`disable loop_1;`
271			`read <= 1;`
272
273			`// data cycle`
274			`@(posedge test_rx_clk);`
275			`for (i = 0; i < data_bit_number; i = i + 1)`
276			`begin`
277			`@(posedge test_rx_clk)`
278			`data[i] <= sout;`
279			`parity <= parity ^ sout;`
280			`end`
281
282			`// parity cycle`
283			`if(control_setup.parity_en)`
284			`begin`
285			`@(posedge test_rx_clk);`
286			`if ((control_setup.even_odd_parity && (sout == parity)) \|\|`
287			`(!control_setup.even_odd_parity && (sout != parity)))`
288			`begin`
289			`$display (">>>>> Parity Error");`
290			`-> error_detected;`
291			`-> uart_parity_error;`
292			`end`
293			`end`
294
295			`// stop cycle 1`
296			`@(posedge test_rx_clk);`
297			`if (!sout)`
298			`begin`
299			`$display (">>>>> Stop signal 1 Error");`
300			`-> error_detected;`
301			`-> uart_stop_error1;`
302			`end`
303
304			`// stop cycle 2`
305			`if (control_setup.stop_bit_number)`
306			`begin`
307			`@(posedge test_rx_clk); // stop cycle 2`
308			`if (!sout)`
309			`begin`
310			`$display (">>>>> Stop signal 2 Error");`
311			`-> error_detected;`
312			`-> uart_stop_error2;`
313			`end`
314			`end`
315
316			`// wait another half cycle for tx_done signal`
317			`@(negedge test_rx_clk);`
318			`read <= 0;`
319			`-> uart_read_done;`
320
321			`// $display ("(%m) Received Data %c", data);`
322			`// $display ("... Read Data from UART done cnt :%d...",rx_count +1);`
323			`$write ("%c",data);`
324			`rxd_data = data;`
325			`end`
326			`join`
327
328			`end`
329
330			`endtask`
331
332			`////////////////////////////////////////////////////////////////////////////////`
333			`task write_char;`
334			`input [7:0] data;`
335
336			`integer i;`
337			`reg parity; // 0: odd parity, 1: even parity`
338
339			`begin`
340			`parity <= #1 1;`
341
342			`// start cycle`
343			`@(posedge test_tx_clk)`
344			`begin`
345			`sin <= #1 0;`
346			`write <= #1 1;`
347			`end`
348
349			`// data cycle`
350			`begin`
351			`for (i = 0; i < data_bit_number; i = i + 1)`
352			`begin`
353			`@(posedge test_tx_clk)`
354			`sin <= #1 data[i];`
355			`parity <= parity ^ data[i];`
356			`end`
357			`end`
358
359			`// parity cycle`
360			`if (control_setup.parity_en)`
361			`begin`
362			`@(posedge test_tx_clk)`
363			`sin <= #1`
364			`control_setup.even_odd_parity ? !parity : parity;`
365			`end`
366
367			`// stop cycle 1`
368			`@(posedge test_tx_clk)`
369			`sin <= #1 stop_err_check ? 0 : 1;`
370
371			`// stop cycle 2`
372			`@(posedge test_tx_clk);`
373			`sin <= #1 1;`
374			`if (data_bit_number == 5)`
375			`@(negedge test_tx_clk);`
376			`else if (control_setup.stop_bit_number)`
377			`@(posedge test_tx_clk);`
378
379			`write <= #1 0;`
380			`// $display ("... Write data %h to UART done cnt : %d ...\n", data,tx_count+1);`
381			`$write ("%c",data);`
382			`-> uart_write_done;`
383			`end`
384			`endtask`
385
386
387			`////////////////////////////////////////////////////////////////////////////////`
388			`task control_setup;`
389			`input [1:0] data_bit_set;`
390			`input stop_bit_number;`
391			`input parity_en;`
392			`input even_odd_parity;`
393			`input [15:0] maxtime;`
394			`input fifo_enable;`
395
396			`begin`
397			`data_bit_number = data_bit_set + 5;`
398			`end`
399			`endtask`
400
401
402			`////////////////////////////////////////////////////////////////////////////////`
403			`task report_status;`
404			`output [15:0] rx_nu;`
405			`output [15:0] tx_nu;`
406			`begin`
407			`$display ("-------------------- Reporting Configuration --------------------");`
408			`$display (" Data bit number setting is : %0d", data_bit_number);`
409			`$display (" Stop bit number setting is : %0d", control_setup.stop_bit_number + 1);`
410			`if (control_setup.parity_en)`
411			`$display (" Parity is enable");`
412			`else`
413			`$display (" Parity is disable");`
414
415			`if (control_setup.even_odd_parity)`
416			`$display (" Even parity setting");`
417			`else`
418			`$display (" Odd parity setting");`
419
420			`if (control_setup.fifo_enable)`
421			`$display (" FIFO mode is enable");`
422			`else`
423			`$display (" FIFO mode is disable");`
424
425			`$display ("-----------------------------------------------------------------");`
426
427			`$display ("-------------------- Reporting Status --------------------\n");`
428			`$display (" Number of character received is : %d", rx_count);`
429			`$display (" Number of character sent is : %d", tx_count);`
430			`$display (" Number of parity error rxd is : %d", par_err_count);`
431			`$display (" Number of stop1 error rxd is : %d", stop_err1_cnt);`
432			`$display (" Number of stop2 error rxd is : %d", stop_err2_cnt);`
433			`$display (" Number of timeout error is : %d", timeout_err_cnt);`
434			`$display (" Number of error is : %d", err_cnt);`
435			`$display ("-----------------------------------------------------------------");`
436
437			`rx_nu = rx_count;`
438			`tx_nu = tx_count;`
439			`end`
440			`endtask`
441
442
443			`////////////////////////////////////////////////////////////////////////////////`
444			`endmodule`