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<div class="title">E:/uart_block/hdl/iseProject/SYC0001a.vhd</div>  </div>
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<a href="_s_y_c0001a_8vhd.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001
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<a name="l00003"></a>00003
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<a name="l00004"></a>00004 <span class="vhdlkeyword">library </span><span class="keywordflow">ieee</span>;
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<a name="l00005"></a>00005 <span class="vhdlkeyword">use </span>ieee.std_logic_1164.<span class="vhdlkeyword">all</span>;
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<a name="l00006"></a>00006
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<a name="l00007"></a>00007
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<a name="l00008"></a><a class="code" href="class_s_y_c0001a.html">00008</a> <span class="keywordflow">entity </span><a class="code" href="class_s_y_c0001a.html">SYC0001a</a> <span class="vhdlkeyword">is</span>
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<a name="l00009"></a>00009     <span class="vhdlkeyword">port</span><span class="vhdlchar">(</span><span class="keyword"></span>
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<a name="l00010"></a>00010 <span class="keyword">           -- WISHBONE Interface</span>
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<a name="l00011"></a><a class="code" href="class_s_y_c0001a.html#a47194b29006cd455b0c9239f61a32662">00011</a>             <span class="vhdlchar"><a class="code" href="class_s_y_c0001a.html#a47194b29006cd455b0c9239f61a32662" title="Clock output.">CLK_O</a></span><span class="vhdlchar">:</span>  <span class="vhdlkeyword">out</span> <span class="comment">std_logic</span>;
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<a name="l00012"></a><a class="code" href="class_s_y_c0001a.html#ad526bc5e7968a2200cff030cb9b1d23e">00012</a>             <span class="vhdlchar"><a class="code" href="class_s_y_c0001a.html#ad526bc5e7968a2200cff030cb9b1d23e" title="Reset output.">RST_O</a></span><span class="vhdlchar">:</span>  <span class="vhdlkeyword">out</span> <span class="comment">std_logic</span>;<span class="keyword"></span>
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<a name="l00013"></a>00013 <span class="keyword">            -- NON-WISHBONE Signals</span>
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<a name="l00014"></a><a class="code" href="class_s_y_c0001a.html#aec20dfafe328406fe05937923ffb3546">00014</a>             <span class="vhdlchar"><a class="code" href="class_s_y_c0001a.html#aec20dfafe328406fe05937923ffb3546" title="Clock input.">EXTCLK</a></span><span class="vhdlchar">:</span> <span class="vhdlkeyword">in</span>  <span class="comment">std_logic</span>;
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<a name="l00015"></a><a class="code" href="class_s_y_c0001a.html#a5242034b20a8e2bd36922221b2791426">00015</a>             <span class="vhdlchar"><a class="code" href="class_s_y_c0001a.html#a5242034b20a8e2bd36922221b2791426" title="Reset input.">EXTRST</a></span><span class="vhdlchar">:</span> <span class="vhdlkeyword">in</span>  <span class="comment">std_logic</span>
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<a name="l00016"></a>00016          <span class="vhdlchar">)</span>;
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<a name="l00017"></a>00017
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<a name="l00018"></a>00018 <span class="vhdlkeyword">end</span> <span class="vhdlchar">SYC0001a</span>;
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<a name="l00019"></a>00019
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<a name="l00020"></a>00020
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<a name="l00021"></a>00021
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<a name="l00024"></a><a class="code" href="class_s_y_c0001a_1_1_s_y_c0001a1.html">00024</a> <span class="vhdlkeyword">architecture</span> SYC0001a1 <span class="vhdlkeyword">of</span> <a class="code" href="class_s_y_c0001a.html">SYC0001a</a> IS
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<a name="l00025"></a>00025
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<a name="l00026"></a>00026 <span class="vhdlkeyword">begin</span>
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<a name="l00027"></a>00027
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<a name="l00028"></a>00028
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<a name="l00029"></a>00029     MAKE_VISIBLE: <span class="vhdlkeyword">process</span>( <a class="code" href="class_s_y_c0001a.html#aec20dfafe328406fe05937923ffb3546" title="Clock input.">EXTCLK</a>, <a class="code" href="class_s_y_c0001a.html#a5242034b20a8e2bd36922221b2791426" title="Reset input.">EXTRST</a> )
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<a name="l00030"></a>00030 <span class="vhdlkeyword">    begin</span>
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<a name="l00031"></a>00031
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<a name="l00032"></a>00032         <span class="vhdlchar"><a class="code" href="class_s_y_c0001a.html#a47194b29006cd455b0c9239f61a32662" title="Clock output.">CLK_O</a></span> <span class="vhdlchar">&lt;=</span> <span class="vhdlchar"><a class="code" href="class_s_y_c0001a.html#aec20dfafe328406fe05937923ffb3546" title="Clock input.">EXTCLK</a></span>;
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<a name="l00033"></a>00033         <span class="vhdlchar"><a class="code" href="class_s_y_c0001a.html#ad526bc5e7968a2200cff030cb9b1d23e" title="Reset output.">RST_O</a></span> <span class="vhdlchar">&lt;=</span> <span class="vhdlchar"><a class="code" href="class_s_y_c0001a.html#a5242034b20a8e2bd36922221b2791426" title="Reset input.">EXTRST</a></span>;
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<a name="l00034"></a>00034
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<a name="l00035"></a>00035     <span class="vhdlkeyword">end</span> <span class="vhdlkeyword">process</span> <span class="vhdlchar">MAKE_VISIBLE</span>;
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<a name="l00036"></a>00036
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<a name="l00037"></a>00037 <span class="vhdlkeyword">end</span> <span class="vhdlkeyword">architecture</span> <span class="vhdlchar">SYC0001a1</span>;
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</pre></div></div><!-- contents -->
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