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39 |
leonardoar |
Running: e:\Xilinx\13.4\ISE_DS\ISE\bin\nt64\unwrapped\fuse.exe -intstyle ise -incremental -o E:/uart_block/hdl/iseProject/testUart_communication_block_isim_beh.exe -prj E:/uart_block/hdl/iseProject/testUart_communication_block_beh.prj work.testUart_communication_block
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| 2 |
35 |
leonardoar |
ISim O.87xd (signature 0xc3576ebc)
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| 3 |
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Number of CPUs detected in this system: 8
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| 4 |
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Turning on mult-threading, number of parallel sub-compilation jobs: 16
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| 5 |
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Determining compilation order of HDL files
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| 6 |
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Parsing VHDL file "E:/uart_block/hdl/iseProject/pkgDefinitions.vhd" into library work
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| 7 |
39 |
leonardoar |
Parsing VHDL file "E:/uart_block/hdl/iseProject/serial_transmitter.vhd" into library work
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| 8 |
35 |
leonardoar |
Parsing VHDL file "E:/uart_block/hdl/iseProject/serial_receiver.vhd" into library work
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| 9 |
39 |
leonardoar |
Parsing VHDL file "E:/uart_block/hdl/iseProject/baud_generator.vhd" into library work
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| 10 |
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Parsing VHDL file "E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd" into library work
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| 11 |
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WARNING:HDLCompiler:946 - "E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd" Line 65: Actual for formal port rst is neither a static name nor a globally static expression
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| 12 |
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Parsing VHDL file "E:/uart_block/hdl/iseProject/testUart_communication_block.vhd" into library work
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| 13 |
35 |
leonardoar |
Starting static elaboration
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| 14 |
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Completed static elaboration
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| 15 |
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Compiling package standard
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| 16 |
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Compiling package std_logic_1164
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| 17 |
39 |
leonardoar |
Compiling package std_logic_arith
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| 18 |
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Compiling package std_logic_unsigned
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| 19 |
35 |
leonardoar |
Compiling package pkgdefinitions
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| 20 |
39 |
leonardoar |
Compiling package numeric_std
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| 21 |
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Compiling architecture behavioral of entity baud_generator [baud_generator_default]
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| 22 |
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Compiling architecture behavioral of entity serial_transmitter [serial_transmitter_default]
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| 23 |
35 |
leonardoar |
Compiling architecture behavioral of entity serial_receiver [serial_receiver_default]
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| 24 |
39 |
leonardoar |
Compiling architecture behavioral of entity uart_communication_blocks [uart_communication_blocks_defaul...]
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| 25 |
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Compiling architecture behavior of entity testuart_communication_block
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| 26 |
35 |
leonardoar |
Time Resolution for simulation is 1ps.
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| 27 |
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Waiting for 1 sub-compilation(s) to finish...
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| 28 |
39 |
leonardoar |
Compiled 15 VHDL Units
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| 29 |
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Built simulation executable E:/uart_block/hdl/iseProject/testUart_communication_block_isim_beh.exe
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| 30 |
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Fuse Memory Usage: 37044 KB
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| 31 |
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Fuse CPU Usage: 420 ms
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