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ISim log file

Running: /home/laraujo/work/uart_block/hdl/iseProject/testUart_communication_block_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/laraujo/work/uart_block/hdl/iseProject/testUart_communication_block_isim_beh.wdb

ISim O.87xd (signature 0x8ddf5b5d)

WARNING: A WEBPACK license was found.

WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.

WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.

This is a Lite version of ISim.

Time resolution is 1 ps

# onerror resume

# wave add /

# run 1000 ms

Simulator is doing circuit initialization process.

Finished circuit initialization process.

** Failure:NONE. End of simulation.

User(VHDL) Code Called Simulation Stop

In process testUart_communication_block.vhd:stim_proc

INFO: Simulator is stopped.

# exit 0