Subversion Repositories uart_plb

/*

 * Copyright (c) 2010 Xilinx, Inc.  All rights reserved.

 *

 * Xilinx, Inc.

 * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A

 * COURTESY TO YOU.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS

 * ONE POSSIBLE   IMPLEMENTATION OF THIS FEATURE, APPLICATION OR

 * STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION

 * IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE

 * FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.

 * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO

 * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO

 * ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE

 * FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY

 * AND FITNESS FOR A PARTICULAR PURPOSE.

 *

 */

#include "xparameters.h"

#include "xil_cache.h"

#include "platform_config.h"

#ifdef STDOUT_IS_16550

#include "xuartns550_l.h"

#endif

void

enable_caches()

{

#ifdef __PPC__

    Xil_ICacheEnableRegion(CACHEABLE_REGION_MASK);

    Xil_DCacheEnableRegion(CACHEABLE_REGION_MASK);

#elif __MICROBLAZE__

#ifdef XPAR_MICROBLAZE_USE_ICACHE 

    Xil_ICacheEnable();

#endif

#ifdef XPAR_MICROBLAZE_USE_DCACHE 

    Xil_DCacheEnable();

#endif

#endif

}

void

disable_caches()

{

    Xil_DCacheDisable();

    Xil_ICacheDisable();

}

void

init_platform()

{

    enable_caches();

    /* if we have a uart 16550, then that needs to be initialized */

#ifdef STDOUT_IS_16550

    XUartNs550_SetBaud(STDOUT_BASEADDR, XPAR_XUARTNS550_CLOCK_HZ, 9600);

    XUartNs550_SetLineControlReg(STDOUT_BASEADDR, XUN_LCR_8_DATA_BITS);

#endif

}

void

cleanup_platform()

{

    disable_caches();

}