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[/] [uart_plb/] [trunk/] [pcores/] [uart_plb_v1_00_a/] [hdl/] [vhdl/] [tx.vhd] - Blame information for rev 2

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-- $Id$
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
-- Serial UART transmitter
entity xmt is
    generic (DATA_BITS : integer);
    port (
        clk       : in  std_logic;  -- Clock
        rst       : in  std_logic;  -- Reset
        tick      : in  std_logic;  -- baudrate * 16 tick
        wr        : in  std_logic;  -- write din to transmitter
        din       : in  std_logic_vector(DATA_BITS-1 downto 0);  -- Input data
        sout      : out std_logic;  -- Transmitter serial output
        done      : out std_logic   -- level signal, transmit shift register empty
    );
end xmt;
 
architecture rtl of xmt is
 
    signal shift_reg : std_logic_vector(DATA_BITS downto 0) := (others=>'1');
    signal shift_cnt : std_logic_vector(DATA_BITS+1 downto 0) := (others=>'1');
    signal baud_cnt  : std_logic_vector(3 downto 0) := (others=>'0');
    signal baud_tick : std_logic := '0';
    signal sout_s    : std_logic := '1';
 
begin
 
    process(clk)
    begin
        if rising_edge(clk) then
            if rst = '1' then
                baud_cnt <= (others=>'0');
            elsif (tick = '1') then
                baud_cnt <= baud_cnt + 1;
            end if;
        end if;
    end process;
 
    process(clk)
    begin
        if rising_edge(clk) then
            if (baud_cnt = "1111") and (tick = '1') then
                baud_tick <= '1';
            else
                baud_tick <= '0';
            end if;
        end if;
    end process;
 
    sout <= sout_s;
 
    process(clk)
    begin
        if rising_edge(clk) then
            if rst = '1' then
                sout_s <= '1';
            elsif (baud_tick = '1') then
                sout_s <= shift_reg(0);
            end  if;
        end if;
    end process;
 
    process(clk)
    begin
        if rising_edge(clk) then
            if wr = '1' then
                shift_reg <= din & '0'; -- add start bit
                shift_cnt <= (others=>'0');
            elsif (baud_tick = '1') then
                shift_reg <= '1' & shift_reg(shift_reg'left downto 1); -- shift out and add stop bits
                shift_cnt <= '1' & shift_cnt(shift_cnt'left downto 1); -- shift out and add done bits
            end if;
        end if;
    end process;
 
    done <= shift_cnt(0); -- it will be '1' when finished sending
 
end rtl;
 

Line No.	Rev	Author	Line
1	2	gavinux	`-- $Id$`
2			`library IEEE;`
3			`use IEEE.STD_LOGIC_1164.ALL;`
4			`use IEEE.STD_LOGIC_ARITH.ALL;`
5			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
6
7			`-- Serial UART transmitter`
8			`entity xmt is`
9			`generic (DATA_BITS : integer);`
10			`port (`
11			`clk : in std_logic; -- Clock`
12			`rst : in std_logic; -- Reset`
13			`tick : in std_logic; -- baudrate * 16 tick`
14			`wr : in std_logic; -- write din to transmitter`
15			`din : in std_logic_vector(DATA_BITS-1 downto 0); -- Input data`
16			`sout : out std_logic; -- Transmitter serial output`
17			`done : out std_logic -- level signal, transmit shift register empty`
18			`);`
19			`end xmt;`
20
21			`architecture rtl of xmt is`
22
23			`signal shift_reg : std_logic_vector(DATA_BITS downto 0) := (others=>'1');`
24			`signal shift_cnt : std_logic_vector(DATA_BITS+1 downto 0) := (others=>'1');`
25			`signal baud_cnt : std_logic_vector(3 downto 0) := (others=>'0');`
26			`signal baud_tick : std_logic := '0';`
27			`signal sout_s : std_logic := '1';`
28
29			`begin`
30
31			`process(clk)`
32			`begin`
33			`if rising_edge(clk) then`
34			`if rst = '1' then`
35			`baud_cnt <= (others=>'0');`
36			`elsif (tick = '1') then`
37			`baud_cnt <= baud_cnt + 1;`
38			`end if;`
39			`end if;`
40			`end process;`
41
42			`process(clk)`
43			`begin`
44			`if rising_edge(clk) then`
45			`if (baud_cnt = "1111") and (tick = '1') then`
46			`baud_tick <= '1';`
47			`else`
48			`baud_tick <= '0';`
49			`end if;`
50			`end if;`
51			`end process;`
52
53			`sout <= sout_s;`
54
55			`process(clk)`
56			`begin`
57			`if rising_edge(clk) then`
58			`if rst = '1' then`
59			`sout_s <= '1';`
60			`elsif (baud_tick = '1') then`
61			`sout_s <= shift_reg(0);`
62			`end if;`
63			`end if;`
64			`end process;`
65
66			`process(clk)`
67			`begin`
68			`if rising_edge(clk) then`
69			`if wr = '1' then`
70			`shift_reg <= din & '0'; -- add start bit`
71			`shift_cnt <= (others=>'0');`
72			`elsif (baud_tick = '1') then`
73			`shift_reg <= '1' & shift_reg(shift_reg'left downto 1); -- shift out and add stop bits`
74			`shift_cnt <= '1' & shift_cnt(shift_cnt'left downto 1); -- shift out and add done bits`
75			`end if;`
76			`end if;`
77			`end process;`
78
79			`done <= shift_cnt(0); -- it will be '1' when finished sending`
80
81			`end rtl;`
82

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[/] [uart_plb/] [trunk/] [pcores/] [uart_plb_v1_00_a/] [hdl/] [vhdl/] [tx.vhd] - Blame information for rev 2