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------------------------------------------------------------------------------

-- user_logic.vhd - entity/architecture pair

------------------------------------------------------------------------------

--

-- ***************************************************************************

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-- **                                                                       **

-- ** Xilinx, Inc.                                                          **

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-- ***************************************************************************

--

------------------------------------------------------------------------------

-- Filename:          user_logic.vhd

-- Version:           1.00.a

-- Description:       User logic.

-- Date:              Fri Jun 03 17:26:27 2011 (by Create and Import Peripheral Wizard)

-- VHDL Standard:     VHDL'93

------------------------------------------------------------------------------

-- Naming Conventions:

--   active low signals:                    "*_n"

--   clock signals:                         "clk", "clk_div#", "clk_#x"

--   reset signals:                         "rst", "rst_n"

--   generics:                              "C_*"

--   user defined types:                    "*_TYPE"

--   state machine next state:              "*_ns"

--   state machine current state:           "*_cs"

--   combinatorial signals:                 "*_com"

--   pipelined or register delay signals:   "*_d#"

--   counter signals:                       "*cnt*"

--   clock enable signals:                  "*_ce"

--   internal version of output port:       "*_i"

--   device pins:                           "*_pin"

--   ports:                                 "- Names begin with Uppercase"

--   processes:                             "*_PROCESS"

--   component instantiations:              "<ENTITY_>I_<#|FUNC>"

------------------------------------------------------------------------------

-- DO NOT EDIT BELOW THIS LINE --------------------

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

use work.uart_components.uart;

library proc_common_v3_00_a;

use proc_common_v3_00_a.proc_common_pkg.all;

-- DO NOT EDIT ABOVE THIS LINE --------------------

--USER libraries added here

------------------------------------------------------------------------------

-- Entity section

------------------------------------------------------------------------------

-- Definition of Generics:

--   C_SLV_DWIDTH                 -- Slave interface data bus width

--   C_NUM_REG                    -- Number of software accessible registers

--   C_NUM_INTR                   -- Number of interrupt event

--

-- Definition of Ports:

--   Bus2IP_Clk                   -- Bus to IP clock

--   Bus2IP_Reset                 -- Bus to IP reset

--   Bus2IP_Data                  -- Bus to IP data bus

--   Bus2IP_BE                    -- Bus to IP byte enables

--   Bus2IP_RdCE                  -- Bus to IP read chip enable

--   Bus2IP_WrCE                  -- Bus to IP write chip enable

--   IP2Bus_Data                  -- IP to Bus data bus

--   IP2Bus_RdAck                 -- IP to Bus read transfer acknowledgement

--   IP2Bus_WrAck                 -- IP to Bus write transfer acknowledgement

--   IP2Bus_Error                 -- IP to Bus error response

--   IP2Bus_IntrEvent             -- IP to Bus interrupt event

------------------------------------------------------------------------------

entity user_logic is

  generic

  (

    -- ADD USER GENERICS BELOW THIS LINE ---------------

    --USER generics added here

    -- ADD USER GENERICS ABOVE THIS LINE ---------------

    -- DO NOT EDIT BELOW THIS LINE ---------------------

    -- Bus protocol parameters, do not add to or delete

    C_SLV_DWIDTH                   : integer              := 32;

    C_NUM_REG                      : integer              := 8;

    C_NUM_INTR                     : integer              := 1

    -- DO NOT EDIT ABOVE THIS LINE ---------------------

  );

  port

  (

    -- ADD USER PORTS BELOW THIS LINE ------------------

    --USER ports added here

    tx_sout                        : out std_logic;

    rx_sin                         : in  std_logic;

    -- ADD USER PORTS ABOVE THIS LINE ------------------

    -- DO NOT EDIT BELOW THIS LINE ---------------------

    -- Bus protocol ports, do not add to or delete

    Bus2IP_Clk                     : in  std_logic;

    Bus2IP_Reset                   : in  std_logic;

    Bus2IP_Data                    : in  std_logic_vector(0 to C_SLV_DWIDTH-1);

    Bus2IP_BE                      : in  std_logic_vector(0 to C_SLV_DWIDTH/8-1);

    Bus2IP_RdCE                    : in  std_logic_vector(0 to C_NUM_REG-1);

    Bus2IP_WrCE                    : in  std_logic_vector(0 to C_NUM_REG-1);

    IP2Bus_Data                    : out std_logic_vector(0 to C_SLV_DWIDTH-1);

    IP2Bus_RdAck                   : out std_logic;

    IP2Bus_WrAck                   : out std_logic;

    IP2Bus_Error                   : out std_logic;

    IP2Bus_IntrEvent               : out std_logic_vector(0 to C_NUM_INTR-1)

    -- DO NOT EDIT ABOVE THIS LINE ---------------------

  );

  attribute SIGIS : string;

  attribute SIGIS of Bus2IP_Clk    : signal is "CLK";

  attribute SIGIS of Bus2IP_Reset  : signal is "RST";

end entity user_logic;

------------------------------------------------------------------------------

-- Architecture section

------------------------------------------------------------------------------

architecture IMP of user_logic is

  --USER signal declarations added here, as needed for user logic

  ------------------------------------------

  -- Signals for user logic slave model s/w accessible register example

  ------------------------------------------

  signal slv_rxd                        : std_logic_vector(0 to C_SLV_DWIDTH-1);

  signal slv_txd                        : std_logic_vector(0 to C_SLV_DWIDTH-1);

  signal slv_ctrl                       : std_logic_vector(0 to C_SLV_DWIDTH-1);

  signal slv_status                     : std_logic_vector(0 to C_SLV_DWIDTH-1);

  signal slv_dlw                        : std_logic_vector(0 to C_SLV_DWIDTH-1) := X"00000019"; -- 115200Hz @50MHz

  signal slv_reg5                       : std_logic_vector(0 to C_SLV_DWIDTH-1);

  signal slv_reg6                       : std_logic_vector(0 to C_SLV_DWIDTH-1);

  signal slv_reg7                       : std_logic_vector(0 to C_SLV_DWIDTH-1);

  signal slv_reg_write_sel              : std_logic_vector(0 to 7);

  signal slv_reg_read_sel               : std_logic_vector(0 to 7);

  signal slv_ip2bus_data                : std_logic_vector(0 to C_SLV_DWIDTH-1);

  signal slv_read_ack                   : std_logic;

  signal slv_write_ack                  : std_logic;

begin

  --USER logic implementation added here

    inst_uart_plb_ip : uart

    generic map(DATA_BITS => 8)

    Port map(

        rst                  => Bus2IP_Reset,

        clk                  => Bus2IP_Clk,

        dlw                  => slv_dlw(16 to 31),

        --

        tx_wr                => Bus2IP_WrCE(1),        -- pulse signal

        tx_fifo_reset        => slv_ctrl(31),       -- pulse

        tx_din               => Bus2IP_Data(24 to 31),

        tx_fifo_full         => slv_status(15),        -- level signal

        tx_fifo_almost_full  => slv_status(14),

        tx_fifo_empty        => slv_status(13),        -- level signal

        tx_fifo_almost_empty => slv_status(12),        -- level signal

        tx_xmt_empty         => slv_status(11),        -- level signal, transmit shift register empty

        --

        rx_rd                => slv_reg_read_sel(0),   -- pulse signal

        rx_fifo_reset        => slv_ctrl(30),       -- pulse

        rx_dout              => slv_rxd(24 to 31),

        rx_fifo_full         => slv_status(7),        -- level signal

        rx_fifo_almost_full  => slv_status(6),

        rx_fifo_empty        => slv_status(5),        -- level signal

        rx_fifo_almost_empty => slv_status(4),

        rx_timeout           => slv_status(3),        -- pulse signal

        --

        tx_sout              => tx_sout,

        rx_sin               => rx_sin

    );

    IP2Bus_IntrEvent(0) <= slv_ctrl(27) and

                        ( (slv_ctrl(15) or slv_status(15)) or

                          (slv_ctrl(14) or slv_status(14)) or

                          (slv_ctrl(13) or slv_status(13)) or

                          (slv_ctrl(12) or slv_status(12)) or

                          (slv_ctrl(11) or slv_status(11)) or

                          (slv_ctrl(7)  or slv_status(7))  or

                          (slv_ctrl(6)  or slv_status(6))  or

                          (slv_ctrl(5)  or slv_status(5))  or

                          (slv_ctrl(4)  or slv_status(4))  or

                          (slv_ctrl(3)  or slv_status(3))

                        );

    slv_status(27) <= slv_ctrl(27);

    slv_status(30) <= slv_ctrl(30);

    slv_status(31) <= slv_ctrl(31);

  ------------------------------------------

  -- Example code to read/write user logic slave model s/w accessible registers

  -- 

  -- Note:

  -- The example code presented here is to show you one way of reading/writing

  -- software accessible registers implemented in the user logic slave model.

  -- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond

  -- to one software accessible register by the top level template. For example,

  -- if you have four 32 bit software accessible registers in the user logic,

  -- you are basically operating on the following memory mapped registers:

  -- 

  --    Bus2IP_WrCE/Bus2IP_RdCE   Memory Mapped Register

  --                     "1000"   C_BASEADDR + 0x0

  --                     "0100"   C_BASEADDR + 0x4

  --                     "0010"   C_BASEADDR + 0x8

  --                     "0001"   C_BASEADDR + 0xC

  -- 

  ------------------------------------------

  slv_reg_write_sel <= Bus2IP_WrCE(0 to 7);

  slv_reg_read_sel  <= Bus2IP_RdCE(0 to 7);

  slv_write_ack     <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3) or Bus2IP_WrCE(4) or Bus2IP_WrCE(5) or Bus2IP_WrCE(6) or Bus2IP_WrCE(7);

  slv_read_ack      <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or Bus2IP_RdCE(2) or Bus2IP_RdCE(3) or Bus2IP_RdCE(4) or Bus2IP_RdCE(5) or Bus2IP_RdCE(6) or Bus2IP_RdCE(7);

  -- implement slave model software accessible register(s)

  SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is

  begin

    if Bus2IP_Clk'event and Bus2IP_Clk = '1' then

      if Bus2IP_Reset = '1' then

        slv_rxd(0 to 23)    <= (others => '0');

        slv_txd    <= (others => '0');

        slv_ctrl   <= (others => '0');

--        slv_status <= (others => '0');

        slv_dlw    <= X"0000001B";

        slv_reg5 <= (others => '0');

        slv_reg6 <= (others => '0');

        slv_reg7 <= (others => '0');

      else

        case slv_reg_write_sel is

          when "10000000" =>

            for byte_index in 0 to (C_SLV_DWIDTH/8)-2 loop

              if ( Bus2IP_BE(byte_index) = '1' ) then

                slv_rxd(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);

              end if;

            end loop;

          when "01000000" =>

            for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop

              if ( Bus2IP_BE(byte_index) = '1' ) then

                slv_txd(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);

              end if;

            end loop;

          when "00100000" =>

            for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop

              if ( Bus2IP_BE(byte_index) = '1' ) then

                slv_ctrl(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);

              end if;

            end loop;

          when "00010000" =>

--            for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop

--              if ( Bus2IP_BE(byte_index) = '1' ) then

--                slv_reg3(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);

--              end if;

--            end loop;

          when "00001000" =>

            for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop

              if ( Bus2IP_BE(byte_index) = '1' ) then

                slv_dlw(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);

              end if;

            end loop;

          when "00000100" =>

            for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop

              if ( Bus2IP_BE(byte_index) = '1' ) then

                slv_reg5(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);

              end if;

            end loop;

          when "00000010" =>

            for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop

              if ( Bus2IP_BE(byte_index) = '1' ) then

                slv_reg6(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);

              end if;

            end loop;

          when "00000001" =>

            for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop

              if ( Bus2IP_BE(byte_index) = '1' ) then

                slv_reg7(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);

              end if;

            end loop;

          when others => null;

        end case;

      end if;

    end if;

  end process SLAVE_REG_WRITE_PROC;

  -- implement slave model software accessible register(s) read mux

  SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_rxd, slv_txd, slv_ctrl, slv_status, slv_dlw, slv_reg5, slv_reg6, slv_reg7 ) is

  begin

    case slv_reg_read_sel is

      when "10000000" => slv_ip2bus_data <= slv_rxd;

      when "01000000" => slv_ip2bus_data <= slv_txd;

      when "00100000" => slv_ip2bus_data <= slv_ctrl;

      when "00010000" => slv_ip2bus_data <= slv_status;

      when "00001000" => slv_ip2bus_data <= slv_dlw;

      when "00000100" => slv_ip2bus_data <= slv_reg5;

      when "00000010" => slv_ip2bus_data <= slv_reg6;

      when "00000001" => slv_ip2bus_data <= slv_reg7;

      when others => slv_ip2bus_data <= (others => '0');

    end case;

  end process SLAVE_REG_READ_PROC;

  ------------------------------------------

  -- Example code to drive IP to Bus signals

  ------------------------------------------

  IP2Bus_Data  <= slv_ip2bus_data when slv_read_ack = '1' else

                  (others => '0');

  IP2Bus_WrAck <= slv_write_ack;

  IP2Bus_RdAck <= slv_read_ack;

  IP2Bus_Error <= '0';

end IMP;