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URL https://opencores.org/ocsvn/udp_ipv4_for_10g_ethernet/udp_ipv4_for_10g_ethernet/trunk

Subversion Repositories udp_ipv4_for_10g_ethernet

[/] [udp_ipv4_for_10g_ethernet/] [trunk/] [component.xml] - Blame information for rev 3

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                xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
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                xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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        dfcdesign.cz
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        dfc
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        udp_ip_10g
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        1.0
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                        RST
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                                        spirit:library="signal"
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                                        spirit:name="reset"
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                                        spirit:version="1.0"/>
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                                        spirit:library="signal"
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                                        spirit:name="reset_rtl"
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                                        spirit:version="1.0"/>
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                                                RST
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                                                RST
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                        CLK
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                                        spirit:library="signal"
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                                        spirit:name="clock"
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                                        spirit:version="1.0"/>
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                                        spirit:library="signal"
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                                        spirit:name="clock_rtl"
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                                        spirit:version="1.0"/>
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                                                CLK
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                                                CLK
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                                        ASSOCIATED_RESET
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                                        RST
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                                        ASSOCIATED_BUSIF
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                                        xgmii
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                        xgmii
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                                        spirit:library="interface"
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                                        spirit:name="xgmii"
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                                        spirit:version="1.0"/>
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                                        spirit:library="interface"
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                                        spirit:name="xgmii_rtl"
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                                        spirit:version="1.0"/>
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                                                TXD
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                                                XGMII_TXD
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                                                RXC
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                                                XGMII_RXC
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                                                TXC
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                                                XGMII_TXC
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                                                RXD
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                                                XGMII_RXD
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111
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113
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                                xilinx_anylanguagesynthesis
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                                Synthesis
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                                :vivado.xilinx.com:synthesis
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                                VHDL
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                                udp_ip_10g
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                                        xilinx_anylanguagesynthesis_xilinx_com_ip_lib_fifo_1_0__ref_view_fileset
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                                        xilinx_anylanguagesynthesis_xilinx_com_ip_lib_cdc_1_0__ref_view_fileset
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                                        xilinx_anylanguagesynthesis_xilinx_com_ip_lib_pkg_1_0__ref_view_fileset
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                                        xilinx_anylanguagesynthesis_xilinx_com_ip_lib_srl_fifo_1_0__ref_view_fileset
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                                        xilinx_anylanguagesynthesis_view_fileset
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                                                viewChecksum
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                                                1a377e3e
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                                xilinx_anylanguagebehavioralsimulation
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                                Simulation
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                                :vivado.xilinx.com:simulation
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                                VHDL
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                                udp_ip_10g
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148 
                                        xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_lib_fifo_1_0__ref_view_fileset
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                                        xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_lib_cdc_1_0__ref_view_fileset
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                                        xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_lib_pkg_1_0__ref_view_fileset
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                                        xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_lib_srl_fifo_1_0__ref_view_fileset
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                                        xilinx_anylanguagebehavioralsimulation_view_fileset
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                                                viewChecksum
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                                                1a377e3e
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                                xilinx_xpgui
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                                UI Layout
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                                :vivado.xilinx.com:xgui.ui
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                                        xilinx_xpgui_view_fileset
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                                                viewChecksum
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                                                8516bdaa
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                                RST
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                                        in
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                                                        std_logic
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                                                        xilinx_anylanguagesynthesis
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                                                        xilinx_anylanguagebehavioralsimulation
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                                CLK
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                                        in
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                                                        std_logic
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                                                        xilinx_anylanguagesynthesis
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                                                        xilinx_anylanguagebehavioralsimulation
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                                LINK_SPEED
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                                        in
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                                                2
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                                                0
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219
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                                                        std_logic_vector
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                                                        xilinx_anylanguagesynthesis
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                                                        xilinx_anylanguagebehavioralsimulation
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                                HOST_MAC
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                                        in
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                                                47
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                                                0
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236
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                                                        std_logic_vector
239 
                                                        xilinx_anylanguagesynthesis
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                                                        xilinx_anylanguagebehavioralsimulation
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245
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                                HOST_IP
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                                        in
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                                                31
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                                                0
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                                                        std_logic_vector
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                                                        xilinx_anylanguagesynthesis
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                                                        xilinx_anylanguagebehavioralsimulation
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261
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                                HOST_IP_NETMASK
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                                        in
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                                                31
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                                                0
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                                                        std_logic_vector
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                                                        xilinx_anylanguagesynthesis
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                                                        xilinx_anylanguagebehavioralsimulation
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                                TX_DST_MAC
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                                        in
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                                                47
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                                                0
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287
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                                                        std_logic_vector
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                                                        xilinx_anylanguagesynthesis
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                                                        xilinx_anylanguagebehavioralsimulation
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                                TX_DST_IP
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                                        in
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                                                31
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                                                0
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                                                        std_logic_vector
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                                                        xilinx_anylanguagesynthesis
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                                                        xilinx_anylanguagebehavioralsimulation
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                                TX_SRC_UDP
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                                        in
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                                                15
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                                                0
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321
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                                                        std_logic_vector
324 
                                                        xilinx_anylanguagesynthesis
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                                                        xilinx_anylanguagebehavioralsimulation
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328
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                                TX_DST_UDP
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                                        in
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                                                15
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                                                0
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338
339
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                                                        std_logic_vector
341 
                                                        xilinx_anylanguagesynthesis
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                                                        xilinx_anylanguagebehavioralsimulation
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345
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                                TX_FRAME_VALID
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                                        in
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352
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                                                        std_logic
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                                                        xilinx_anylanguagesynthesis
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                                                        xilinx_anylanguagebehavioralsimulation
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357
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                                TX_FRAME_RDY
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                                        out
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                                                        std_logic
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                                                        xilinx_anylanguagesynthesis
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                                                        xilinx_anylanguagebehavioralsimulation
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370
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                                TX_FRAME_LAST
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                                        in
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                                                        std_logic
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                                                        xilinx_anylanguagesynthesis
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                                                        xilinx_anylanguagebehavioralsimulation
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383
384
385
386
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                                TX_FRAME_BE
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389 
                                        in
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                                                7
392 
                                                0
393
394
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                                                        std_logic_vector
397 
                                                        xilinx_anylanguagesynthesis
398 
                                                        xilinx_anylanguagebehavioralsimulation
399
400
401
402
403
404 
                                TX_FRAME_DATA
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                                        in
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408 
                                                63
409 
                                                0
410
411
412
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                                                        std_logic_vector
414 
                                                        xilinx_anylanguagesynthesis
415 
                                                        xilinx_anylanguagebehavioralsimulation
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417
418
419
420
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                                RX_SRC_MAC
422
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                                        out
424
425 
                                                47
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                                                0
427
428
429
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                                                        std_logic_vector
431 
                                                        xilinx_anylanguagesynthesis
432 
                                                        xilinx_anylanguagebehavioralsimulation
433
434
435
436
437
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                                RX_SRC_IP
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440 
                                        out
441
442 
                                                31
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                                                0
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                                                        std_logic_vector
448 
                                                        xilinx_anylanguagesynthesis
449 
                                                        xilinx_anylanguagebehavioralsimulation
450
451
452
453
454
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                                RX_SRC_UDP
456
457 
                                        out
458
459 
                                                15
460 
                                                0
461
462
463
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                                                        std_logic_vector
465 
                                                        xilinx_anylanguagesynthesis
466 
                                                        xilinx_anylanguagebehavioralsimulation
467
468
469
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471
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                                RX_DST_UDP
473
474 
                                        out
475
476 
                                                15
477 
                                                0
478
479
480
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                                                        std_logic_vector
482 
                                                        xilinx_anylanguagesynthesis
483 
                                                        xilinx_anylanguagebehavioralsimulation
484
485
486
487
488
489 
                                RX_FRAME_VALID
490
491 
                                        out
492
493
494 
                                                        std_logic
495 
                                                        xilinx_anylanguagesynthesis
496 
                                                        xilinx_anylanguagebehavioralsimulation
497
498
499
500
501
502 
                                RX_FRAME_RDY
503
504 
                                        in
505
506
507 
                                                        std_logic
508 
                                                        xilinx_anylanguagesynthesis
509 
                                                        xilinx_anylanguagebehavioralsimulation
510
511
512
513
514
515 
                                RX_FRAME_LAST
516
517 
                                        out
518
519
520 
                                                        std_logic
521 
                                                        xilinx_anylanguagesynthesis
522 
                                                        xilinx_anylanguagebehavioralsimulation
523
524
525
526
527
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                                RX_FRAME_BE
529
530 
                                        out
531
532 
                                                7
533 
                                                0
534
535
536
537 
                                                        std_logic_vector
538 
                                                        xilinx_anylanguagesynthesis
539 
                                                        xilinx_anylanguagebehavioralsimulation
540
541
542
543
544
545 
                                RX_FRAME_DATA
546
547 
                                        out
548
549 
                                                63
550 
                                                0
551
552
553
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                                                        std_logic_vector
555 
                                                        xilinx_anylanguagesynthesis
556 
                                                        xilinx_anylanguagebehavioralsimulation
557
558
559
560
561
562 
                                RX_FRAME_LENGTH
563
564 
                                        out
565
566 
                                                15
567 
                                                0
568
569
570
571 
                                                        std_logic_vector
572 
                                                        xilinx_anylanguagesynthesis
573 
                                                        xilinx_anylanguagebehavioralsimulation
574
575
576
577
578
579 
                                XGMII_TXC
580
581 
                                        out
582
583 
                                                7
584 
                                                0
585
586
587
588 
                                                        std_logic_vector
589 
                                                        xilinx_anylanguagesynthesis
590 
                                                        xilinx_anylanguagebehavioralsimulation
591
592
593
594
595
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                                XGMII_TXD
597
598 
                                        out
599
600 
                                                63
601 
                                                0
602
603
604
605 
                                                        std_logic_vector
606 
                                                        xilinx_anylanguagesynthesis
607 
                                                        xilinx_anylanguagebehavioralsimulation
608
609
610
611
612
613 
                                XGMII_RXC
614
615 
                                        in
616
617 
                                                7
618 
                                                0
619
620
621
622 
                                                        std_logic_vector
623 
                                                        xilinx_anylanguagesynthesis
624 
                                                        xilinx_anylanguagebehavioralsimulation
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626
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                                                0
629
630
631
632
633 
                                XGMII_RXD
634
635 
                                        in
636
637 
                                                63
638 
                                                0
639
640
641
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                                                        std_logic_vector
643 
                                                        xilinx_anylanguagesynthesis
644 
                                                        xilinx_anylanguagebehavioralsimulation
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646
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                                                0
649
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                                        spirit:dataType="integer">
656 
                                g_tx_dfifo_depth
657 
                                G Tx Dfifo Depth
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659 
                                                spirit:resolve="generated"
660 
                                                spirit:id="MODELPARAM_VALUE.g_tx_dfifo_depth">2048
661
662
663 
                                g_tx_tfifo_depth
664 
                                G Tx Tfifo Depth
665
666 
                                                spirit:resolve="generated"
667 
                                                spirit:id="MODELPARAM_VALUE.g_tx_tfifo_depth">128
668
669
670 
                                g_rx_dfifo_depth
671 
                                G Rx Dfifo Depth
672
673 
                                                spirit:resolve="generated"
674 
                                                spirit:id="MODELPARAM_VALUE.g_rx_dfifo_depth">2048
675
676
677 
                                g_rx_tfifo_depth
678 
                                G Rx Tfifo Depth
679
680 
                                                spirit:resolve="generated"
681 
                                                spirit:id="MODELPARAM_VALUE.g_rx_tfifo_depth">128
682
683
684 
                                g_tx_dfifo_type
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                                G Tx Dfifo Type
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                                                spirit:id="MODELPARAM_VALUE.g_tx_dfifo_type">block
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                                g_tx_tfifo_type
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                                G Tx Tfifo Type
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                                                spirit:id="MODELPARAM_VALUE.g_tx_tfifo_type">block
694
695
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                                g_rx_dfifo_type
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                                G Rx Dfifo Type
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                                                spirit:id="MODELPARAM_VALUE.g_rx_dfifo_type">block
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                                g_rx_tfifo_type
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                                G Rx Tfifo Type
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                                                spirit:id="MODELPARAM_VALUE.g_rx_tfifo_type">block
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                        choice_list_91f1634a
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                        block
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                        auto
714 
                        distributed
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717
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                        xilinx_anylanguagesynthesis_view_fileset
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                                src/hdl/math_pack.vhd
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                                vhdlSource
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                                src/hdl/crc/crc32_fast64_tab.vhd
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                                vhdlSource
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                                src/hdl/crc/crc32_fast128_tab.vhd
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                                src/hdl/crc/crc32_fast16_tab.vhd
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                                vhdlSource
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                                src/hdl/crc/crc32_fast8_tab.vhd
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                                vhdlSource
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                                src/hdl/crc/crc32_fast1024_tab.vhd
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                                vhdlSource
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                                src/hdl/crc/crc32_fast24_tab.vhd
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                                vhdlSource
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                                src/hdl/crc/crc32_fast32_tab.vhd
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                                vhdlSource
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                                src/hdl/crc/crc32_fast256_tab.vhd
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                                vhdlSource
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                                src/hdl/crc/crc32_fast512_tab.vhd
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                                vhdlSource
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                                src/hdl/crc/crc32_fast_tab.vhd
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                                vhdlSource
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                                src/hdl/crc/crc32_gen_tab_tree.vhd
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                                vhdlSource
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                                src/hdl/crc/crc32_gen_fsm.vhd
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                                vhdlSource
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                                src/hdl/frame_pkg.vhd
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                                vhdlSource
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                                src/hdl/srl_pkg.vhd
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                                vhdlSource
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                                src/hdl/crc/crc32_gen.vhd
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                                vhdlSource
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                                src/hdl/frame_tx_if.vhd
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                                vhdlSource
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                                src/hdl/frame_throttle.vhd
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                                vhdlSource
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792
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                                src/hdl/frame_gen_fifo_if.vhd
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                                vhdlSource
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                                src/hdl/frame_rx_if.vhd
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                                vhdlSource
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                                src/hdl/frame_process.vhd
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                                vhdlSource
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                                src/hdl/frame_gen.vhd
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                                vhdlSource
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                                src/hdl/frame_receiver.vhd
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                                vhdlSource
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                                src/hdl/udp_ip_10g.vhd
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                                vhdlSource
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                                CHECKSUM_08f45ea1
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819 
                        xilinx_anylanguagesynthesis_xilinx_com_ip_lib_fifo_1_0__ref_view_fileset
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                                                        xilinx:library="ip"
824 
                                                        xilinx:name="lib_fifo"
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                                                        xilinx:version="1.0">
826
827
828
829
830
831
832 
                        xilinx_anylanguagesynthesis_xilinx_com_ip_lib_cdc_1_0__ref_view_fileset
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                                                        xilinx:library="ip"
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                                                        xilinx:name="lib_cdc"
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                                                        xilinx:version="1.0">
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845 
                        xilinx_anylanguagesynthesis_xilinx_com_ip_lib_pkg_1_0__ref_view_fileset
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                                                        xilinx:library="ip"
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                                                        xilinx:name="lib_pkg"
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                                                        xilinx:version="1.0">
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854
855
856
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                        xilinx_anylanguagesynthesis_xilinx_com_ip_lib_srl_fifo_1_0__ref_view_fileset
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862 
                                                        xilinx:library="ip"
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                                                        xilinx:name="lib_srl_fifo"
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                                                        xilinx:version="1.0">
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866
867
868
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870
871 
                        xilinx_anylanguagebehavioralsimulation_view_fileset
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                                vhdlSource
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                                vhdlSource
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                                vhdlSource
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                                vhdlSource
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                                src/hdl/crc/crc32_fast8_tab.vhd
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                                vhdlSource
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                                vhdlSource
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                                src/hdl/crc/crc32_fast24_tab.vhd
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                                vhdlSource
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                                src/hdl/crc/crc32_fast32_tab.vhd
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                                vhdlSource
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                                src/hdl/crc/crc32_fast256_tab.vhd
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                                vhdlSource
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                                src/hdl/crc/crc32_fast512_tab.vhd
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                                vhdlSource
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                                src/hdl/crc/crc32_fast_tab.vhd
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                                src/hdl/crc/crc32_gen_tab_tree.vhd
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                                vhdlSource
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                                src/hdl/crc/crc32_gen_fsm.vhd
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                                vhdlSource
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                                src/hdl/frame_pkg.vhd
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                                vhdlSource
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                                vhdlSource
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                                vhdlSource
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                                vhdlSource
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                                vhdlSource
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                                vhdlSource
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                                vhdlSource
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                                src/hdl/frame_gen.vhd
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                                vhdlSource
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                                src/hdl/frame_receiver.vhd
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                                vhdlSource
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                                src/hdl/udp_ip_10g.vhd
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                                vhdlSource
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                        xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_lib_fifo_1_0__ref_view_fileset
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                                                        xilinx:library="ip"
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                                                        xilinx:name="lib_fifo"
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                        xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_lib_cdc_1_0__ref_view_fileset
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995
996 
                        xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_lib_pkg_1_0__ref_view_fileset
997
998
999
1000 
                                                        xilinx:library="ip"
1001 
                                                        xilinx:name="lib_pkg"
1002 
                                                        xilinx:version="1.0">
1003
1004
1005
1006
1007
1008
1009 
                        xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_lib_srl_fifo_1_0__ref_view_fileset
1010
1011
1012
1013 
                                                        xilinx:library="ip"
1014 
                                                        xilinx:name="lib_srl_fifo"
1015 
                                                        xilinx:version="1.0">
1016
1017
1018
1019
1020
1021
1022 
                        xilinx_xpgui_view_fileset
1023
1024 
                                xgui/udp_ip_10g_v1_0.tcl
1025 
                                tclSource
1026 
                                CHECKSUM_a48910cf
1027 
                                XGUI_VERSION_2
1028
1029
1030
1031 
        UDP/IPv4 core for 10 Gbps Ethernet. Six link speeds are supported - 10 Gbps, 5 Gbps, 2.5 Gbps, 1 Gbps, 100 Mbps, 10 Mbps  - (full-duplex only).
1032
1033
1034 
                        Component_Name
1035
1036 
                                        spirit:id="PARAM_VALUE.Component_Name"
1037 
                                        spirit:order="1">udp_ip_10g_v1_0
1038
1039
1040 
                        g_tx_dfifo_depth
1041 
                        Tx data FIFO depth
1042
1043 
                                        spirit:resolve="user"
1044 
                                        spirit:id="PARAM_VALUE.g_tx_dfifo_depth">2048
1045
1046
1047 
                        g_tx_tfifo_depth
1048 
                        Tx tag FIFO depth
1049
1050 
                                        spirit:resolve="user"
1051 
                                        spirit:id="PARAM_VALUE.g_tx_tfifo_depth">128
1052
1053
1054 
                        g_rx_dfifo_depth
1055 
                        Rx data FIFO depth
1056
1057 
                                        spirit:resolve="user"
1058 
                                        spirit:id="PARAM_VALUE.g_rx_dfifo_depth">2048
1059
1060
1061 
                        g_rx_tfifo_depth
1062 
                        Rx tag FIFO depth
1063
1064 
                                        spirit:resolve="user"
1065 
                                        spirit:id="PARAM_VALUE.g_rx_tfifo_depth">128
1066
1067
1068 
                        g_tx_dfifo_type
1069 
                        Memory type for TX data FIFO
1070
1071 
                                        spirit:id="PARAM_VALUE.g_tx_dfifo_type"
1072 
                                        spirit:choiceRef="choice_list_91f1634a">block
1073
1074
1075 
                        g_tx_tfifo_type
1076 
                        Memory type for TX tag FIFO
1077
1078 
                                        spirit:id="PARAM_VALUE.g_tx_tfifo_type"
1079 
                                        spirit:choiceRef="choice_list_91f1634a">block
1080
1081
1082 
                        g_rx_dfifo_type
1083 
                        Memory type for RX data FIFO
1084
1085 
                                        spirit:id="PARAM_VALUE.g_rx_dfifo_type"
1086 
                                        spirit:choiceRef="choice_list_91f1634a">block
1087
1088
1089 
                        g_rx_tfifo_type
1090 
                        Memory type for RX tag FIFO
1091
1092 
                                        spirit:id="PARAM_VALUE.g_rx_tfifo_type"
1093 
                                        spirit:choiceRef="choice_list_91f1634a">block
1094
1095
1096
1097
1098
1099 
                                kintex7
1100
1101
1102 
                                /UserIP
1103
1104 
                        UDP/IP
1105 
                        package_project
1106
1107 
                                XPM_CDC
1108 
                                XPM_MEMORY
1109
1110 
                        DFC Design, s.r.o.
1111 
                        http://www.dfcdesign.cz
1112 
                        3
1113 
                        2017-04-18T09:56:50Z
1114
1115 
                                c:/projects/dfc/xenie/ip_repo_dev/udp_ip_10g/trunk
1116 
                                c:/projects/dfc/xenie/ip_repo_dev/udp_ip_10g/trunk
1117 
                                c:/projects/dfc/xenie/ip_repo_dev/udp_ip_10g/trunk
1118
1119
1120
1121 
                        2016.4
1122
1123 
                                        xilinx:value="f9e4054d"/>
1124
1125 
                                        xilinx:value="a1e708f3"/>
1126
1127 
                                        xilinx:value="930b2e64"/>
1128
1129 
                                        xilinx:value="629d0888"/>
1130
1131 
                                        xilinx:value="d6ef4370"/>
1132
1133
1134

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