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ZTEX |
/*!
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memfifo -- implementation of EZ-USB slave FIFO's (input and output) a FIFO using the DDR3 SDRAM for ZTEX USB-FPGA Modules 2.13
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Copyright (C) 2009-2014 ZTEX GmbH.
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http://www.ztex.de
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License version 3 as
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published by the Free Software Foundation.
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This program is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, see http://www.gnu.org/licenses/.
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!*/
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/*
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Implements a huge FIFO from all SDRAM.
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*/
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module fifo_512x128 #(
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parameter ALMOST_EMPTY_OFFSET1 = 13'h0020, // Sets the almost empty threshold
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parameter ALMOST_EMPTY_OFFSET2 = 13'h0006, // Sets the almost empty threshold
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parameter ALMOST_FULL_OFFSET1 = 13'h0020, // Sets almost full threshold
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parameter ALMOST_FULL_OFFSET2 = 13'h0006, // Sets almost full threshold
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parameter FIRST_WORD_FALL_THROUGH = "TRUE" // Sets the FIFO FWFT to FALSE, TRUE
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) (
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input RST, // 1-bit input: Reset
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// input signals
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input [127:0] DI, // 64-bit input: Data input
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output FULL, // 1-bit output: Full flag
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output ALMOSTFULL1, // 1-bit output: Almost full flag
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output ALMOSTFULL2, // 1-bit output: Almost full flag
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output WRERR, // 1-bit output: Write error
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input WRCLK, // 1-bit input: Rising edge write clock.
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input WREN, // 1-bit input: Write enable
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// output signals
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output [127:0] DO,
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output EMPTY, // 1-bit output: Empty flag
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output ALMOSTEMPTY1, // 1-bit output: Almost empty flag
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output ALMOSTEMPTY2, // 1-bit output: Almost empty flag
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output RDERR, // 1-bit output: Read error
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input RDCLK, // 1-bit input: Read clock
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input RDEN // 1-bit input: Read enable
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);
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FIFO36E1 #(
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.ALMOST_EMPTY_OFFSET(ALMOST_EMPTY_OFFSET1),
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.ALMOST_FULL_OFFSET(ALMOST_FULL_OFFSET1),
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.DATA_WIDTH(72),
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.DO_REG(1),
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.EN_ECC_READ("TRUE"),
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.EN_ECC_WRITE("TRUE"),
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.EN_SYN("FALSE"),
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.FIFO_MODE("FIFO36_72"),
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.FIRST_WORD_FALL_THROUGH(FIRST_WORD_FALL_THROUGH),
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.INIT(72'h000000000000000000),
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.SIM_DEVICE("7SERIES"),
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.SRVAL(72'h000000000000000000)
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)
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U (
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.DBITERR(),
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.ECCPARITY(),
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.SBITERR(),
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.DO(DO[127:64]),
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.DOP(),
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.ALMOSTEMPTY(ALMOSTEMPTY1),
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.ALMOSTFULL(ALMOSTFULL1),
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.EMPTY(EMPTY_U),
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.FULL(FULL_U),
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.RDCOUNT(),
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.RDERR(RDERR_U),
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.WRCOUNT(),
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.WRERR(WRERR_U),
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.INJECTDBITERR(1'b0),
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.INJECTSBITERR(1'b0),
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.RDCLK(RDCLK),
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.RDEN(RDEN),
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.REGCE(1'b0),
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.RST(RST),
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.RSTREG(1'b0),
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.WRCLK(WRCLK),
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.WREN(WREN),
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.DI(DI[127:64]),
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.DIP(4'd0)
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);
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FIFO36E1 #(
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.ALMOST_EMPTY_OFFSET(ALMOST_EMPTY_OFFSET2),
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.ALMOST_FULL_OFFSET(ALMOST_FULL_OFFSET2),
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.DATA_WIDTH(72),
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.DO_REG(1),
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.EN_ECC_READ("TRUE"),
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.EN_ECC_WRITE("TRUE"),
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.EN_SYN("FALSE"),
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.FIFO_MODE("FIFO36_72"),
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.FIRST_WORD_FALL_THROUGH(FIRST_WORD_FALL_THROUGH),
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.INIT(72'h000000000000000000),
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.SIM_DEVICE("7SERIES"),
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.SRVAL(72'h000000000000000000)
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)
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L (
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.DBITERR(),
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.ECCPARITY(),
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.SBITERR(),
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.DO(DO[63:0]),
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.DOP(),
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.ALMOSTEMPTY(ALMOSTEMPTY2),
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.ALMOSTFULL(ALMOSTFULL2),
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.EMPTY(EMPTY_L),
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.FULL(FULL_L),
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.RDCOUNT(),
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.RDERR(RDERR_L),
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.WRCOUNT(),
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.WRERR(WRERR_L),
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.INJECTDBITERR(1'b0),
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.INJECTSBITERR(1'b0),
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.RDCLK(RDCLK),
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.RDEN(RDEN),
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.REGCE(1'b0),
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.RST(RST),
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.RSTREG(1'b0),
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.WRCLK(WRCLK),
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.WREN(WREN),
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.DI(DI[63:0]),
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.DIP(4'd0)
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);
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assign EMPTY = EMPTY_U || EMPTY_L;
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assign FULL = FULL_U || FULL_L;
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assign RDERR = RDERR_U || RDERR_L;
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assign WRERR = WRERR_U || WRERR_L;
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endmodule
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module dram_fifo # (
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// fifo parameters, see "7 Series Memory Resources" user guide (ug743)
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parameter ALMOST_EMPTY_OFFSET1 = 13'h0010, // Sets the almost empty threshold
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parameter ALMOST_EMPTY_OFFSET2 = 13'h0001, // Sets the almost empty threshold
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parameter ALMOST_FULL_OFFSET1 = 13'h0010, // Sets almost full threshold
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parameter ALMOST_FULL_OFFSET2 = 13'h0001, // Sets almost full threshold
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parameter FIRST_WORD_FALL_THROUGH = "TRUE", // Sets the FIFO FWFT to FALSE, TRUE
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// clock dividers for PLL outputs not used for memory interface, VCO frequency is 1200 MHz
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parameter CLKOUT2_DIVIDE = 1,
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parameter CLKOUT3_DIVIDE = 1,
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parameter CLKOUT4_DIVIDE = 1,
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parameter CLKOUT5_DIVIDE = 1,
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parameter CLKOUT2_PHASE = 0.0,
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parameter CLKOUT3_PHASE = 0.0,
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parameter CLKOUT4_PHASE = 0.0,
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parameter CLKOUT5_PHASE = 0.0
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) (
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input fxclk_in, // 48 MHz input clock pin
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input reset,
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output reset_out, // reset output
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output clkout2, clkout3, clkout4, clkout5, // PLL clock outputs not used for memory interface
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// ddr3 pins
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inout [15:0] ddr3_dq,
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inout [1:0] ddr3_dqs_n,
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inout [1:0] ddr3_dqs_p,
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output [13:0] ddr3_addr,
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output [2:0] ddr3_ba,
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output ddr3_ras_n,
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output ddr3_cas_n,
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output ddr3_we_n,
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output ddr3_reset_n,
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output [0:0] ddr3_ck_p,
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output [0:0] ddr3_ck_n,
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output [0:0] ddr3_cke,
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output [1:0] ddr3_dm,
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output [0:0] ddr3_odt,
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// input fifo interface, see "7 Series Memory Resources" user guide (ug743)
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input [127:0] DI, // 64-bit input: Data input
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output FULL, // 1-bit output: Full flag
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output ALMOSTFULL1, // 1-bit output: Almost full flag
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output ALMOSTFULL2, // 1-bit output: Almost full flag
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output WRERR, // 1-bit output: Write error
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input WRCLK, // 1-bit input: Rising edge write clock.
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input WREN, // 1-bit input: Write enable
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// output fifo interface, see "7 Series Memory Resources" user guide (ug743)
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output [127:0] DO,
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output EMPTY, // 1-bit output: Empty flag
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output ALMOSTEMPTY1, // 1-bit output: Almost empty flag
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output ALMOSTEMPTY2, // 1-bit output: Almost empty flag
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output RDERR, // 1-bit output: Read error
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input RDCLK, // 1-bit input: Read clock
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input RDEN, // 1-bit input: Read enable
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// free memory
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output [APP_ADDR_WIDTH:0] mem_free_out,
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// for debugging
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output [9:0] status
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);
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localparam APP_DATA_WIDTH = 128;
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localparam APP_MASK_WIDTH = 16;
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localparam APP_ADDR_WIDTH = 24;
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wire pll_fb, clk200_in, clk67_in, clk200, clk67, uiclk, fxclk;
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wire mem_reset, ui_clk_sync_rst, init_calib_complete;
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reg reset_buf;
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// memory control
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reg [7:0] wr_cnt, rd_cnt;
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reg [APP_ADDR_WIDTH-1:0] mem_wr_addr, mem_rd_addr;
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reg [APP_ADDR_WIDTH:0] mem_free;
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reg rd_mode, wr_mode_buf;
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wire wr_mode;
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// fifo control
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wire infifo_empty, infifo_almost_empty, outfifo_almost_full, infifo_rden;
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wire [APP_DATA_WIDTH-1:0] infifo_do;
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reg [5:0] outfifo_pending;
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reg [9:0] rd_cnt_dbg;
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// debug
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wire infifo_err_w, outfifo_err_w;
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reg infifo_err, outfifo_err, outfifo_err_uf;
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// memory interface
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reg [APP_ADDR_WIDTH-1:0] app_addr;
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reg [2:0] app_cmd;
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reg app_en, app_wdf_wren;
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wire app_rdy, app_wdf_rdy, app_rd_data_valid;
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reg [APP_DATA_WIDTH-1:0] app_wdf_data;
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wire [APP_DATA_WIDTH-1:0] app_rd_data;
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BUFG fxclk_buf (
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.I(fxclk_in),
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.O(fxclk)
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);
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PLLE2_BASE #(
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.BANDWIDTH("LOW"),
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.CLKFBOUT_MULT(25), // f_VCO = 1200 MHz (valid: 800 .. 1600 MHz)
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.CLKFBOUT_PHASE(0.0),
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.CLKIN1_PERIOD(0.0),
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.CLKOUT0_DIVIDE(18), // 66.666 MHz
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.CLKOUT1_DIVIDE(6), // 200 MHz
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.CLKOUT2_DIVIDE(CLKOUT2_DIVIDE),
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.CLKOUT3_DIVIDE(CLKOUT3_DIVIDE),
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.CLKOUT4_DIVIDE(CLKOUT4_DIVIDE),
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.CLKOUT5_DIVIDE(CLKOUT5_DIVIDE),
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.CLKOUT0_DUTY_CYCLE(0.5),
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.CLKOUT1_DUTY_CYCLE(0.5),
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.CLKOUT2_DUTY_CYCLE(0.5),
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.CLKOUT3_DUTY_CYCLE(0.5),
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.CLKOUT4_DUTY_CYCLE(0.5),
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.CLKOUT5_DUTY_CYCLE(0.5),
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.CLKOUT0_PHASE(0.0),
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.CLKOUT1_PHASE(0.0),
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.CLKOUT2_PHASE(CLKOUT2_PHASE),
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.CLKOUT3_PHASE(CLKOUT3_PHASE),
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.CLKOUT4_PHASE(CLKOUT4_PHASE),
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.CLKOUT5_PHASE(CLKOUT5_PHASE),
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.DIVCLK_DIVIDE(1),
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.REF_JITTER1(0.0),
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.STARTUP_WAIT("FALSE")
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)
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dram_fifo_pll_inst (
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.CLKIN1(fxclk),
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.CLKOUT0(clk67),
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.CLKOUT1(clk200),
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.CLKOUT2(clkout2),
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.CLKOUT3(clkout3),
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.CLKOUT4(clkout4),
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.CLKOUT5(clkout5),
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.CLKFBOUT(pll_fb),
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.CLKFBIN(pll_fb),
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.PWRDWN(1'b0),
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.RST(1'b0)
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);
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fifo_512x128 #(
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.ALMOST_EMPTY_OFFSET1(13'h0026),
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.ALMOST_EMPTY_OFFSET2(13'h0006),
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.ALMOST_FULL_OFFSET1(ALMOST_FULL_OFFSET1),
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.ALMOST_FULL_OFFSET2(ALMOST_FULL_OFFSET2),
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.FIRST_WORD_FALL_THROUGH("TRUE")
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) infifo (
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.RST(reset_buf),
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// output
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.DO(infifo_do),
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.EMPTY(infifo_empty),
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.ALMOSTEMPTY1(infifo_almost_empty),
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.ALMOSTEMPTY2(),
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.RDERR(infifo_err_w),
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.RDCLK(uiclk),
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.RDEN(infifo_rden),
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// input
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.DI(DI),
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.FULL(FULL),
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.ALMOSTFULL1(ALMOSTFULL1),
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.ALMOSTFULL2(ALMOSTFULL2),
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.WRERR(WRERR),
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.WRCLK(WRCLK),
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.WREN(WREN)
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);
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fifo_512x128 #(
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.ALMOST_FULL_OFFSET1(13'h0044),
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.ALMOST_FULL_OFFSET2(13'h0004),
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.ALMOST_EMPTY_OFFSET1(ALMOST_EMPTY_OFFSET1),
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.ALMOST_EMPTY_OFFSET2(ALMOST_EMPTY_OFFSET2),
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.FIRST_WORD_FALL_THROUGH(FIRST_WORD_FALL_THROUGH)
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) outfifo (
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.RST(reset_buf),
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// output
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.DO(DO),
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.EMPTY(EMPTY),
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.ALMOSTEMPTY1(ALMOSTEMPTY1),
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.ALMOSTEMPTY2(ALMOSTEMPTY2),
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.RDERR(RDERR),
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.RDCLK(RDCLK),
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.RDEN(RDEN),
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// input
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.DI(app_rd_data),
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.FULL(),
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.ALMOSTFULL1(outfifo_almost_full),
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|
.ALMOSTFULL2(),
|
328 |
|
|
.WRERR(outfifo_err_w),
|
329 |
|
|
.WRCLK(uiclk),
|
330 |
|
|
.WREN(app_rd_data_valid)
|
331 |
|
|
);
|
332 |
|
|
|
333 |
|
|
mig_7series_0 # (
|
334 |
|
|
//***************************************************************************
|
335 |
|
|
// The following parameters refer to width of various ports
|
336 |
|
|
//***************************************************************************
|
337 |
|
|
.BANK_WIDTH (3),
|
338 |
|
|
// # of memory Bank Address bits.
|
339 |
|
|
.CK_WIDTH (1),
|
340 |
|
|
// # of CK/CK# outputs to memory.
|
341 |
|
|
.COL_WIDTH (10),
|
342 |
|
|
// # of memory Column Address bits.
|
343 |
|
|
.CS_WIDTH (1),
|
344 |
|
|
// # of unique CS outputs to memory.
|
345 |
|
|
.nCS_PER_RANK (1),
|
346 |
|
|
// # of unique CS outputs per rank for phy
|
347 |
|
|
.CKE_WIDTH (1),
|
348 |
|
|
// # of CKE outputs to memory.
|
349 |
|
|
.DATA_BUF_ADDR_WIDTH (5),
|
350 |
|
|
.DQ_CNT_WIDTH (4),
|
351 |
|
|
// = ceil(log2(DQ_WIDTH))
|
352 |
|
|
.DQ_PER_DM (8),
|
353 |
|
|
.DM_WIDTH (2),
|
354 |
|
|
// # of DM (data mask)
|
355 |
|
|
.DQ_WIDTH (16),
|
356 |
|
|
// # of DQ (data)
|
357 |
|
|
.DQS_WIDTH (2),
|
358 |
|
|
.DQS_CNT_WIDTH (1),
|
359 |
|
|
// = ceil(log2(DQS_WIDTH))
|
360 |
|
|
.DRAM_WIDTH (8),
|
361 |
|
|
// # of DQ per DQS
|
362 |
|
|
.ECC ("OFF"),
|
363 |
|
|
.DATA_WIDTH (16),
|
364 |
|
|
.ECC_TEST ("OFF"),
|
365 |
|
|
.PAYLOAD_WIDTH (16),
|
366 |
|
|
.nBANK_MACHS (4),
|
367 |
|
|
.RANKS (1),
|
368 |
|
|
// # of Ranks.
|
369 |
|
|
.ODT_WIDTH (1),
|
370 |
|
|
// # of ODT outputs to memory.
|
371 |
|
|
.ROW_WIDTH (14),
|
372 |
|
|
// # of memory Row Address bits.
|
373 |
|
|
.ADDR_WIDTH (28),
|
374 |
|
|
// # = RANK_WIDTH + BANK_WIDTH
|
375 |
|
|
// + ROW_WIDTH + COL_WIDTH;
|
376 |
|
|
// Chip Select is always tied to low for
|
377 |
|
|
// single rank devices
|
378 |
|
|
.USE_CS_PORT (0),
|
379 |
|
|
// # = 1, When Chip Select (CS#) output is enabled
|
380 |
|
|
// = 0, When Chip Select (CS#) output is disabled
|
381 |
|
|
// If CS_N disabled, user must connect
|
382 |
|
|
// DRAM CS_N input(s) to ground
|
383 |
|
|
.USE_DM_PORT (1),
|
384 |
|
|
// # = 1, When Data Mask option is enabled
|
385 |
|
|
// = 0, When Data Mask option is disbaled
|
386 |
|
|
// When Data Mask option is disabled in
|
387 |
|
|
// MIG Controller Options page, the logic
|
388 |
|
|
// related to Data Mask should not get
|
389 |
|
|
// synthesized
|
390 |
|
|
.USE_ODT_PORT (1),
|
391 |
|
|
// # = 1, When ODT output is enabled
|
392 |
|
|
// = 0, When ODT output is disabled
|
393 |
|
|
.PHY_CONTROL_MASTER_BANK (0),
|
394 |
|
|
// The bank index where master PHY_CONTROL resides,
|
395 |
|
|
// equal to the PLL residing bank
|
396 |
|
|
|
397 |
|
|
//***************************************************************************
|
398 |
|
|
// The following parameters are mode register settings
|
399 |
|
|
//***************************************************************************
|
400 |
|
|
.AL ("0"),
|
401 |
|
|
// DDR3 SDRAM:
|
402 |
|
|
// Additive Latency (Mode Register 1).
|
403 |
|
|
// # = "0", "CL-1", "CL-2".
|
404 |
|
|
// DDR2 SDRAM:
|
405 |
|
|
// Additive Latency (Extended Mode Register).
|
406 |
|
|
.nAL (0),
|
407 |
|
|
// # Additive Latency in number of clock
|
408 |
|
|
// cycles.
|
409 |
|
|
.BURST_MODE ("8"),
|
410 |
|
|
// DDR3 SDRAM:
|
411 |
|
|
// Burst Length (Mode Register 0).
|
412 |
|
|
// # = "8", "4", "OTF".
|
413 |
|
|
// DDR2 SDRAM:
|
414 |
|
|
// Burst Length (Mode Register).
|
415 |
|
|
// # = "8", "4".
|
416 |
|
|
.BURST_TYPE ("SEQ"),
|
417 |
|
|
// DDR3 SDRAM: Burst Type (Mode Register 0).
|
418 |
|
|
// DDR2 SDRAM: Burst Type (Mode Register).
|
419 |
|
|
// # = "SEQ" - (Sequential),
|
420 |
|
|
// = "INT" - (Interleaved).
|
421 |
|
|
.CL (7),
|
422 |
|
|
// in number of clock cycles
|
423 |
|
|
// DDR3 SDRAM: CAS Latency (Mode Register 0).
|
424 |
|
|
// DDR2 SDRAM: CAS Latency (Mode Register).
|
425 |
|
|
.CWL (6),
|
426 |
|
|
// in number of clock cycles
|
427 |
|
|
// DDR3 SDRAM: CAS Write Latency (Mode Register 2).
|
428 |
|
|
// DDR2 SDRAM: Can be ignored
|
429 |
|
|
.OUTPUT_DRV ("HIGH"),
|
430 |
|
|
// Output Driver Impedance Control (Mode Register 1).
|
431 |
|
|
// # = "HIGH" - RZQ/7,
|
432 |
|
|
// = "LOW" - RZQ/6.
|
433 |
|
|
.RTT_NOM ("40"),
|
434 |
|
|
// RTT_NOM (ODT) (Mode Register 1).
|
435 |
|
|
// # = "DISABLED" - RTT_NOM disabled,
|
436 |
|
|
// = "120" - RZQ/2,
|
437 |
|
|
// = "60" - RZQ/4,
|
438 |
|
|
// = "40" - RZQ/6.
|
439 |
|
|
.RTT_WR ("OFF"),
|
440 |
|
|
// RTT_WR (ODT) (Mode Register 2).
|
441 |
|
|
// # = "OFF" - Dynamic ODT off,
|
442 |
|
|
// = "120" - RZQ/2,
|
443 |
|
|
// = "60" - RZQ/4,
|
444 |
|
|
.ADDR_CMD_MODE ("1T" ),
|
445 |
|
|
// # = "1T", "2T".
|
446 |
|
|
.REG_CTRL ("OFF"),
|
447 |
|
|
// # = "ON" - RDIMMs,
|
448 |
|
|
// = "OFF" - Components, SODIMMs, UDIMMs.
|
449 |
|
|
.CA_MIRROR ("OFF"),
|
450 |
|
|
// C/A mirror opt for DDR3 dual rank
|
451 |
|
|
|
452 |
|
|
//***************************************************************************
|
453 |
|
|
// The following parameters are multiplier and divisor factors for PLLE2.
|
454 |
|
|
// Based on the selected design frequency these parameters vary.
|
455 |
|
|
//***************************************************************************
|
456 |
|
|
.CLKIN_PERIOD (15000),
|
457 |
|
|
// Input Clock Period
|
458 |
|
|
.CLKFBOUT_MULT (12),
|
459 |
|
|
// write PLL VCO multiplier
|
460 |
|
|
.DIVCLK_DIVIDE (1),
|
461 |
|
|
// write PLL VCO divisor
|
462 |
|
|
.CLKOUT0_DIVIDE (1),
|
463 |
|
|
// VCO output divisor for PLL output clock (CLKOUT0)
|
464 |
|
|
.CLKOUT1_DIVIDE (2),
|
465 |
|
|
// VCO output divisor for PLL output clock (CLKOUT1)
|
466 |
|
|
.CLKOUT2_DIVIDE (32),
|
467 |
|
|
// VCO output divisor for PLL output clock (CLKOUT2)
|
468 |
|
|
.CLKOUT3_DIVIDE (8),
|
469 |
|
|
// VCO output divisor for PLL output clock (CLKOUT3)
|
470 |
|
|
|
471 |
|
|
//***************************************************************************
|
472 |
|
|
// Memory Timing Parameters. These parameters varies based on the selected
|
473 |
|
|
// memory part.
|
474 |
|
|
//***************************************************************************
|
475 |
|
|
.tCKE (5000),
|
476 |
|
|
// memory tCKE paramter in pS.
|
477 |
|
|
.tFAW (40000),
|
478 |
|
|
// memory tRAW paramter in pS.
|
479 |
|
|
.tPRDI (1_000_000),
|
480 |
|
|
// memory tPRDI paramter in pS.
|
481 |
|
|
.tRAS (35000),
|
482 |
|
|
// memory tRAS paramter in pS.
|
483 |
|
|
.tRCD (13750),
|
484 |
|
|
// memory tRCD paramter in pS.
|
485 |
|
|
.tREFI (7800000),
|
486 |
|
|
// memory tREFI paramter in pS.
|
487 |
|
|
.tRFC (160000),
|
488 |
|
|
// memory tRFC paramter in pS.
|
489 |
|
|
.tRP (13750),
|
490 |
|
|
// memory tRP paramter in pS.
|
491 |
|
|
.tRRD (7500),
|
492 |
|
|
// memory tRRD paramter in pS.
|
493 |
|
|
.tRTP (7500),
|
494 |
|
|
// memory tRTP paramter in pS.
|
495 |
|
|
.tWTR (7500),
|
496 |
|
|
// memory tWTR paramter in pS.
|
497 |
|
|
.tZQI (128_000_000),
|
498 |
|
|
// memory tZQI paramter in nS.
|
499 |
|
|
.tZQCS (64),
|
500 |
|
|
// memory tZQCS paramter in clock cycles.
|
501 |
|
|
|
502 |
|
|
//***************************************************************************
|
503 |
|
|
// Simulation parameters
|
504 |
|
|
//***************************************************************************
|
505 |
|
|
.SIM_BYPASS_INIT_CAL ("OFF"),
|
506 |
|
|
// # = "OFF" - Complete memory init &
|
507 |
|
|
// calibration sequence
|
508 |
|
|
// # = "SKIP" - Not supported
|
509 |
|
|
// # = "FAST" - Complete memory init & use
|
510 |
|
|
// abbreviated calib sequence
|
511 |
|
|
.SIMULATION ("FALSE"),
|
512 |
|
|
// Should be TRUE during design simulations and
|
513 |
|
|
// FALSE during implementations
|
514 |
|
|
|
515 |
|
|
//***************************************************************************
|
516 |
|
|
// The following parameters varies based on the pin out entered in MIG GUI.
|
517 |
|
|
// Do not change any of these parameters directly by editing the RTL.
|
518 |
|
|
// Any changes required should be done through GUI and the design regenerated.
|
519 |
|
|
//***************************************************************************
|
520 |
|
|
.BYTE_LANES_B0 (4'b1111),
|
521 |
|
|
// Byte lanes used in an IO column.
|
522 |
|
|
.BYTE_LANES_B1 (4'b0000),
|
523 |
|
|
// Byte lanes used in an IO column.
|
524 |
|
|
.BYTE_LANES_B2 (4'b0000),
|
525 |
|
|
// Byte lanes used in an IO column.
|
526 |
|
|
.BYTE_LANES_B3 (4'b0000),
|
527 |
|
|
// Byte lanes used in an IO column.
|
528 |
|
|
.BYTE_LANES_B4 (4'b0000),
|
529 |
|
|
// Byte lanes used in an IO column.
|
530 |
|
|
.DATA_CTL_B0 (4'b0011),
|
531 |
|
|
// Indicates Byte lane is data byte lane
|
532 |
|
|
// or control Byte lane. '1' in a bit
|
533 |
|
|
// position indicates a data byte lane and
|
534 |
|
|
// a '0' indicates a control byte lane
|
535 |
|
|
.DATA_CTL_B1 (4'b0000),
|
536 |
|
|
// Indicates Byte lane is data byte lane
|
537 |
|
|
// or control Byte lane. '1' in a bit
|
538 |
|
|
// position indicates a data byte lane and
|
539 |
|
|
// a '0' indicates a control byte lane
|
540 |
|
|
.DATA_CTL_B2 (4'b0000),
|
541 |
|
|
// Indicates Byte lane is data byte lane
|
542 |
|
|
// or control Byte lane. '1' in a bit
|
543 |
|
|
// position indicates a data byte lane and
|
544 |
|
|
// a '0' indicates a control byte lane
|
545 |
|
|
.DATA_CTL_B3 (4'b0000),
|
546 |
|
|
// Indicates Byte lane is data byte lane
|
547 |
|
|
// or control Byte lane. '1' in a bit
|
548 |
|
|
// position indicates a data byte lane and
|
549 |
|
|
// a '0' indicates a control byte lane
|
550 |
|
|
.DATA_CTL_B4 (4'b0000),
|
551 |
|
|
// Indicates Byte lane is data byte lane
|
552 |
|
|
// or control Byte lane. '1' in a bit
|
553 |
|
|
// position indicates a data byte lane and
|
554 |
|
|
// a '0' indicates a control byte lane
|
555 |
|
|
|
556 |
|
|
.PHY_0_BITLANES (48'hFFF_CFF_3DF_2FF),
|
557 |
|
|
.PHY_1_BITLANES (48'h000_000_000_000),
|
558 |
|
|
.PHY_2_BITLANES (48'h000_000_000_000),
|
559 |
|
|
.CK_BYTE_MAP (144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_02),
|
560 |
|
|
.ADDR_MAP (192'h000_000_037_025_03A_024_035_03B_039_027_031_026_023_034_036_038),
|
561 |
|
|
.BANK_MAP (36'h033_02A_032),
|
562 |
|
|
.CAS_MAP (12'h020),
|
563 |
|
|
.CKE_ODT_BYTE_MAP (8'h00),
|
564 |
|
|
.CKE_MAP (96'h000_000_000_000_000_000_000_02B),
|
565 |
|
|
.ODT_MAP (96'h000_000_000_000_000_000_000_030),
|
566 |
|
|
.CS_MAP (120'h000_000_000_000_000_000_000_000_000_000),
|
567 |
|
|
.PARITY_MAP (12'h000),
|
568 |
|
|
.RAS_MAP (12'h021),
|
569 |
|
|
.WE_MAP (12'h022),
|
570 |
|
|
.DQS_BYTE_MAP (144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_01),
|
571 |
|
|
.DATA0_MAP (96'h016_018_014_019_010_017_011_013),
|
572 |
|
|
.DATA1_MAP (96'h003_002_005_004_001_006_000_007),
|
573 |
|
|
.DATA2_MAP (96'h000_000_000_000_000_000_000_000),
|
574 |
|
|
.DATA3_MAP (96'h000_000_000_000_000_000_000_000),
|
575 |
|
|
.DATA4_MAP (96'h000_000_000_000_000_000_000_000),
|
576 |
|
|
.DATA5_MAP (96'h000_000_000_000_000_000_000_000),
|
577 |
|
|
.DATA6_MAP (96'h000_000_000_000_000_000_000_000),
|
578 |
|
|
.DATA7_MAP (96'h000_000_000_000_000_000_000_000),
|
579 |
|
|
.DATA8_MAP (96'h000_000_000_000_000_000_000_000),
|
580 |
|
|
.DATA9_MAP (96'h000_000_000_000_000_000_000_000),
|
581 |
|
|
.DATA10_MAP (96'h000_000_000_000_000_000_000_000),
|
582 |
|
|
.DATA11_MAP (96'h000_000_000_000_000_000_000_000),
|
583 |
|
|
.DATA12_MAP (96'h000_000_000_000_000_000_000_000),
|
584 |
|
|
.DATA13_MAP (96'h000_000_000_000_000_000_000_000),
|
585 |
|
|
.DATA14_MAP (96'h000_000_000_000_000_000_000_000),
|
586 |
|
|
.DATA15_MAP (96'h000_000_000_000_000_000_000_000),
|
587 |
|
|
.DATA16_MAP (96'h000_000_000_000_000_000_000_000),
|
588 |
|
|
.DATA17_MAP (96'h000_000_000_000_000_000_000_000),
|
589 |
|
|
.MASK0_MAP (108'h000_000_000_000_000_000_000_009_012),
|
590 |
|
|
.MASK1_MAP (108'h000_000_000_000_000_000_000_000_000),
|
591 |
|
|
|
592 |
|
|
.SLOT_0_CONFIG (8'b0000_0001),
|
593 |
|
|
// Mapping of Ranks.
|
594 |
|
|
.SLOT_1_CONFIG (8'b0000_0000),
|
595 |
|
|
// Mapping of Ranks.
|
596 |
|
|
.MEM_ADDR_ORDER ("BANK_ROW_COLUMN"),
|
597 |
|
|
//***************************************************************************
|
598 |
|
|
// IODELAY and PHY related parameters
|
599 |
|
|
//***************************************************************************
|
600 |
|
|
.IBUF_LPWR_MODE ("OFF"),
|
601 |
|
|
// to phy_top
|
602 |
|
|
.DATA_IO_IDLE_PWRDWN ("ON"),
|
603 |
|
|
// # = "ON", "OFF"
|
604 |
|
|
.DATA_IO_PRIM_TYPE ("HR_LP"),
|
605 |
|
|
// # = "HP_LP", "HR_LP", "DEFAULT"
|
606 |
|
|
.CKE_ODT_AUX ("FALSE"),
|
607 |
|
|
.USER_REFRESH ("OFF"),
|
608 |
|
|
.WRLVL ("ON"),
|
609 |
|
|
// # = "ON" - DDR3 SDRAM
|
610 |
|
|
// = "OFF" - DDR2 SDRAM.
|
611 |
|
|
.ORDERING ("NORM"),
|
612 |
|
|
// # = "NORM", "STRICT", "RELAXED".
|
613 |
|
|
.CALIB_ROW_ADD (16'h0000),
|
614 |
|
|
// Calibration row address will be used for
|
615 |
|
|
// calibration read and write operations
|
616 |
|
|
.CALIB_COL_ADD (12'h000),
|
617 |
|
|
// Calibration column address will be used for
|
618 |
|
|
// calibration read and write operations
|
619 |
|
|
.CALIB_BA_ADD (3'h0),
|
620 |
|
|
// Calibration bank address will be used for
|
621 |
|
|
// calibration read and write operations
|
622 |
|
|
.TCQ (100),
|
623 |
|
|
.IODELAY_GRP ("MIG_7SERIES_0_IODELAY_MIG"),
|
624 |
|
|
// It is associated to a set of IODELAYs with
|
625 |
|
|
// an IDELAYCTRL that have same IODELAY CONTROLLER
|
626 |
|
|
// clock frequency.
|
627 |
|
|
.SYSCLK_TYPE ("NO_BUFFER"),
|
628 |
|
|
// System clock type DIFFERENTIAL or SINGLE_ENDED
|
629 |
|
|
.REFCLK_TYPE ("NO_BUFFER"),
|
630 |
|
|
// Reference clock type DIFFERENTIAL or SINGLE_ENDED
|
631 |
|
|
.CMD_PIPE_PLUS1 ("ON"),
|
632 |
|
|
// add pipeline stage between MC and PHY
|
633 |
|
|
.DRAM_TYPE ("DDR3"),
|
634 |
|
|
.CAL_WIDTH ("HALF"),
|
635 |
|
|
.STARVE_LIMIT (2),
|
636 |
|
|
// # = 2,3,4.
|
637 |
|
|
//***************************************************************************
|
638 |
|
|
// Referece clock frequency parameters
|
639 |
|
|
//***************************************************************************
|
640 |
|
|
.REFCLK_FREQ (200.0),
|
641 |
|
|
// IODELAYCTRL reference clock frequency
|
642 |
|
|
.DIFF_TERM_REFCLK ("TRUE"),
|
643 |
|
|
// Differential Termination for idelay
|
644 |
|
|
// reference clock input pins
|
645 |
|
|
//***************************************************************************
|
646 |
|
|
// System clock frequency parameters
|
647 |
|
|
//***************************************************************************
|
648 |
|
|
.tCK (3000),
|
649 |
|
|
// memory tCK paramter.
|
650 |
|
|
// # = Clock Period in pS.
|
651 |
|
|
.nCK_PER_CLK (4),
|
652 |
|
|
// # of memory CKs per fabric CLK
|
653 |
|
|
.DIFF_TERM_SYSCLK ("TRUE"),
|
654 |
|
|
// Differential Termination for System
|
655 |
|
|
// clock input pins
|
656 |
|
|
|
657 |
|
|
|
658 |
|
|
//***************************************************************************
|
659 |
|
|
// Debug parameters
|
660 |
|
|
//***************************************************************************
|
661 |
|
|
.DEBUG_PORT ("OFF"),
|
662 |
|
|
// # = "ON" Enable debug signals/controls.
|
663 |
|
|
// = "OFF" Disable debug signals/controls.
|
664 |
|
|
|
665 |
|
|
.RST_ACT_LOW (1)
|
666 |
|
|
// =1 for active low reset,
|
667 |
|
|
// =0 for active high.
|
668 |
|
|
)
|
669 |
|
|
//***************************************************************************
|
670 |
|
|
// end of section copied from mig_7series_0.voe
|
671 |
|
|
//***************************************************************************
|
672 |
|
|
mem0 (
|
673 |
|
|
// Memory interface ports
|
674 |
|
|
.ddr3_dq(ddr3_dq),
|
675 |
|
|
.ddr3_dqs_n(ddr3_dqs_n),
|
676 |
|
|
.ddr3_dqs_p(ddr3_dqs_p),
|
677 |
|
|
.ddr3_addr(ddr3_addr),
|
678 |
|
|
.ddr3_ba(ddr3_ba),
|
679 |
|
|
.ddr3_ras_n(ddr3_ras_n),
|
680 |
|
|
.ddr3_cas_n(ddr3_cas_n),
|
681 |
|
|
.ddr3_we_n(ddr3_we_n),
|
682 |
|
|
.ddr3_reset_n(ddr3_reset_n),
|
683 |
|
|
.ddr3_ck_p(ddr3_ck_p[0]),
|
684 |
|
|
.ddr3_ck_n(ddr3_ck_n[0]),
|
685 |
|
|
.ddr3_cke(ddr3_cke[0]),
|
686 |
|
|
.ddr3_dm(ddr3_dm),
|
687 |
|
|
.ddr3_odt(ddr3_odt[0]),
|
688 |
|
|
// Application interface ports
|
689 |
|
|
.app_addr( {1'b0, app_addr, 3'b000} ),
|
690 |
|
|
.app_cmd(app_cmd),
|
691 |
|
|
.app_en(app_en),
|
692 |
|
|
.app_rdy(app_rdy),
|
693 |
|
|
.app_wdf_rdy(app_wdf_rdy),
|
694 |
|
|
.app_wdf_data(app_wdf_data),
|
695 |
|
|
.app_wdf_mask({ APP_MASK_WIDTH {1'b0} }),
|
696 |
|
|
.app_wdf_end(app_wdf_wren), // always the last word in 4:1 mode
|
697 |
|
|
.app_wdf_wren(app_wdf_wren),
|
698 |
|
|
.app_rd_data(app_rd_data),
|
699 |
|
|
.app_rd_data_end(app_rd_data_end),
|
700 |
|
|
.app_rd_data_valid(app_rd_data_valid),
|
701 |
|
|
.app_sr_req(1'b0),
|
702 |
|
|
.app_sr_active(),
|
703 |
|
|
.app_ref_req(1'b0),
|
704 |
|
|
.app_ref_ack(),
|
705 |
|
|
.app_zq_req(1'b0),
|
706 |
|
|
.app_zq_ack(),
|
707 |
|
|
.ui_clk(uiclk),
|
708 |
|
|
.ui_clk_sync_rst(ui_clk_sync_rst),
|
709 |
|
|
.init_calib_complete(init_calib_complete),
|
710 |
|
|
.sys_rst(!reset),
|
711 |
|
|
// clocks inputs
|
712 |
|
|
.sys_clk_i(clk67),
|
713 |
|
|
.clk_ref_i(clk200)
|
714 |
|
|
);
|
715 |
|
|
|
716 |
|
|
assign mem_reset = reset || ui_clk_sync_rst || !init_calib_complete;
|
717 |
|
|
assign reset_out = reset_buf;
|
718 |
|
|
assign wr_mode = wr_mode_buf && app_wdf_rdy && !infifo_empty;
|
719 |
|
|
assign infifo_rden = app_rdy && wr_mode && !rd_mode;
|
720 |
|
|
|
721 |
|
|
assign status[0] = init_calib_complete;
|
722 |
|
|
assign status[1] = app_rdy;
|
723 |
|
|
assign status[2] = app_wdf_rdy;
|
724 |
|
|
assign status[3] = app_rd_data_valid;
|
725 |
|
|
assign status[4] = infifo_err;
|
726 |
|
|
assign status[5] = outfifo_err;
|
727 |
|
|
assign status[6] = outfifo_err_uf;
|
728 |
|
|
assign status[7] = wr_mode;
|
729 |
|
|
assign status[8] = rd_mode;
|
730 |
|
|
assign status[9] = !reset;
|
731 |
|
|
|
732 |
|
|
assign mem_free_out = mem_free;
|
733 |
|
|
|
734 |
|
|
always @ (posedge uiclk)
|
735 |
|
|
begin
|
736 |
|
|
// reset
|
737 |
|
|
reset_buf <= mem_reset;
|
738 |
|
|
|
739 |
|
|
// used for debuggig only
|
740 |
|
|
if ( reset_buf ) outfifo_err <= 1'b0;
|
741 |
|
|
else if ( outfifo_err_w ) outfifo_err <= 1'b1;
|
742 |
|
|
if ( reset_buf ) infifo_err <= 1'b0;
|
743 |
|
|
else if ( infifo_err_w ) infifo_err <= 1'b1;
|
744 |
|
|
|
745 |
|
|
// memory interface --> outfifo
|
746 |
|
|
if ( reset_buf )
|
747 |
|
|
begin
|
748 |
|
|
outfifo_err_uf <= 1'b0;
|
749 |
|
|
outfifo_pending <= 6'd0;
|
750 |
|
|
end else if ( app_rd_data_valid && !(rd_mode && app_rdy) )
|
751 |
|
|
begin
|
752 |
|
|
if ( outfifo_pending != 6'd0 )
|
753 |
|
|
begin
|
754 |
|
|
outfifo_pending = outfifo_pending - 6'd1;
|
755 |
|
|
end else
|
756 |
|
|
begin
|
757 |
|
|
outfifo_err_uf <= 1'b1;
|
758 |
|
|
end
|
759 |
|
|
end else if ( (!app_rd_data_valid) && rd_mode && app_rdy )
|
760 |
|
|
begin
|
761 |
|
|
outfifo_pending = outfifo_pending + 6'd1;
|
762 |
|
|
end
|
763 |
|
|
|
764 |
|
|
// wr_mode
|
765 |
|
|
if ( reset_buf )
|
766 |
|
|
begin
|
767 |
|
|
wr_mode_buf <= 1'b0;
|
768 |
|
|
end else if ( infifo_empty || (!app_wdf_rdy) || wr_cnt[7] || ( mem_free[APP_ADDR_WIDTH:1] == {APP_ADDR_WIDTH{1'b0}} ) ) // at maximum 128 words
|
769 |
|
|
begin
|
770 |
|
|
wr_mode_buf <= 1'b0;
|
771 |
|
|
end else if ( (!rd_mode) && !infifo_almost_empty && (mem_free[APP_ADDR_WIDTH:5] != {(APP_ADDR_WIDTH-4){1'b0}}) ) // at least 32 words
|
772 |
|
|
begin
|
773 |
|
|
wr_mode_buf <= 1'b1;
|
774 |
|
|
end
|
775 |
|
|
|
776 |
|
|
// rd_mode
|
777 |
|
|
if ( reset_buf )
|
778 |
|
|
begin
|
779 |
|
|
rd_mode <= 1'b0;
|
780 |
|
|
end else if ( rd_mode || outfifo_almost_full || (outfifo_pending == 6'd31) || rd_cnt[7] || ( mem_free[APP_ADDR_WIDTH-1:0] == {(APP_ADDR_WIDTH){1'b1}}) || mem_free[APP_ADDR_WIDTH] ) // at maximum 128 words )
|
781 |
|
|
begin
|
782 |
|
|
rd_mode <= 1'b0;
|
783 |
|
|
end else if ( (!wr_mode_buf) && (outfifo_pending == 6'd0) && (mem_free[APP_ADDR_WIDTH-1:5] != {(APP_ADDR_WIDTH-5){1'b1}}) ) // at least 32 words
|
784 |
|
|
begin
|
785 |
|
|
rd_mode <= 1'b1;
|
786 |
|
|
end
|
787 |
|
|
|
788 |
|
|
if ( reset_buf )
|
789 |
|
|
begin
|
790 |
|
|
rd_cnt_dbg <= 10'd0;
|
791 |
|
|
end else if ( app_rd_data_valid )
|
792 |
|
|
begin
|
793 |
|
|
rd_cnt_dbg <= rd_cnt_dbg + 1;
|
794 |
|
|
end;
|
795 |
|
|
|
796 |
|
|
// command generator
|
797 |
|
|
if ( reset_buf )
|
798 |
|
|
begin
|
799 |
|
|
app_en <= 1'b0;
|
800 |
|
|
mem_wr_addr <= {APP_ADDR_WIDTH{1'b0}};
|
801 |
|
|
mem_rd_addr <= {APP_ADDR_WIDTH{1'b0}};
|
802 |
|
|
mem_free <= {1'b1, {APP_ADDR_WIDTH{1'b0}}};
|
803 |
|
|
wr_cnt <= 8'd0;
|
804 |
|
|
rd_cnt <= 8'd0;
|
805 |
|
|
end else if ( app_rdy )
|
806 |
|
|
begin
|
807 |
|
|
if ( rd_mode )
|
808 |
|
|
begin
|
809 |
|
|
app_cmd <= 3'b001;
|
810 |
|
|
app_en <= 1'b1;
|
811 |
|
|
app_addr <= mem_rd_addr;
|
812 |
|
|
mem_rd_addr <= mem_rd_addr + 1;
|
813 |
|
|
rd_cnt <= rd_cnt + 1;
|
814 |
|
|
wr_cnt <= 8'd0;
|
815 |
|
|
mem_free <= mem_free + 1;
|
816 |
|
|
end else if ( wr_mode )
|
817 |
|
|
begin
|
818 |
|
|
app_cmd <= 3'b000;
|
819 |
|
|
app_en <= 1'b1;
|
820 |
|
|
app_addr <= mem_wr_addr;
|
821 |
|
|
app_wdf_data <= infifo_do;
|
822 |
|
|
// app_wdf_data <= { 8{mem_wr_addr[15:0]} };
|
823 |
|
|
// app_wdf_data <= { {7{mem_wr_addr[15:0]}}, infifo_do[71:64], infifo_do[7:0] };
|
824 |
|
|
mem_wr_addr <= mem_wr_addr + 1;
|
825 |
|
|
mem_free <= mem_free - 1;
|
826 |
|
|
wr_cnt <= wr_cnt + 1;
|
827 |
|
|
rd_cnt <= 8'd0;
|
828 |
|
|
end else
|
829 |
|
|
begin
|
830 |
|
|
app_en <= 1'b0;
|
831 |
|
|
wr_cnt <= 8'd0;
|
832 |
|
|
rd_cnt <= 8'd0;
|
833 |
|
|
end
|
834 |
|
|
end
|
835 |
|
|
|
836 |
|
|
if ( reset_buf )
|
837 |
|
|
begin
|
838 |
|
|
app_wdf_wren <= 1'b0;
|
839 |
|
|
// infifo_rden <= 1'b0;
|
840 |
|
|
end else if ( app_rdy && (!rd_mode) && wr_mode )
|
841 |
|
|
begin
|
842 |
|
|
app_wdf_wren <= 1'b1;
|
843 |
|
|
// infifo_rden <= 1'b1;
|
844 |
|
|
end else
|
845 |
|
|
begin
|
846 |
|
|
if ( app_wdf_rdy ) app_wdf_wren <= 1'b0;
|
847 |
|
|
// infifo_rden <= 1'b0;
|
848 |
|
|
end
|
849 |
|
|
|
850 |
|
|
|
851 |
|
|
end
|
852 |
|
|
|
853 |
|
|
endmodule
|